Strong dependence of the inversion mobility of 4H and 6H SiC(0001)MOSFETs on the water content in pyrogenic re-oxidation annealing

The inversion channel mobility of 4H and 6H-SiC(0001) metal-oxide-semiconductor field-effect transistors (MOSFETs) has been evaluated for its dependence on the re-oxidation annealing (ROA) conditions in a wet oxidizing ambient. The wet ambient was supplied by the pyrogenic reaction of hydrogen and oxygen gas (pyrogenic ROA), where the water vapor content (ρ(H₂O)) was controlled by adjusting the hydrogen/oxygen gas flow rate. Not only the annealing temperature and the time, but also ρ(H₂O) are found to be the critical parameters for improving channel mobility. As a result, field-effect channel mobilities as high as 47 cm²/Vs for 4H and 95 cm²/Vs for 6H-SiC MOSFETs were achieved by pryrogenic ROA treatment with a ρ(H₂O) of 50%     

Accumulation-layer electron mobility in n-channel 4H-SiC MOSFETs

Accumulation-layer electron mobility in n-channel depletion-mode metal oxide semiconductor field effect transistors (MOSFETs) fabricated in 4H-SiC was investigated using Hall-measurements. The accumulation-layer mobility showed a smooth transition from the bulk value (~350 cm²/V-s) in the depletion regime into accumulation (~200 cm²/V-s). In contrast, the field-effect mobility, extracted from the transconductance, was found to be much lower (~27 cm²/V-s), due to the trapping of the field-induced carriers by interface states. Though the current in depletion/accumulation-mode MOSFETs can be high due to the contribution of bulk conduction resulting in low on-resistance, carrier trapping will cause the transconductance to be low in the accumulation regime     

Electron mobility models for 4H, 6H, and 3C SiC [MESFETs]

Models for the electron mobility in the three most important silicon carbide (SiC) polytypes, namely, 4H, 6H, and 3C SiC are developed. A large number of experimental mobility data and Monte Carlo (MC) results reported in the literature have been evaluated and serve as the basis for the model development. The proposed models describe the dependence of the electron mobility on doping concentration, temperature, and electric field. The low-field mobility in 4H SiC is much higher than in 6H and 3C in the doping range interesting for RF power transistors (10¹⁶ cm^-3 ...10¹⁸ cm ^-3), whereas the saturation velocities in the three polytypes investigated are nearly the same (slightly above 2×10⁷ cm/s at 300 K). The models developed can be easily incorporated into numerical device simulators     

Normally-off 4H-SiC trench-gate MOSFETs with high mobility

A new 4H-SiC trench-gate MOSFET structure with epitaxial buried channel for accumulation-mode operation, has been designed and fabricated, aiming at improving channel electron mobility. Coupled with improved fabrication processes, the MOSFET structure eliminates the need of high dose N⁺ source implantation. High dose N⁺ implantation requires high-temperature (1550 °C) activation annealing and tends to cause substantial surface roughness, which degrades MOSFET threshold voltage stability and gate oxide reliability. The buried channel is implemented without epitaxial regrowth or accumulation channel implantation. Fabricated MOSFETs subject to ohmic contact rapid thermal annealing at 850 °C for 5 min exhibit a high peak field-effect mobility (μ_FE) of 95 cm²/V s at room temperature (25 °C) and 255 cm²/V s at 200 °C with stable normally-off operation from 25 °C to 200 °C. The dependence of channel mobility and threshold voltage on the buried channel depth is investigated and the optimum range of channel depth is reported.     

A field-effect electron mobility model for SiC MOSFETs including high density of traps at the interface

Besides its favorable physical properties, high performant MOSFETs (metal-oxide-semiconductor field-effect transistors) fabrication in silicon carbide (SiC) remains an open issue due to their low channel mobility values. The effect of charge trapping and the scattering at interface states have been invoked as the main reasons for mobility reduction in SiC thermal oxidized MOS gated devices. In this paper, we propose a compact electron mobility model based on the well-established Lombardi mobility model to reproduce the mobility degradation commonly observed in these SiC devices. Using 2D electrical simulations along with the proposed model and taking into account interface traps Coulomb scattering, the experimental field-effect mobility of 4H-SiC MOSFET devices has been fitted with a good agreement.     

Status and prospects for SiC power MOSFETs

SiC electronic device technology has made rapid progress during the past decade. In this paper, we review the evolution of SiC power MOSFETs between 1992 and the present, discuss the current status of device development, identify the critical fabrication issues, and assess the prospects for continued progress and eventual commercialization     

High channel mobility in normally-off 4H-SiC buried channel MOSFETs

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500°C. The optimum doping depth of the BC region has been investigated. For a nitrogen concentration of 1×10¹⁷ cm^-3, the optimum depth was found to be 0.2 μm. Under this condition, a channel mobility of 140 cm²/Vs was achieved with a threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide     

SiC JBS二极管和SiC MOSFET的空间辐照效应及机理

基于第六代650 V碳化硅结型肖特基二极管(SiC JBS Diode)和第三代900 V碳化硅场效应晶体管(SiC MOSFET),开展SiC功率器件的单粒子效应、总剂量效应和位移损伤效应研究。20～80 MeV质子单粒子效应实验中,SiC功率器件发生单粒子烧毁(SEB)时伴随着波浪形脉冲电流的产生,辐照后SEB器件的击穿特性完全丧失。SiC功率器件发生SEB时的累积质子注量随偏置电压的增大而减小。利用计算机辅助设计工具(TCAD)开展SiC MOSFET的单粒子效应仿真,结果表明,重离子从源极入射器件时,具有更短的SEB发生时间和更低的SEB阈值电压。栅-源拐角和衬底-外延层交界处为SiC MOSFET的SEB敏感区域,强电场强度和高电流密度的同时存在导致敏感区域产生过高的晶格温度。SiC MOSFET在栅压偏置(U_GS=3 V,U_DS=0 V)下开展钴源总剂量效应实验,相比于漏压偏置(U_GS=0 V,U_DS=300 V)和零压偏置(U_GS=U_DS=0...     

Improved inversion channel mobility for 4H-SiC MOSFETs followinghigh temperature anneals in nitric oxide

Results presented in this letter demonstrate that the effective channel mobility of lateral, inversion-mode 4H-SiC MOSFETs is increased significantly after passivation of SiC/SiO₂ interface states near the conduction band edge by high temperature anneals in nitric oxide. Hi-lo capacitance-voltage (C-V) and ac conductance measurements indicate that, at 0.1 eV below the conduction band edge, the interface trap density decreases from approximately 2×10¹³ to 2×10¹² eV^-1 cm^-2 following anneals in nitric oxide at 1175°C for 2 h. The effective channel mobility for MOSFETs fabricated with either wet or dry oxides increases by an order of magnitude to approximately 30-35 cm²/V-s following the passivation anneals     

Measurement considerations for evaluating BTI effects in SiC MOSFETs

In this paper, we review the phenomenon of bias-temperature instability (BTI) in SiC MOS devices, with an emphasis on the effects of metrology. The complex behavior of the charge trapping mechanism responsible for V_T instability requires careful consideration of measurement conditions and precise control of the associated parameters to produce meaningful results. Preconditioning the devices to be tested, as well as making faster measurements, will elicit the truest response. Any bias interruption or delay between stressing and measurement will produce a large deterioration in the original V_T drift caused by the stressing, though this can be effectively counteracted by briefly reapplying the stress bias before measurement.     

Impact of the gate driver voltage on temperature sensitive electrical parameters for condition monitoring of SiC power MOSFETs

Condition monitoring using temperature sensitive electrical parameters (TSEPs) is widely recognized as an enabler for health management of power modules. The on-state resistance/forward voltage of MOSFETs, IGBTs and diodes has already been identified as TSEPs by several researchers. However, for SiC MOSFETs, the temperature sensitivity of on-state voltage/resistance varies depending on the device and is generally not as high as in silicon devices. Recently the turn-on current switching rate has been identified as a TSEP in SiC MOSFETs, but its temperature sensitivity was shown to be significantly affected by the gate resistance. Hence, an important consideration regarding the use of TSEPs for health monitoring is how the gate driver can be used for improving the temperature sensitivity of determined electrical parameters and implementing more effective condition monitoring strategies. This paper characterizes the impact of the gate driver voltage on the temperature sensitivity of the on-state resistance and current switching rate of SiC power MOSFETs. It is shown that the temperature sensitivity of the switching rate in SiC MOSFETs increases if the devices are driven at lower gate voltages. It is also shown, that depending on the SiC MOSFET technology, reducing the gate drive voltage can increase the temperature sensitivity of the on-state resistance. Hence, using an intelligent gate driver with the capability of customizing occasional switching pulses for junction temperature sensing using TSEPs, it would be possible to implement condition monitoring more effectively for SiC power devices.     

Flicker noise in MOSFETs with gate-voltage-dependent mobility

Flicker noise measurements in MOSFETs at low drain bias are explained in terms of the dependence of the carrier mobility on the gate voltage of the form μ₀₀[1 + β(V_G ? V_T ? V₀)]^?1. Excellent agreement, both for the (I_d, V_g) characteristic and for the flicker noise, is obtained. The noise current spectrum is expressed in the normalized functions f(y₀, y₁) and f(y₀, y₁)/y₀ in terms of the bias parameters y₀ = β(V_g ? V_T) and y₁ = β(V_g ? V_T ? V_d).     

A semi-empirical model for the field-effect mobility ofhydrogenated polycrystalline-silicon MOSFETs

The quantitative relationship between field-effect mobility (μ _FE) and grain-boundary trap-state density (N_t ) in hydrogenated polycrystalline-silicon (poly-Si) MOSFETs is investigated. The focus is on the field-effect mobility in MOSFETs with N_t 1×10² cm^-2. It is found that reducing N_t to as low as 5×10¹¹ cm^-2 has a great impact on μ_FE. MOSFETs with the N_t of 4.2×10¹¹ cm^-2 show an electron mobility of 185 cm²/V-s, despite a mean grain size of 0.5 μm. The three principal factors that determine μ_FE, namely, the low-field mobility, the mobility degradation factor, and the trap-state density N_t are clarified     

p-channel germanium MOSFETs with high channel mobility

The fabrication and performance of p-channel germanium MOSFETs having a nitrided native oxide gate insulator are reported. A self-aligned dummy-gate process suitable for circuit integration is utilized. Common-source characteristics exhibit no looping and indicate a peak room-temperature channel mobility of 770 cm²/V-s. These results provide further evidence that a high-performance germanium CMOS technology is possible     

Low-temperature electron mobility in Trigate SOI MOSFETs

Evidence of one-dimensional subband formation is found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the I/sub D/(V/sub G/) characteristics. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased. High mobility, reaching 1200 cm/sup 2//Vs, is measured in the subbands at T=4.4 K. Subband mobility decreases as temperature is increased. Conduction in subbands disappears for temperatures higher than 100 K or for drain voltage values that are significantly larger than kT/q.     

SiC MOS器件界面钝化研究进展

从氧化后退火处理、氮化处理、碳帽、钡夹层、淀积氧化物后退火处理五个方面介绍了碳化硅钝化工艺.通过改进钝化工艺可以有效降低界面态密度.针对这几种钝化工艺对SiC/SiO2界面态密度的影响进行讨论,分析几种钝化工艺的优劣,并重点介绍了氧化后退火处理和氮化处理两种钝化方法.研究发现,NO氮化工艺能有效降低界面态密度,提高界面...     

Observation of mobility enhancement in ultrathin SOI MOSFETs

The mobility in n-channel SOI MOSFETs exhibits a significant increase as the SOI film becomes thinner than 1000 Å. At a 500 Å SOI thickness, the mobility values are distributed in the 700-1100 cm²/Vs range, which are obviously higher than the value in a bulk MOSFET having an identical doping concentration. The observed mobility enhancement has been explained by a decrease in the vertical electric field, associated with the complete depletion of the SOI film     

Edge termination strategies for a 4 kV 4H–SiC thyristor

Thyristors able to block 4 kV have been fabricated and characterised. The experimental forward current is 1.3 A @ V_AK = 10 V for a 9 mA gate current during 550 ns. The device active area is 2.3 mm². The devices and their edge terminations have been designed using numerical simulations. Two different edge terminations have been envisaged (mesa and a combination of mesa and JTE). A SiO₂ passivation layer also improves the forward blocking voltage depending on the sign and the magnitude of the effective charge density in the oxide. The mesa protection is not enough to allowing the thyristor to block 5 kV, due to the low etching rate in SiC. Thus, a mesa/JTE protection has been used. The influence of the etching depth, the JTE dose and length on the forward blocking voltage of the thyristor has been studied in details. Simulation results have allowed designing the devices, not far from the optimal structure. The best results of the forward blocking voltage are 4 kV for the mesa protected thyristor, while the mesa/JTE combination yields 3.6 kV. Furthermore, experimental results confirm the simulations concerning the influence of the oxide thickness on the forward blocking voltage. The better results for the mesa protected thyristor are due to a lower interface SiC/SiO₂ charge density provided by the different oxidation processes (at different foundries).In addition, the comparison between experiments and simulations allows estimate the effective charge density of the SiO₂ layer in 10¹²–5 × 10¹² cm⁻² range for the two fabricated thyristors. The improvement in the forward blocking voltage must pass through an improvement of the passivation layer. Passivation still remains a technological key step to obtain SiC high-voltage devices.     

基于Matlab/Simulink的SiC MOSFET建模与分析

针对现阶段SiC MOSFET建模研究无法应用在电机控制系统领域的现状,提出了一种基于Matlab/Simulink的SiC MOSFET仿真电路模型。对功率器件的动态特性和静态特性进行综合分析,采用非分段受控电流源模型模拟功率器件静态特性,具体分析SiC MOSFET的开关过程,同时采用曲线拟合的方法对影响器件开关过程的非线性电容进行表征,在Matlab/Simulink中建立SiC MOSFET等效电路模型。为了验证模型准确性,将仿真结果与数据手册中的数据进行比较分析,仿真结果表明所建模型可以较为准确地描述SiC MOSFET动、静态特性,开通时间和关断时间误差均小于7%,对比结果验证了模型的准确性和有效性。建立的模型为SiC MOSFET在电机控制策略仿真及应用领域提供了参考依据。