Offset-compensated switched-capacitor circuits

Novel switched-capacitor circuits are described which make the offset-compensation possible without short-circuiting the input and output terminals of op amps. Based on a common configuration, the proposed circuits are useful for basic building blocks integrable using the semicustom IC process.     

MOS switched-capacitor filters

In the past several years, much progress has been made in bringing the economies of integrated-circuit technology to bear on the realization of voiceband frequency selective filters. This paper will review one approach to this problem, the use of switched-capacitor techniques. The paper emphasizes the practical aspects of switched-capacitor filter design under the constraints imposed by MOS integrated-circuit technology. The basic operation of switched-capacitor filters is reviewed, followed by a discussion of the properties of the various circuit building blocks in MOS technology. Finally, a summary of several filter organizations which appear to be well suited to switched-capacitor implementation is presented.     

Testable switched-capacitor filters

A design-for-testability (DFT) methodology for switched-capacitor (SC) filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and online test. A programmable biquad is used for on-chip comparison of the transfer functions for every filter stage. Test area overhead consists of the programmable biquad, a set of switches, and a finite-sequential-machine (FSM) control part. The design and implementation of an example filter are included to assess the potential usefulness of this approach     

New switched-capacitor ladder filters

A method is described and implemented for the derivation of switched-capacitor discrete-time filters from analogue passive filters of the ladder doubly terminated kind. The method is based on linear transformation active (LTA) synthesis, and yields some very interesting results.     

Pseudopower in switched-capacitor filters

The concepts of pseudopower, pseudopassivity, and pseudolosslessness are introduced in connection with switched-capacitor filters employing voltage invertor switches. With such concepts the verification of the low sensitivity and stability properties is straightforward.     

New switched-capacitor immittance converter using operational amplifier leapfrog structure

A new switched-capacitor immittance converter is obtained from the operational amplifier leapfrog structure which simulates a grounded inductor. Any capacitive (n + 1)-terminal network which has a capacitance matrix can be converted into the corresponding inductive network by using a set of these n immittance converters.     

Parasitics-insensitive switched-capacitor ladder filters

A simple method for designing parasitics-insensitive switched-capacitor (s.c.) ladder filters is described. The response of the s.c. filter is related to that of a continuous-time prototype circuit by the bilinear z-transform.     

Stability test for switched-capacitor filters

A general stability test is described which may be employed in the analysis of all switched-capacitor filters of the lossless discrete integrator (LDI) type.     

CMOS high-frequency switched-capacitor filters fortelecommunication applications

A digitally programmable high-frequency switched-capacitor filter for use in a switched digital video (SDV/VDSL) link is described. The highest available clock frequency in the system is 51.84 MHz (f_s =2f_clock=103.68 MHz for double sampling) while the three desired low-pass corner frequencies (f_c) are 8,12, and 20 MHz. The double-sampling, bilinear, elliptic, fifth-order switched-capacitor filter meets the desired -40-dB attenuation at 1.3 f _c, and -30 dB at 1.25 f_c. For the 12-MHz corner frequency setting, given the 2V_pp differential input, the measured worst case total harmonic distortion is -60 dB, with signal-to-noise ratio of 54 dB. The analog power dissipation is 125 mW from a 5-V power supply. The test results indicate that the clock frequency can be increased to 73 MHz without any ill effects. More measurements verify that an all-digital CMOS implementation, utilizing metal-sandwich capacitors, performs as well as the special-layer analog capacitors implementation, with a small reduction in the absolute corner frequencies. The prototype IC's are fabricated in a 0.35-μm 5-V (0.48 μm drawn) CMOS process     

A single-chip codec with switched-capacitor filters

A single-chip CMOS codec with filters has been developed using charge redistribution and switched-capacitor techniques. Its features are ~30 mm/SUP 2/ small chip area, 35 mW low power dissipation, and small 16 pin package. These are achieved with novel analog circuit techniques for A/D and D/A conversions and clock generation. Measured transmission characteristics meet the system requirements.     

Improving the testability of switched-capacitor filters

A design-for-test methodology for SC filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off-and on-line tests. The approach uses a comparison (voting) mechanism to indicate whether or not two copies of a filter element (a biquad, for instance) have a similar response during their actual operation. The design and implementation of a few filter examples are included to assess the potential usefulness of this new approach.     

Parasitics-compensated building blocks for switched-capacitor filters

A switched-capacitor voltage-controlled charge source with differential outputs and a switched-capacitor differential integrator are proposed. The proposed circuits are parasitics insensitive, and can be operated using only a two-phase clock.     

Improving the testability of switched-capacitor filters

A design-for-test methodology for SC filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and on-line tests. The approach uses a comparison (voting) mechanism to indicate whether or not two copies of a filter element (a biquad, for instance) have a similar response during their actual operation. The design and implementation of a few filter examples are included to assess the potential usefulness of this new approach.     

Power-supply rejection in differential switched-capacitor filters

The principal motivation of using a fully differential configuration is to reduce power supply coupling. For this reason, an analysis of some of the mechanisms associated with this effect and the usefulness of some forms of common mode feedback are discussed. Experimental results obtained from a CMOS integrated circuit realization are also included. The circuit achieves 50 dB of power supply rejection ratio across the passband.     

Ladder-simulation switched-capacitor filters with inductor loops

In ladder-simulation switched-capacitor filters, offset voltages of the op-amps can cause the output simulating inductor currents to build up if the LC prototype contains an inductor loop. This problem is eliminated by a novel technique where the sum of inductor currents flowing into each node is simulated by one op-amp output.     

Offset-compensated switched-capacitor delay circuit that is insensitive to stray capacitance and to capacitor mismatch

A switched-capacitor delay circuit that is offset-compensated and insensitive to stray capacitance and to capacitor mismatch is proposed. It uses a four-phase clock and contains a single operational amplifier, two capacitors and seven switches. A delay line composed of such building blocks requires only two operational amplifiers per three delay sections and two clock phases per sample.<>     

Biquad alternatives for high-frequency switched-capacitor filters

Biquad sections are the basic building block of practical switched-capacitor (SC) filters. The authors focus on the amenability of various biquad options for high-frequency operation. A comparison on the basis of analysis and a recent nonideal SC network simulation tool are confirmed by results from a VLSI 1.25-/spl mu/m CMOS test chip. A differencing-input SC biquad is shown to have a significant performance advantage over other circuits.     

Synthesis of highpass switched-capacitor LDI filters

Exact techniques are given for the design of highpass LDI switched-capacitor ladder filters. The filters have no lumped counterparts and cannot be obtained from a lumped prototype by a transformation. Only stray-insensitive circuits are employed in the realisation, and the filters retain the lowsensitivity properties of a passive (distributed) prototype function.     

Sequential voltage-inversion principle for switched-capacitor filters

For a special class of switched-capacitor filters, voltage-inverter switches are needed. It is shown how several voltage-inverter switches can be realised using only one operational amplifier.     

Tuning of leapfrog multiple loop feedback bandpass filters

Off-line tuning of leapfrog multiple loop feedback bandpass filters is demonstrated using a modification of Dishal's method. The proposed method has advantages including simplified tuning circuits and algorithms, minimal additional circuit parasitics and suitability for high frequency applications