共查询到12条相似文献,搜索用时 46 毫秒
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宽度窄、幅度大的脉冲生成是探地雷达系统中要解决的关键问题之一.本文在比较了几种不同实现电路的优缺点,详细分析了雪崩三极管原理的基础,提出利用雪崩三极管的雪崩特性,实现超宽带、窄脉冲的生成.文中给出了电路原理图和实验结果,电路分为正、负脉冲2部分,可生成底宽为纳/亚纳秒级、正、负脉冲的峰-峰值高达160 V的窄脉冲信号,并且脉冲拖尾的振荡起伏小,很好地满足了雷达系统的宽度窄、幅度大的要求.电路结构简单、参数可调、移植性强、适用范围广. 相似文献
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高幅度窄脉冲时域脉冲信号源及超宽带低振铃时域脉冲天线是脉冲探地雷达(ground-penetrating radar,GPR)的关键部件。本文通过挖槽技术有效的减少了电磁辐射干扰,设计并研制了脉冲幅度为156.2V,脉冲宽度为1.6ns的MARX级联脉冲信号源。同时首次提出了半圆形天线臂电阻加载天线,相比于传统三角形天线臂电阻加载天线,0.5-7GHz带宽内驻波系数控制在3.5以内,天线时域脉冲的拖尾幅度由17.5%下降到8.3%,具有超宽带、低振铃的特点。最终开展了隐藏目标的探测实验,雷达探测结果成像清晰、浅层目标分辨率高,有力的验证了本文所研究的脉冲探地雷达前端探测子系统的优越性能及潜在的使用价值。 相似文献
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为实现探地雷达小型化和数字化的设计,对伪随机编码探地雷达的系统设计方案进行了研究。该文研制了一款双通道伪随机编码超宽带探地雷达主控机。研究基于FPGA芯片Virtex-5和宇航级ADC芯片ADS5463-SP,采用码元平衡直发的信号源设计方案,配合混合采样实现了中心频率60MHz和800MHz的双通道格雷互补码编码信号的发射和接收。进行了信号源测试实验和主控机的闭环测试实验,双通道脉冲压缩结果峰值旁瓣比均大于25dB,并达到了低频1.875m和高频11.72cm的距离分辨率。将主控机接入雷达系统,在沙坑中进行雷达整机的高频通道测试实验,测得埋藏大理石板厚度约17cm。结果表明该文设计的雷达主控机性能可靠,可以广泛应用于伪随机编码体制超宽带探地雷达系统。 相似文献
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铁路建设中常需在铁路两侧构筑挡土墙对铁轨进行保护,因此挡土墙施工质量对铁路具有重要意义.为了获得更有效的挡土墙质检数据,常用探地雷达(ground penetrating radar,GPR)进行质检.结合理论分析了电磁波在地下非均匀介质边界的反射和衍射特性,结果表明回波噪声呈二维分布.对仿真回波二维加噪后,对比二维中值和一维自适应(1D-LMS)算法滤波效果,仿真结果表明二维处理明显优于一维.为适应GPR回波信号的非线性特征,选取二维自适应(2D-LMS)算法对回波信号进行处理,并与二维中值滤波相比较.广东省某铁路挡土墙实测数据处理结果表明,2D-LMS算法滤波信号具有更高信噪比,能更有效地去除噪声,使回波图像更加清晰. 相似文献
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This paper presents a circuit modeling procedure for Ultra‐wideband (UWB) Tx‐Rx antenna systems based on frequency domain S‐parameters. The modeling used an existing two‐port network's model consisting of four SPICE analog behavioral modules. The accuracy of the model has been validated by comparing its transient response with the measurement result using an oscillograph. This model can be used for the co‐design of the UWB Tx‐Rx antenna system with transmitters and receivers in circuit simulators. In the study, Tx‐Rx antenna systems using planar bow‐tie antenna and horn antenna with ultra‐wide bandwidths are used as examples. Copyright © 2010 John Wiley & Sons, Ltd. 相似文献
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Ahmed M. El‐Gabaly Carlos E. Saavedra 《International Journal of Circuit Theory and Applications》2013,41(2):150-167
A new energy‐efficient tunable pulse generator is presented in this paper using 0.13‐µm CMOS technology for short‐range high‐data‐rate 3.1–10.6 GHz ultra‐wideband applications. A ring oscillator consisting of current‐starved CMOS inverters is quickly switched on and off for the duration of the pulse, and the amplitude envelope is shaped with a variable passive CMOS attenuator. The variable passive attenuator is controlled using an impulse that is created by a low‐power glitch generator (CMOS NOR gate). The glitch generator combines the falling edge of the clock and its delayed inverse, allowing the duration of the impulse to be changed over a wide range (500–900 ps) by varying the delay between the edges. The pulses generated with this technique can provide a sharp frequency roll off with high out‐of‐band rejection to help meet the Federal Communications Commission mask. The entire circuit operates in switched mode with a low average power consumption of less than 3.8 mW at 910 MHz pulse repetition frequency or below 4.2 pJ of energy per pulse. It occupies a total area of 725 × 600 µm2 including bonding pads and decoupling capacitors, and the active circuit area is only 360 × 200 µm2. Copyright © 2011 John Wiley & Sons, Ltd. 相似文献