高真空化学气相外延炉的研制

研制出满足Ｓｉ１－ｘＧｅｘ异质结薄膜材料生长工艺的高真空化学气相外延炉,介绍了Ｓｉ１－ｘＧｅｘ异质结薄膜材料的生长工艺,详述了该气相外延设备的性能指标、结构组成和设计原理,并且给出了利用该设备生长Ｓｉ１－ｘＧｅｘ异质薄膜的实验结果。     

Kinetic lattice Monte Carlo simulations of silicon and germanium epitaxial growth on the silicon (100) surface

We present kinetic lattice Monte Carlo simulations of epitaxial growth of Si and Ge films on the Si (100) surface. Our simulations take into account surface reconstruction, in particular, how it makes the diffusion properties of ad-dimers and adatoms on the surface depend on the direction of motion and whether they are moving over a row or a trough. In the case of Ge expitaxial growth, when dealing with growth of Ge films, we incorporated the effect of Ge-Si exchange through a mechanism involving the ad-dimers. This results in a significant fraction of the first epitaxial layer containing Si, with an abrupt increase at one monolayer of coverage.     

Coupled effects of ion beam chemistry and morphology on directed self-assembly of epitaxial semiconductor nanostructures

We study the coupled effects of ion beam chemistry and morphology on the assembly of templated epitaxial nanostructures. Using a focused ion beam (FIB) system equipped with a mass-selecting filter, we pattern Si substrates with local ion doses of Si, Ge and Ga to control subsequent Ge(x)Si(1 - x) epitaxial nanostructure assembly. This capability to employ different templating species allows us to study how different incorporated ion species in the near surface region affect the ability to localize nucleation during subsequent epitaxial growth. Our results indicate that FIB-directed self-assembly is a complex process, dependent on dose-induced morphology in addition to ion-specific chemical effects.     

Atomically controlled processing in silicon-based CVD epitaxial growth

One of the main requirements for Si-based ultrasmall device is atomic-order control of process technology. Here, we show the concept of atomically controlled processing for group IV semiconductors based on atomic-order surface reaction control in Si-based CVD epitaxial growth. Self-limiting formation of 1-3 atomic layers of group IV or related atoms after thermal adsorption and reaction of hydride gases on Si(1-x)Gex(100) (x = 0-1) surface are generalized based on the Langmuir-type model. Moreover, Si-based epitaxial growth on N, P or C atomic layer formed on Si(1-x)Gex(100) surface is achieved at temperatures below 500 degrees C. N atoms of about 4 x 10(14) cm(-2) are buried in the Si epitaxial layer within about 1 nm thick region. In the Si(0.5)Ge(0.5) epitaxial layer, N atoms of about 6 x 10(14) cm(-2) are confined within about 1.5 nm thick region. The confined N atoms in Si(1-x)Gex preferentially form Si-N bonds. For unstrained Si cap layer grown on top of the P atomic layer formed on Si(1-x)Gex(100) with P atomic amount of below about 4 x 10(14) cm(-2) using Si2H6 instead of SiH4, the incorporated P atoms are almost confined within 1 nm around the heterointerface. It is found that tensile-strain in the Si cap layer growth enhances P surface segregation and reduces the incorporated P atomic amount around the heterointerface. Heavy C atomic-layer doping suppresses strain relaxation as well as intermixing between Si and Ge at the nm-order thick Si(1-x)Gex/Si heterointerface. These results open the way to atomically controlled technology for ULSIs.     

体硅上外延超薄Si1-xGex用于制备SGOI材料

采用减压化学气相沉积的方法在Si衬底上制备了高质量的Si0.75Ge0.25/Si/Si0.86Ge0.14叠层材料,通过TEM、光学显微镜和XRD分析表明,外延的SiGe薄膜具有完好的晶格结构,平整的表面质量,SiGe薄膜处于完全应变状态.通过与Si上外延渐变缓冲层制备的SiGe材料比较发现,使用这种超薄的全应变Si...     

The Reliability of Revealing Threading Dislocations in Epitaxial Films by Structure-Sensitive Etching

Correspondence between threading dislocations (TDs) in epitaxial films and the etch pits observed upon selective chemical etching of the samples was studied in Ge/Si(001) heterostructures. It is established that the density of TDs revealed in epitaxial films with thicknesses h ≤ 1 μm can be significantly understated because of insufficient resolution of optical microscopy. Recommendations are given that increase the reliability of PD density estimation by means of structure-sensitive etching.     

Ge-rich islands grown on patterned Si substrates by low-energy plasma-enhanced chemical vapour deposition

Si(1-x)Ge(x) islands grown on Si patterned substrates have received considerable attention during the last decade for potential applications in microelectronics and optoelectronics. In this work we propose a new methodology to grow Ge-rich islands using a chemical vapour deposition technique. Electron-beam lithography is used to pre-pattern Si substrates, creating material traps. Epitaxial deposition of thin Ge films by low-energy plasma-enhanced chemical vapour deposition then leads to the formation of Ge-rich Si(1-x)Ge(x) islands (x > 0.8) with a homogeneous size distribution, precisely positioned with respect to the substrate pattern. The island morphology was characterized by atomic force microscopy, and the Ge content and strain in the islands was studied by μRaman spectroscopy. This characterization indicates a uniform distribution of islands with high Ge content and low strain: this suggests that the relatively high growth rate (0.1 nm s(-1)) and low temperature (650?°C) used is able to limit Si intermixing, while maintaining a long enough adatom diffusion length to prevent nucleation of islands outside pits. This offers the novel possibility of using these Ge-rich islands to induce strain in a Si cap.     

Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 10⁷ cm^− 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III-V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.     

Molecular beam epitaxial growth of germanium and silicon films: Surface structure,film defects and properties

Germanium and silicon films were grown on substrates of silicon (germanium and silicon films) and gallium arsenide (germanium films). Reflection high energy electron diffraction was used to investigate superstructure reconstructions on the growth surface as a function of the growth temperature and the film thickness. The greatest number of superstructures was observed during epitaxy of germanium films on Si(111): Si(7 × 7)Ge, Si,Ge(5 × 5), Ge(8 × 2), Ge(7 × 7)Si and Ge(1 × 1). The defects were studied in Ge/Si and Ge/GaAs heterosystems. The surface diffusion was found to have a marked effect on the film surface morphology and as a result of this on the type of misfit dislocations at the interface and on the density of threading dislocations. Electrophysical properties of the films are also discussed.     

High quality Ge epitaxial layers on Si by ultrahigh vacuum chemical vapor deposition

Flat, relaxed Ge epitaxial layers with low threading dislocation density (TDD) of 1.94 × 10⁶ cm^− 2 were grown on Si(001) by ultrahigh vacuum chemical vapor deposition. High temperature Ge growth at 500 °C on 45 nm low temperature (LT) Ge buffer layer grown at 300 °C ensured the growth of a flat surface with RMS roughness of 1 nm; however, the growth at 650 °C resulted in rough intermixed SiGe layer irrespective of the use of low temperature Ge buffer layer due to the roughening of LT Ge buffer layer during the temperature ramp and subsequent severe surface diffusion at high temperatures. Two-dimensional Ge layer grown at LT was very crucial in achieving low TDD Ge epitaxial film suitable for device applications.     

Diameter-dependent composition of vapor-liquid-solid grown Si(1-x)Ge(x) nanowires

Diameter-dependent compositions of Si(1-x)Ge(x) nanowires grown by a vapor-liquid-solid mechanism using SiH(4) and GeH(4) precursors are studied by transmission electron microscopy and X-ray energy dispersive spectroscopy. For the growth conditions studied, the Ge concentration in Si(1-x)Ge(x) nanowires shows a strong dependence on nanowire diameter, with the Ge concentration decreasing with decreasing nanowire diameter below approximately 50 nm. The size-dependent nature of Ge concentration in Si(1-x)Ge(x) NWs is strongly suggestive of Gibbs-Thomson effects and highlights another important phenomenon in nanowire growth.     

Epitaxial growth of metal single-crystal films

A review of the epitaxial growth of metals in high and ultra-high vacuum leading to single-crystal films is presented. The conditions for obtaining such films are described and tabulated for two groups of substrates: (i) metals, Si, Ge (strong interfacial bonding) and (ii) alkali halides and MgO cleavage faces (weak interfacial bonding). Information on the crystal defects and their relation with the growth parameters and annealing procedures is also given.     

Si-Sb-Te materials for phase change memory applications

Si-Sb-Te materials including Te-rich Si?Sb?Te? and Si(x)Sb?Te? with different Si contents have been systemically studied with the aim of finding the most suitable Si-Sb-Te composition for phase change random access memory (PCRAM) use. Si(x)Sb?Te? shows better thermal stability than Ge?Sb?Te? or Si?Sb?Te? in that Si(x)Sb?Te? does not have serious Te separation under high annealing temperature. As Si content increases, the data retention ability of Si(x)Sb?Te? improves. The 10 years retention temperature for Si?Sb?Te? film is ~393 K, which meets the long-term data storage requirements of automotive electronics. In addition, Si richer Si(x)Sb?Te? films also show improvement on thickness change upon annealing and adhesion on SiO? substrate compared to those of Ge?Sb?Te? or Si?Sb?Te? films. However, the electrical performance of PCRAM cells based on Si(x)Sb?Te? films with x > 3.5 becomes worse in terms of stable and long-term operations. Si(x)Sb?Te? materials with 3 < x < 3.5 are proved to be suitable for PCRAM use to ensure good overall performance.     

Germanium epitaxy on silicon

With the rapid development of on-chip optical interconnects and optical computing in the past decade, silicon-based integrated devices for monolithic and hybrid optoelectronic integration have attracted wide attention. Due to its narrow pseudo-direct gap behavior and compatibility with Si technology, epitaxial Ge-on-Si has become a significant material for optoelectronic device applications. In this paper, we describe recent research progress on heteroepitaxy of Ge flat films and self-assembled Ge quantum dots on Si. For film growth, methods of strain modification and lattice mismatch relief are summarized, while for dot growth, key process parameters and their effects on the dot density, dot morphology and dot position are reviewed. The results indicate that epitaxial Ge-on-Si materials will play a bigger role in silicon photonics.     

溅射气压对Ge/Si纳米点表面形貌的影响

利用磁控溅射技术在Si(100)衬底上直接外延生长一系列不同压强下的Ge纳米点样品,并利用AFM、Raman和XRF对Ge纳米点样品形貌和结构进行了研究。结果表明Ge薄膜表面粗糙度在某一临界压强下发生突变,高能粒子热化的临界值与这种转变密切相联;分析讨论了Ge岛在不同溅射气压下的生长过程,在一定范围随着压强的增大会显示典型生长阶段的特征。     

High strain embedded-SiGe via low temperature reduced pressure chemical vapor deposition

Performance improvement of strained p-type metal oxide semiconductor field effect transistors (p-MOSFETs) via embedded SiGe (e-SiGe) is well established. Strain scaling of p-MOSFETs since 90 nm complementary metal oxide semiconductor node has been accomplished by increasing Ge content in e-SiGe from nominally < 20% in 90 nm p-MOSFETs to > 35% Ge in 32 nm p-MOSFETs. Further strain enhancement for 22 nm and beyond p-MOSFETs is required due to disproportionate reduction in device area per generation caused by non-scaled gate length. Relaxation of SiGe with > 35% Ge during epitaxial growth and subsequent processing is a major concern. Specifically low temperature growth is required to achieve meta-stable pseudomorphic SiGe film with high Ge%. Currently, selective SiGe epitaxial film in reduced pressure chemical vapor deposition (RPCVD) epitaxy is grown with conventional Si gas precursors and co-flow etch using HCl at temperatures higher than 625 °C. At temperatures lower than 625 °C in RPCVD epitaxy, however, HCl has negligible etch capability making selectivity difficult to achieve during epitaxial growth. Hence, cyclic deposit and etch epitaxial growth in conjunction with a low temperature etching chemistry is desirable to achieve selectivity at temperatures lower than 625 °C. In this paper, we apply the above concept to achieve selective growth of high strain SiGe (> 35%) at 500 °C on test patterns corresponding to 65 nm node. SiGe is grown non-selectively first at 500 °C with high order of silane as Si source, and Germane as Ge source followed by an etching chemistry also at 500 °C to achieve selectivity. In addition, the growth rate of SiGe epitaxial film and the Ge concentration in the deposited epitaxial film were studied as a function of Si precursor flow; the effect of HCl introduction on Ge concentration and film growth rate was discussed.     

The growth and transformation of Pd2Si on (111), (110) and (100) Si

Thin Pd films on (111), (110), (100) and amorphous Si substrates form [001] fiber textured Pd₂Si in the temperature range 100°–700°C. The degree of texture is a function of substrate orientation, increasing in the order amorphous Si, (100) Si, (110) Si and (111) Si. Only on the (111) Si substrate is the Pd₂Si film epitaxially oriented. Temperature-dependent growth on this orientation can be characterized by [001] textured growth, epitaxial azimuth orientation at the Si interface and progressive layer by layer formation of the mosaic crystal to the thin film surface.During Pd deposition, rapid non-diffusion-controlled growth of epitaxial Pd₂Si on (111) Si occurs at substrate temperatures of 100° and 200°C. An unidentified palladium silicide of low crystallographic symmetry forms during Pd deposition onto a 50°C substrate. The diffusion-controlled growth of Pd₂Si on (111) Si follows a t^0.5 dependence. The velocity constant is

$\text{k = 7 × 10}{}^{\mathrm{?2}}\text{exp}\text{?}\text{29200±800}\text{RT}\text{cm}{}^2\text{/}\text{sec}$

Palladium deposited on 100°C (111) Ge substrates reacts during deposition to form epitaxially oriented Pd₂Ge. However, growth of this phase at higher temperatures results in a randomly oriented film. The transformation of Pd₂Ge to PdGe is kinetically controlled. After a 15 min anneal at 560°±10°C in N₂ only PdGe is detectable on (111) Ge.The high temperature stability of thin film Pd₂Si is controlled by time- temperature kinetics. For a given annealing cycle, the nucleation and growth rates of the PdSi phase are inversely related to the crystalline perfection of Pd₂Si. Decreasing transformation rates follow the order (100), (110), (111) Si. formation of thin film Pd₂Si occurs by the formation of PdSi and subsequent growth of Si within the PdSi phase. After a 30 min N₂ anneal, initial transformation occurs at 735°C on (100) Si, 760°C on (110) Si and 840°C on (111) Si. Extended high temperature annealing produces a two-phase structure of highly twinned and misoriented Si and small PdSi grains that penetrate as much as 3 μm into the Si.     

An investigation of epitaxial films by means of high energy electron diffraction: II. A study of film morphology

In the present work film morphology was studied by an electron diffraction method. The electron microscopy replica method seems to be insufficient to give unambiguous information concerning film morphology and the growth process, but a combination of diffraction data and electron microscope observations gives much more complete information. We applied these methods to investigations of Ge epitaxial films on GaAs and Si substrates at different stages of growth (at thicknesses of 20 Å upwards).     

Composition controlled synthesis and Raman analysis of Ge-rich Si(x)Ge(1-x) nanowires

Here, we report the synthesis of Si(x)Ge(1-x) nanowires with x values ranging from 0 to 0.5 using bulk nucleation and growth from larger Ga droplets. Room temperature Raman spectroscopy is shown to determine the composition of the as-synthesized Si(x)Ge(1-x) nanowires. Analysis of peak intensities observed for Ge (near 300 cm(-1)) and the Si-Ge alloy (near 400 cm(-1)) allowed accurate estimation of composition compared to that based on the absolute peak positions. The results showed that the fraction of Ge in the resulting Si(x)Ge(1-x) alloy nanowires is controlled by the vapor phase composition of Ge.     

Electrical isolation of dislocations in Ge layers on Si(001) substrates through CMOS-compatible suspended structures

Abstract

Suspended crystalline Ge semiconductor structures are created on a Si(001) substrate by a combination of epitaxial growth and simple patterning from the front surface using anisotropic underetching. Geometric definition of the surface Ge layer gives access to a range of crystalline planes that have different etch resistance. The structures are aligned to avoid etch-resistive planes in making the suspended regions and to take advantage of these planes to retain the underlying Si to support the structures. The technique is demonstrated by forming suspended microwires, spiderwebs and van der Pauw cross structures. We finally report on the low-temperature electrical isolation of the undoped Ge layers. This novel isolation method increases the Ge resistivity to 280 Ω cm at 10 K, over two orders of magnitude above that of a bulk Ge on Si(001) layer, by removing material containing the underlying misfit dislocation network that otherwise provides the main source of electrical conduction.