A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines halve the data line precharging power dissipation and the number of data lines. Clocks phase shifted by 0/spl deg/, 90/spl deg/, and 270/spl deg/ are generated through the proposed clock adjustment circuits. The latter circuits make input data sampled with an optimized setup/hold window. On-chip input termination with a linearity error of /spl plusmn/4.1% is developed to improve signal integrity at higher data rates. A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM is fabricated in a 0.10-/spl mu/m CMOS process with five metals. The cell size and the chip size are 0.845 /spl mu/m/sup 2/ and 151.1 mm/sup 2/, respectively.     

A high-speed, 240-frames/s, 4.1-Mpixel CMOS sensor

This paper describes a large-format 4-Mpixel (2352/spl times/1728) sensor with on-chip parallel 10-b analog-to-digital converters (ADCs). The chip size is 20/spl times/20 mm with a 7-/spl mu/m pixel pitch. At a 66-MHz master clock rate and 3.3-V operating voltage, it achieves a high frame rate of 240 frames/s delivering 9.75 Gb/s of data with power dissipation of less than 700 mW. The principal architectural features of the sensor are discussed along with the results of sensor characterization.     

Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect

A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, data rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive nonreturn-to-zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35-/spl mu/m CMOS technology. Accuracy of the models is verified. Bit-error rate is investigated for various inductor layouts and communication distance. The maximum data rate is 1.25 Gb/s/channel. Power dissipation is 43 mW in the transmitter and 2.6 mW in the receiver at 3.3 V. If chip thickness is reduced to 30 /spl mu/m in 90-nm device generation, power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm/sup 2/.     

A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver

A CMOS low-power mixed-signal clock and data recovery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR backplane transceiver, and consists of a phase detector, loop filter, phase control logic, and phase interpolator. A unique subsampled architecture makes it possible for a low-power mixed-signal clock recovery loop running at a rate of 6 Gb/s. The proposed architecture has data pattern independent loop bandwidth. Fabricated in a 0.13-/spl mu/m CMOS technology in an area of 280/spl times/100 /spl mu/m/sup 2/, the clock and data recovery loop exhibits a frequency tracking range up to 2000 ppm. The bit error rate is less than 10/sup -12/ with a pseudorandom bit sequence of length 2/sup 31/-1. The power dissipation is 24 mW for clock and data recovery circuits from a single 1.2-V supply.     

10-Gb/s limiting amplifier and laser/modulator driver in 0.18-/spl mu/m CMOS technology

A limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50 dB, a bandwidth of 9.4 GHz, and a sensitivity of 4.6 mV/sub pp/ for a bit-error rate of 10/sup -12/ while consuming 150 mW. A driver employs T-coil peaking and negative impedance conversion to achieve operation at 10 Gb/s while delivering a current of 100 mA to 25-/spl Omega/ lasers or a voltage swing of 2 V/sub pp/ to 50-/spl Omega/ modulators with a power dissipation of 675 mW. Fabricated in 0.18-/spl mu/m CMOS technology, both prototypes operate with a 1.8-V supply.     

A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications

A 6.5-GHz FSK modulator suitable for low power wireless sensor network is presented. The energy efficient modulator employs closed-loop direct VCO modulation to achieve high data rate, multistage variable loop bandwidth technique for fast startup time and /spl Sigma/-/spl Delta/ for reduced power consumption in the synthesizer with fine resolution in frequency channel selection. The modulator, implemented using 0.25-/spl mu/m CMOS, achieves 20-/spl mu/s startup time with an effective data rate of 2.5 Mb/s while consuming 22 mW.     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

Parallel-optical interconnects >100 gb/s

A parallel-optical interconnect with 12 channels operating at 8.5 Gb/s giving an aggregate data rate of 102 Gb/s is demonstrated, to the authors' knowledge, for the first time. The paper describes and demonstrates 13 /spl times/ 16-mm cross-section 12-channel parallel-optic transmitter and receiver modules with each channel operating at a data rate of 8.5-10 Gb/s. This was achieved using bottom-emitting 990-nm vertical-cavity surface-emitting lasers and bottom-illuminated InGaAs-InP photodetectors flip-chip bonded directly to 12-channel transmitter and receiver integrated circuits, respectively. In addition, 102-Gb/s link results are demonstrated over 100 m of 50-/spl mu/m-core standard multimode ribbon fiber. A bit-error ratio of <10/sup -13/ was measured on a single channel after transmission through 100 m of multimode fiber at a data rate of 8.5 Gb/s with all 12 channels operating simultaneously.     

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

This work presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5Gb/s for a single 10-Gbit eXtended Attachment Unit Interface (XAUI) in a standard 0.18-/spl mu/m CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than <4.5/spl times/10/sup -15/ while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.     

Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits

In this paper, we present integrated circuit solutions that enable high-speed data transmission over legacy systems such as short reach optics and electrical backplanes. These circuits compensate for the most critical signal impairments, intersymbol interference and crosstalk. The finite impulse response (FIR) filter is the cornerstone of our architecture, and in this study we present 5- and 10-Gsym/s FIR filters in 2-/spl mu/m GaAs HBTs and 0.18-/spl mu/m CMOS, respectively. The GaAs FIR filter is used in conjunction with spectrally efficient four-level pulse-amplitude modulation to demonstrate 10-Gb/s data throughput over 150 m of 500 MHz/spl middot/km multimode fiber. The same filter is also used to demonstrate equalization and crosstalk cancellation at 5 Gb/s on legacy backplane. The crosstalk canceller improves the bit error rate by five orders of magnitude. Furthermore, our CMOS FIR filter is tested and demonstrates backplane channel equalization at 10 Gb/s. Finally, building blocks for crosstalk cancellation at 10 Gb/s are implemented in a 0.18-/spl mu/m CMOS process. These circuits will enable 10-Gb/s data rates on legacy systems.     

A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication

This paper presents a monolithic optical detector, consisting of an integrated photodiode and a preamplifier in a standard 0.18-/spl mu/m CMOS technology. A data rate of 3 Gb/s at BER <10/sup -11/ was achieved for /spl lambda/=850 nm with 25-/spl mu/W peak-peak optical power. This data rate is more than four times than that of current state-of-the-art optical detectors in standard CMOS reported so far. High-speed operation is achieved without reducing circuit responsivity by using an inherently robust analog equalizer that compensates (in gain and phase) for the photodiode roll-off over more than three decades. The presented solution is applicable to various photodiode structures, wavelengths, and CMOS generations.     

A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus

This paper describes a low-power synchronous pulsed signaling scheme on a fully AC coupled multidrop bus for board-level chip-to-chip communications. The proposed differential pulsed signaling transceiver achieves a data rate of 1 Gb/s/pair over a 10-cm FR4 printed circuit board, which dissipates only 2.9 mW (2.9 pJ/bit) for the driver and channel termination and 2.7 mW for the receiver pre-amplifier at 500 MHz. The fully AC coupled multipoint bus topology with high signal integrity is proposed that minimizes the effect of inter-symbol interference (ISI) and achieves a 3 dB corner frequency of 3.2 GHz for an 8-drop PCB trace. The prototype transceiver chip is implemented in a 0.10-/spl mu/m 1.8-V CMOS DRAM technology and packaged in a WBGA. It occupies an active area of 330/spl times/85 /spl mu/m/sup 2/.     

Bipolar high-gain limiting amplifier IC for optical-fiber receivers operating up to 4 Gbit/s

A monolithic integrated high-gain limiting amplifier for future optical-fiber receivers is described. It is characterized by the following features: high insertion-voltage gain (maximum 54 dB); high input dynamic range (about 52 dB) at constant output-voltage swing (400 mV/SUB p-p/); high operating speed (up to at least 4 Gb/s); low power dissipation (350 mW at 50-/spl Omega/ load); standard supply voltage (5 V); 50-/spl Omega/ output buffer; one-chip solution; and small fabrication costs by use of a 2-/spl mu/m standard bipolar technology without needing polysilicon self-aligning processes. The good values of operating speed and power consumption, which the authors believe has until now not nearly been achieved by other comparable bipolar amplifier ICs, are a result of careful circuit design and optimization. The amplifier was extended to a high-sensitivity (amplitude and time) decision circuit operating at up to 4.0 Gb/s by adding a high-speed master-slave D-flip-flop IC fabricated with the same technology.     

A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling

This paper presents a simultaneous bi-directional (SBD) 4-level I/O interface for high-speed DRAMs. The data rate of 4 Gb/s/pin was demonstrated using a 500-MHz clock generator and a full CMOS rail-to-rail power swing. The power consumed by the I/O circuit was measured to be 28 mW/pin, when connected to a 10-pF load, at a 1.8-V supply voltage. The transmitter uses a 4-level push-pull linear output driver and a 4-level automatic impedance controller, achieving the reduction of driver currents and the voltage margin as large as 200 mV. The receiver employs a hierarchical sampling scheme, wherein a differential amplifier selects three out of six reference voltage levels. This scheme ensures minimized sampling power and a wide common-mode sampling range. The 6-level reference voltage for sampling is generated by the combination of the transmitter replica. The proposed I/O interface circuits are fabricated using a 0.10-/spl mu/m, 2-metal layers DRAM process, and the active area is 330 /spl times/ 66 /spl mu/m/sup 2/. It exhibits 200 mV /spl times/ 690 ps eye windows on the given channel with a 1.8-V supply voltage.     

An 8-Gb/s/pin simultaneously bidirectional transceiver in 0.35-/spl mu/m CMOS

This paper presents architecture, circuits, and test results for a single-ended, simultaneously bidirectional interface capable of a total throughput of 8 Gb/s per pin. The interface addresses noise reduction challenges by utilizing a pseudodifferential reference with noise immunity approaching that of a fully differential reference. The transmitter supports on-chip termination, predistortion, and low-skew near-end outgoing signal echo cancellation. The receiver's sense amplifier evaluates the average of two differential input signals without use of analog components and utilizes imbalanced charge injection to compensate for offset voltages. A test chip integrated in a 0.35-/spl mu/m digital CMOS technology uses the proposed techniques to implement an 8-bit wide single-ended voltage-mode simultaneous bidirectional interface and achieves a performance of 8 Gb/s per pin.     

A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling

This paper describes an adaptive bandwidth bus (ABB) architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode signaling. Attaining a maximum aggregate bandwidth of 16 Gb/s (i.e., 1 Gb/s per line) across lossy on-chip interconnects spanning 1.75 cm in length, the bus core fabricated in 0.35 /spl mu/m CMOS technology dissipates approximately 93 mW with a supply of 2.5 V and signal activity of 0.5, equivalent to 5.71 pJ/bit. Experimental results using a 16-bit reference bus design that can be externally programmed to operate in voltage, current or adaptive modes indicate a 50% reduction in power dissipation over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66% over voltage-mode (VM) sensing, respectively.     

Self-heating and trapping effects on the RF performance of GaN MESFETs

RF power performances of GaN MESFETs incorporating self-heating and trapping effects are reported. A physics-based large-signal model is used, which includes temperature dependences of transport and trapping parameters. Current collapse and dc-to-RF dispersion of output resistance and transconductance due to traps have been accounted for in the formulation. Calculated dc and pulsed I-V characteristics are in excellent agreement with the measured data. At 2 GHz, calculated maximum output power of a 0.3 /spl mu/m/spl times/100 /spl mu/m GaN MESFET is 22.8 dBm at the power gain of 6.1 dB and power-added efficiency of 28.5% are in excellent agreement with the corresponding measured values of 23 dBm, 5.8 dB, and 27.5%, respectively. Better thermal stability is observed for longer gate-length devices due to lower dissipation power density. At 2 GHz, gain compressions due to self-heating are 2.2, 1.9, and 0.75 dB for 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs, respectively. Significant increase in gain compression due to thermal effects is reported at elevated frequencies. At 2-GHz and 10-dBm output power, calculated third-order intermodulations (IM3s) of 0.30 /spl mu/m/spl times/100 /spl mu/m, 0.50 /spl mu/m/spl times/100 /spl mu/m, and 0.75 /spl mu/m/spl times/100 /spl mu/m GaN MESFETs are -61, -54, and - 45 dBc, respectively. For the same devices, the IM3 increases by 9, 6, and 3 dBc due to self-heating effects, respectively. Due to self-heating effects, the output referred third-order intercept point decreases by 4 dBm in a 0.30 /spl mu/m/spl times/100 /spl mu/m device.     

A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

This brief describes an adaptive bandwidth bus architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode (CM) signaling. An experimental adaptive bandwidth bus test chip fabricated in AMI 1.6-/spl mu/m Bulk CMOS indicates a reduction in power dissipation of approximately 62% over CM sensing and an increase in maximum data rate of 40% over voltage-mode signaling.     

A CMOS 10-gb/s power-efficient 4-PAM transmitter

A novel power-efficient architecture for a multilevel pulse amplitude modulation (PAM) transmitter is proposed. A data-look-ahead technique is used to pre-switch the current sources so that drive current is reduced when transmitting small voltage levels. This technique also eliminates the need for a pre-driver block, which also saves transmitter power. Based on this architecture, a 4-PAM transmitter is designed in 0.18-/spl mu/m standard digital CMOS technology. The transmitter achieves 3.5 GS/s (7 Gb/s) with a 1.7-V supply and 5 GS/s (10 Gb/s) with a 2-V supply and it occupies an area of 0.16 mm/sup 2/. The output driver and the entire transmitter consume only 11.25 and 66 mW at 7 Gb/s (20 and 121 mW at 10 Gb/s), respectively, which are the lowest reported powers at this speed.     

A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-/spl mu/m CMOS

A monolithic 10-Gb/s clock/data recovery and 1:2 demultiplexer are implemented in 0.18-/spl mu/m CMOS. The quadrature LC delay line oscillator has a tuning range of 125 MHz and a 60-MHz/V sensitivity to power supply pulling. The circuit meets SONET OC-192 jitter specifications with a measured jitter of 8 ps p-p when performing error-free recovery of PRBS 2/sup 31/-1 data. Clock and data recovery (CDR) is achieved at 10 Gb/s, demonstrating the feasibility of a half-rate early/late PD (with tri-state) based CDR on 0.18-/spl mu/m CMOS. The 1.9/spl times/1.5 mm/sup 2/ IC (not including output buffers) consumes 285 mW from a 1.8-V supply.