基于模拟的故障注入技术在高可靠处理器的应用

高可靠处理器在设计过程中,需要在不同阶段采用适当的故障注入技术,对其可靠性进行验证和评估.以LEON3高可靠处理器中的TMR(Triple Module Redundancy)flip-flop为例,使用基于模拟的故障注入技术对高可靠处理器进行故障注入.通过实验表明,采用此类故障注入技术,可以在设计前期对加固设计的可靠性进行快速验证,缩短开发周期,降低验证成本.     

A Differential Fault Analysis Attack Against the Light Weight PRINTcipher

We present two fault injection attacks against the IC-Printing block cipher (PRINTcipher).The basic idea of our attack is to notice the property that by using some couples of input difference and output difference,the attacker can determine the permutation control key.To recover the permutation control key,one needs to inject at least 4 faults.It is needed at least 15 faults to reveal the whole key.     

Fault Emulation for Dependability Evaluation of VLSI Systems

Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently pro posed as a means for speeding-up the fault injection process in VLSI systems models (fault emulation) and for reducing the cost of fixing any error due to their applicability in the first steps of the development cycle. However, only a reduced set of fault models, mainly stuck-at and bit-flip, have been considered in fault emulation approaches. This paper describes the procedures to inject a wide set of faults representative of deep-submicrometer technology, like stuck-at, bit-flip, pulse, indetermination, stuck-open, delay, short, open-line, and bridging, using the best suitable FPGA- based technique. This paper also sets some basic guidelines for comparing VLSI systems in terms of their availability and safety, which is mandatory in mission and safety critical application contexts. This represents a step forward in the dependability benchmarking of VLSI systems and towards the definition of a framework for their evaluation and comparison in terms of performance, power consumption, and dependability.     

空间单粒子故障容错设计的验证技术研究

由于空间环境的特殊性,可靠性成为航天器的重要指标,容错设计在航天关键电子元器件中必不可少。在航天器进入太空之前,为了模拟空间辐射效应,文中采用一种新颖方法对航天关键电子元器件进行单粒子故障注入,同时通过软件配合测试的方式,达到验证其容错结构的目的。采用了该技术的面向空间应用的高性能高可靠32位嵌入式RISC处理器取得了一次流片成功的结果。     

基于故障注入的基准电路故障响应分析

为了提高集成电路的成品率,试图采用更简便有效的方法测试芯片,并获得反映电路特性的故障响应率,在进行电路功能仿真(前仿真)或电路时序仿真(后仿真)的过程中,对电路注入单故障或多故障,然后在电路存在故障的情况下,模拟电路的行为,获得电路的故障响应率.实现了一个通用的数字电路"故障响应分析"程序,他模拟电路注入故障,收集模拟结果,通过分析获取电路的故障响应率.     

Modelling multiple faults in fault-tolerant processor architectures

The fault-tolerant microprocessor systems used in safety-critical applications need to be thoroughly validated during the design stages. As feature sizes reduce in future CMOS technologies, there is an increased probability of transient and intermittent faults. A new model for multiple bit-flips in the time domain is proposed, which can be used to target fault injection experiments. This extends the single or multiple bit-flip model that is currently used. Some results from fault injection experiments on two different processor architectures are also presented to illustrate the applicability of this model.     

A Java Framework to Specify Faultloads for Fault Injection Campaigns

In an operational environment, the identification and reproduction of faults may be hard to be done, specially in complex systems. Use of fault injection accelerates this process, improving the test of fault tolerance mechanisms. However, there are a significant amount of fault injectors available, using several different approaches. This diversity of tools, each one with different methods to describe faultloads for fault injection campaigns, imposes severe obstacles to the efficient use of such fault injectors. In this context, this paper presents jFaultload, which applies Java for the specification of faultloads and translates them to specific formats that are appropriate to each available fault injector. Fault injectors for communication systems were integrated in the environment and completes the test scenario. The service under test used to demonstrate the usability and expressiveness of our solution is a video streaming session using RTP Protocol.     

Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs

Dependability evaluation of embedded systems due to the integration of hardware and software parts is difficult to analyze. In this paper, we have proposed an experimental method to determine sensitivity to soft errors in an embedded system exploiting Altera SRAM-based FPGAs. The evaluation is performed using both the hardware and software parts of the embedded system in a single framework. To do this, the HDL hardware model of the target system as well as the C-written software codes of the target system, are required. Both permanent and transient faults are injected into the partially- or fully-synthesizable hardware of the target system and this can be performed during the design cycle of the system. The fault injection is composed of injecting SEUs into user design memory, and used configuration memory of the exploited FPGA. Using the experimental results, the sensitivity of Altera FPGAs to SEU faults are analyzed and derived. The analytical results reveal that the configuration memory is more significant than design memory to the SEUs due to the relative number of SRAM bits. Moreover, in this framework, in the case of injecting SEUs into user memory, the fault injection experiments are accelerated by the cooperation between a simulator and the FPGA.     

机电设备的测试性验证方法初探

针对目前机电设备缺少有效的测试性验证方法的问题,提出了机电设备测试性验证方法与步骤.通过采取基于故障影响相对比值的样本分配方案,可以使试验结果更加真实、可信.根据注入故障必须不能破坏任何设备的原则,对于串联型机电设备中不宜直接进行故障注入的目标,可以通过后驱动技术进行故障注入.最后,对某串联型机电设备进行了测试性验证,...     

基于Pspice的电路仿真故障注入的方法研究

为克服在测试性验证与评估过程中手动进行故障注入时费时的问题,对Pspice电路仿真中的故障注入的方法进行研究,提出了一种仿真电路故障注入自动化的方法,使用LL(k)语法分析技术开发了Pspice解析器,用Hook技术对Pspice进行监控,实现了电路的自动故障注入和仿真。经验证提出的解决方法,有助于提高在测试性验证与评估过程中故障注入的效率。     

Vom Lenkrad zum Joystick

Embedded computer systems are increasingly being entrusted with vital control tasks in safety critical applications. Due to their immense versatility they are replacing conventional relay- and mechanical control systems as well as pneumatic systems. The high complexity inherent to computer control systems, however, makes the assessment and proof of their reliability more difficult. While conventional failure mode analysis has proven effective for mechanical and relay control, embedded systems rather require probabilistic and metrological approaches. In this context our paper will concentrate on some aspects of fail-silent architectures as an alternative to TMR systems, system level reliability modelling and fault injection for the assessment of fault tolerance. The implications of this approach will be demonstrated for an automotive steer-by-wire system.     

现代模拟电路智能故障诊断方法研究与发展

对系统可靠性和经济性要求的提高使得模拟电路故障诊断的重要性日益凸显。首先在介绍了模拟电路故障原因及分类的基础上,详细分析了模拟电路故障诊断的特点。针对传统诊断方法的不足之处,介绍了基于人工智能和现代信息信号处理的现代故障诊断方法,包括专家系统诊断方法、神经网络诊断方法、模糊诊断方法和基于核的诊断方法,同时系统地分析了每种方法的基本原理、优缺点、研究进展和典型应用。最后探讨了目前模拟电路故障诊断研究存在的问题和未来的发展方向。     

雷达检测平台故障注入系统研究与设计

应用故障注入方法对系统进行检测是提高系统可靠性的有效途径。针对某型雷达检测系统的特点,通过对故障注入技术的研究,设计出相应的故障注入系统,给出一套完整的故障注入系统框架和软件总体的功能设计,基于集成度高、体积小的单片机系统,可对雷达检测装备系统的容错能力进行考查和验证。该系统可成功注入故障,具有操作简单、实时注入、性价比高、机动性好等突出优点。     

基于FPGA的功能域隔离电路设计

静态随机存储器(Static Random Access Memory, SRAM)型现场可编程门阵列（Field Programmable Gate Array, FPGA）广泛应用于航空航天系统中,但是高空中FPGA易受高能粒子影响造成配置出错,互联资源上发生的单点错误可能导致跨域故障,使芯片内多个模块同时失效。跨域故障可能导致电路中的工作模块与检错模块同时故障,使设备中存在不能被检测到的隐蔽故障。针对上述问题,提出在芯片上将不同功能的模块相互隔离,并通过约束实现模块间可信通信的故障隔离方法,将故障限定在单一模块内,防止多个模块同时失效,提高电路的容错能力。通过故障注入评估隔离设计前后的航空电子全双工交换式以太网（Avionics Full Duplex Switched Ethernet, AFDX）电路的各类故障发生率。实验结果证明隔离设计可以与电路原有的检错容错机制结合,将隐蔽故障的发生率降为原来的3%。     

Error Detection Enhancement in PowerPC Architecture-based Embedded Processors

This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer are combined with the Branch Trace Exception mechanism. The proposed technique is experimentally evaluated on a 32-bit PowerPC microcontroller using software implemented fault injection (SWIFI) and Power Supply Disturbances fault injection (PSD). A total of 6,000 faults were injected in microcontroller to measure the error detection coverage of the proposed control flow checking technique. The experimental results show that this technique detects about 95.2% of transient errors in software implemented fault injection method and 96.4% of transient errors in power supply disturbances fault injection method.     

Practical Analog Circuit Diagnosis Based on Fault Features with Minimum Ambiguities

As numerous faults exist in practical analog circuits, new challenges arise in the field of diagnosis with large-scale target faults as well as fault features. To address this issue, firstly, an ambiguity model is built to measure the distinguishability between two faults. Then, the optimal fault features are obtained by analyzing the response curves of the circuit under test (CUT) to minimize the ambiguities among the faults. Finally, comparisons are made among three classification methods, including the maximum likelihood classifier (MLC), artificial neural networks (ANNs) and support vector machine (SVM), to demonstrate their own diagnostic abilities for practical use. Two examples are illustrated, and taking advantage of an automated implementation framework, 92 faults in total are examined in the second example. The experimental results show that good diagnostic performances can be obtained with the proposed method. However, when a practical case is encountered, the ANNs method may fail due to its high time and space complexity, while the MLC and SVM methods are still applicable.     

Using multi-stage and stratified sampling for inferringfault-coverage probabilities

Development of fault-tolerant computing systems requires accurate reliability modeling. Analytic, simulation, and hybrid models are commonly used for obtaining reliability measures. These measures are functions of component failure rates and fault-coverage (probabilities). Coverage provides information about the fault and error detection, isolation, and system recovery capabilities. This parameter can be derived by physical or simulated fault injection. Statistical inference has been used to extract meaningful information from sample observation. The problem of conducting fault injection experiments and statistically inferring the coverage from the information gathered in those experiments is addressed in this paper. We perform statistical experiments in a multi-dimensional space of events. In this way all major factors which influence the coverage (fault locations, timing characteristics of the fault, and the workload) are accounted for. Multi-stage, stratified, and combined multi-stage and stratified sampling are used in this paper for deriving the coverage. Equations of the mean, variance, and confidence interval of the coverage are provided. The statistical error produced by the injected faults which do not induce errors in the tested system (also known as the nonresponse problem) is considered, A program which emulates a typical fault environment was developed and four hypothetical systems are analyzed