D/A和A/D转换器型谱的品种优化分析

本文从D/A与A/D转换器的基本概念和制造技术着手概述,特别对D/A和A/D转换器的应用之主要选择因素,进行了着重说明。随后,提出了D/A和A/D转换器优化品种的原则意见。     

Reference refreshing cyclic analog-to-digital and digital-to-analog converters

A method of cyclic analog-to-digital (A/D) and digital-to-analog (D/A) conversion using switched-capacitor techniques is described. By periodically modifying the reference voltage to compensate for the nonideal signal-transfer-loop gain, it is possible in principle to build A/D and D/A converters whose linearity is independent of component ratios and that occupy only a small die area. These converters require two moderate-gain MOS operational amplifiers, one comparator, and a few capacitors. A test chip for A/D conversion was built and evaluated. The test data show that the A/D performs as a monotonic 13-bit converter with maximum 1-LSB differential and 2-LSB integral nonlinearity.     

Analysis and modeling of an improved dual-array D/A network for SAR A/D converter

Based on the discussion of traditional dual-array charge scaling D/A conversion approach, an improved D/A network for successive approximation A/D converter (ADC) is proposed in this letter. With a unit capacitor instead of traditional non-integral scaling capacitor and by adding several additional logic control signals, this novel D/A network is easier to realize in process than traditional dual-array approach. Theoretical analysis and high-level Matlab modeling results prove that this improved D/A network is suitable for embedded SoC applications.     

Low-power C-R hybrid D/A conversion network for SAR A/D converter

An energy-efficient D/A conversion structure combined with a splited unit-capacitor array and an intermittent-sleeping resistor string is presented for low power SAR A/D converter. The energy dissipation and the matching requirement of the D/A conversion network are researched based on Matlab modeling. And its superiority and applicability are proven by the realization of an 8-bit 200kS/s 25.6 μW 65 nm CMOS SAR A/D converter with this proposed D/A structure.     

A/D转换器非线性特性简易测试方法

A／D转换器非线性测试是A／D转换器静态特性测试的一项重要内容。相对于以往成本较高的测试方法，文章提出了一种简易可行的测试方法：利用高精度D／A转换器和低精度A／D转换器的精度差，借助8051仿真系统进行测试。实验表明，该方法成本低廉，操作简单，适用于A／D转换器非线性特性的初期评测。     

A self-latching A/D converter using resonant tunneling diodes

A high-speed analog-to-digital (A/D) converter based on the resonant tunneling diode (RTD) is described. This A/D converter takes advantage of the folding characteristic of the RTD to reduce circuit complexity. The speed of the A/D converter is improved by the fast latching action of the RTD digitizer. Simulations show that the 4-B A/D converter can have a sampling rate of several gigahertz     

一种高速A/D转换器时域重构技术研究

A/D转换器在航空航天系统中的重要元器件,随着器件转换时钟频率不断提高而其工作环境不断恶化,如何准确测试其时间参数对于全面评价A/D转换器性能特别重要。目前对于高速A/D转换器时间参数测试,主流方法是通过示波器直接测试其输出,该方法对于示波器采样速度要求比较高。文章提出一种高速A/D转换器时域重构技术,可以通过计算机数字信号处理方法来实现高速A/D转换器时间参数测试,同时避免对示波器采样速度的依赖。同时,在研究高速A/D转换器时域重构技术方法及其应用的基础上,通过了相关试验验证。     

基于传输电流开关理论的电流型CMOS ADC电路设计

本文利用数字电路设计理论中的舆电流开关理论对Ａ／Ｄ转换器的转换过程进行了分析,提出了仅基于该理论的电流型ＣＭＯＳ Ａ／Ｄ转换器电路设计。与传统的Ａ／Ｄ转换器电路设计比较,它避免了复杂的模拟信号处理部分电路,显著地简化了电路结构。结果表明该电路设计具有正确的逻辑功能。     

可编程控制器串行A／D,D／A接口电路的研究与应用

从Ｖ／Ｆ（电压／频率）转换电路入手，结合可编控制器中高速计数器及频率输出指令的特点，分别研究并设计了一种可以用可编程控制器的开关量输入口和输出口分别实现Ａ／Ｄ或Ｄ／Ａ转换的接口电路，并研究了相应的程序设计方法。     

基于DRFM的SAR干扰技术研究

本文从DRFM的时钟分析出发,研究了DRFM的A/D、D/A时钟差异对输出信号的影响,并以此为基础研究了DRFM输出信号对SAR进行干扰所带来的影响,研究了A/D、D/A时钟的差异与干扰模式和干扰效果的关系,最后通过仿真对前文的分析进行了验证。     

基于单片机和555定时器的A/D转换器设计

为克服在A/D转换中输入电压范围窄的问题,介绍了一种采用单片机AT89C51和NE555定时器构成的A/D转换器.详细分析了其工作原理和A/D转换的特性.该A/D转换器对低频输入信号在较高电压范围内具有一定的实用价值.     

High accuracy pipeline D/A convertor configuration

A new pipeline D/A convertor configuration is presented. This structure can be used as a module in a pipeline A/D convertor. The advantage of this D/A structure is that the accuracy is not influenced by any stray capacitor such as bottom plates or drain/source junction capacitors. As a result video frequency operation can be obtained with this structure     

Static linearity error analysis of subranging A/D converters

An 8- to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits a reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with individual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate f _sand the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.     

新型自控原理实验装置的研制

本文介绍了一种基于计算机并口A/D、D/A转换实现的新型自控原理实验装置。该装置由计算机、A/D及D/A接口板、模拟实验箱等组成，软件在Windows环境下用VB编制，实现了对实验数据的采集、存储和计算处理，使实验结果更准确直观，显著提高了实验效果。     

一种12位400 MHz电流开关型D/A转换器的设计

基于TSMC 0.25μm工艺、采用电流开关结构,设计了一个3.3 V 12位400 M采样率的D/A转换器。在电路中,设计了一种新的电压限幅结构,从而使其具有较好的动态性能。该D/A转换器在1 MHz输入信号下,无杂散动态范围(SFDR)达到83.75 dB;在12.5 MHz输入信号下,可获得70 dB的SFDR;在不同温度和工艺corner下,仿真得到的电路性能也都能达到上述指标。     

Analogue to digital convertor architecture with a signal leveldetector

A new signal level detector for a flash-type A/D convertor is introduced. It operates like a comparator with the 1-of-n encoder of flash-type A/D convertors. Because the clock signal can be omitted in the application of the comparator, clock feedthrough noise is not a problem. A resolution of up to 8 bits in A/D conversion is feasible     

A behavioral model of A/D converters using a mixed-mode simulator

A mixed-mode behavioral model of analog-to-digital (A/D) converters is described. A generalized model structure is introduced. The basic function of an A/D converter is to convert an analog voltage into a digital code, for example, a binary number. Three conversion methods (successive approximation, flash, and dual integration) which are commonly used in A/D converters are modeled and can be selected simply by specifying a parameter of the model. For brevity, only the successive-approximation method is described. The modeling considerations of various parts in the A/D converter, including the input amplifier, D/A converter, comparator, and the synchronization problem, are described. The model has been implemented in the Saber mixed-mode simulator. Simulation results are given     

A CMOS ratio-independent and gain-insensitive algorithmicanalog-to-digital converter

This paper describes the design of a CMOS capacitor-ratio-independent and gain-insensitive algorithmic analog-to-digital (A/D) converter. Using the fully differential switched-capacitor technique, the A/D converter is insensitive to capacitor-ratio accuracy as well as finite gain and offset voltage of operational amplifiers. The switch-induced error voltage becomes the only major error source, which is further suppressed by the fully differential structure. The proposed A/D converter is designed and fabricated by 0.8 μm double-poly double-metal CMOS technology. The op-amp gain is only 60 dB and no special layout care is done for capacitor matching. Experimental results have shown that 14-b resolution at the sampling frequency of 10 kHz can be achieved in the fabricated A/D converter. Thus it can be used in the applications which require low-cost high-resolution A/D conversion     

基于对称三值逻辑的数模转换器研究

本文通过对称三值数字信号的开关理论分析和对称三值的数模转换的理论分析，设计了基于对称三值的数模转换电路。设计结果显示电路结构简单、合理，通过计算机模拟表明该数模转换电路的设计具有正确的逻辑功能。     

A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter

A 175 Ms/s A/D converter with a latency of one clock cycle is designed in a 0.7 μm digital CMOS technology. The resolution of the converter is 6 b while the power dissipation is only 160 mW. The A/D converter architecture is based on a continuous time analog preprocessing topology. A continuous time current interpolation circuit is implemented. The performance of the A/D converter is ruled by a tradeoff between speed, power, and accuracy