Two-dimensional charge-transfer arrays

Charge-transfer arrays with a truly two-dimensional organization in which an element of information contained in a general cell can be moved in more than one direction to an adjacent cell are proposed. After a review of the basic electrode arrangements for various charge-transfer techniques, some possible layouts for actual devices are described. It is shown that simple orthogonal arrays could readily lead to mass serial/parallel converters. Other arrays in which not all unit cells are identical could perform more complicated processing such as mixing operations or passing maneuvers between two fields of information. The possibilities of building logic arrays and of using two-dimensional arrays in electrooptical systems are also discussed. It is concluded that the introduction of additional degrees of freedom into charge-transfer devices increases their versatility and their potential uses, and that technologies are available for the fabrication of two-dimensional arrays.     

Logic operations in memory using a memristive Akers array

In-memory computation is one of the most promising features of memristive memory arrays. In this paper, we propose an array architecture that supports in-memory computation based on a logic array first proposed in 1972 by Sheldon Akers. The Akers logic array satisfies this objective since this array can realize any Boolean function, including bit sorting. We present a hardware version of a modified Akers logic array, where the values stored within the array serve as primary inputs. The proposed logic array uses memristors, which are nonvolatile memory devices with noteworthy properties. An Akers logic array with memristors combines memory and logic operations, where the same array stores data and performs computation. This combination opens opportunities for novel non-von Neumann computer architectures, while reducing power and enhancing memory bandwidth.     

Low power serial-parallel dynamic shift register

Serial-to-parallel shift registers have a wide range of applications. These registers are commonly found in communication systems and interfaces between electronic peripherals. Presented is a unique low power area efficient 128-bit serial-to-parallel shift register design that contains only four transistors per stage. The new register uses the capacitive bootstrapping technique to overcome the threshold voltage drop of MOSFETs. This logic family is named non-ratioed bootstrap logic (NRBL). Target applications are dense smart sensor arrays and image sensors.     

高速多通道CCD图像数据处理与传输系统设计

针对航天光学遥感成像系统输出通道多、输出速率高的特点,提出一种高速、多通道CCD图像数据并行处理与传输系统的设计方案.该方案以FPGA为数据处理和控制核心,采用基于FPGA区域并行处理的数据处理方法,运用FPGA内部块RAM构建高速多通道CCD图像的缓冲区,在存取控制上采取区域缓存和时分复用的策略完成对高速多通道CCD...     

中值滤波在红外成像引信中的应用及硬件实现

文中研究了在成像引信中应用中值滤波作为一种非线性的图像处理方法及其实现技术。通过运算、试验证明中值滤波在抑制成像引信扫描图像噪声、克服探测元失效方面起着良好的作用。本文提出了一种逻辑选通模块用于硬件实现元素个数较少的中值滤波,不同于常用实现中值滤波的排序网络,其具有更好的并行性且能够降低硬件资源消耗,通过FPGA 实现后取得了良好的效果。     

WCDMA上行链路中的一种有效的RAKE接收方案

在WCDMA系统上行链路中，提出把智能天线与RAKE接收机相结合，利用上行链路的帧结构特征，将各时隙的导频符号的扩频序列作为阵列处理部分的LMS自适应算法更新阵元权矢量的参考信号，来解决CDMA系统反向信道的容量受限问题。仿真实验结果表明该方法能显著提高系统的容量，且简单易行。     

计算机控制智能小车的软件设计

本设计是采用单片机作为从机(也称下位机),而PC机作为中央控制机的主从式系统。主机同时根据从从机接收的过程参数进行判断处理并给从机发送各种控制命令。利用单片机的串行口与PC机的串行口进行串行通信,PC机可对远程前端单片机进行控制,将单片机采集的数据传送到PC中去,由PC机对数据进行处理和显示,同时把反馈信号发到单片机,实现闭环控制和管理。本设计在VC++6.0的环境下,编写使用C++语言,SQL数据库的串口通信程序,控制由单片机控制的智能小车。     

Smart Phased Array SoCs: A Novel Application for Advanced SiGe HBT BiCMOS Technology

As BiCMOS IC technology continues to advance in scaling and performance, new applications are continually enabled. One such concept is a smart phased array system on a chip (SoC). The combination of high-performance SiGe heterojunction bipolar transistor (HBT) bipolar devices, well-characterized RF/analog passive components, and dense CMOS digital technology provides the capability to create large multielement, electronically tunable phased arrays with onboard processing intelligence, inside a single die. This SoC will have superior characteristics of lower cost, weight, and size as compared to the large multichip, multitechnology, and multipackage systems in deployment today. Furthermore, using reconfigurable logic and embedded memory, this SoC has the advantage of dynamic software and digital signal processing engine updates, without expensive redesigns of the chip. This publication will describe the necessary ingredients to create such an SoC as well as relevant applications of smart phased arrays that require an SiGe HBT BiCMOS technology. Potential markets for this technology include communications systems, weather tracking, radio astronomy, automotive radar, cellular basestation capacity improvement, satellite and aerial resource imaging, ground-level airplane collision avoidance, as well as military tracking and guidance systems.     

Implementation of an SDR platform using GPU and its application to a 2?��?2 MIMO WiMAX system

Conventional communication systems have been implemented using digital signal processors (DSPs) and/or field programmable gate arrays (FPGAs), especially for software defined radio (SDR) functionality. We propose a scheme that uses a graphics processing unit (GPU) in place of the conventional DSPs or FPGAs for the implementation of an SDR-based communication system. The GPU, a high-speed parallel processor with multiple arithmetic logic units, is adopted for the signal processing of the physical layer required for the parallel processing in an SDR system. The compute unified device architecture (CUDA) based on the C language provides a software development kit (SDK) for the modem application of the GPU. Therefore we utilize the CUDA SDK to implement the real-time modem function. This paper presents an implementation of a 2 × 2 multiple-input multiple-output (MIMO) WiMAX system employing a GPU as the real-time modem. By installing a radio frequency module on top of the GPU modem, we implement a real-time transmission system for video data. The performance of the proposed GPU-based system is demonstrated by comparing its operation time against that of the conventional DSP-based system.     

New field integration frequency interleaving color television pickup system for single-chip CCD camera

A new field integration frequency interleaving color-television pickup system has been developed for a single-chip CCD color video camera. This system uses anew color filter array, comprising a plurality of unit filter arrays, each unit consisting of 2 × 4 filter elements of yellow, cyan, and green color. High color fidelity and high-resolution color pictures without frame integration lag were obtained using only a ½-inch interline transfer CCD having 500 × 400 picture elements.     

Parallel architectures for digital optical cellular imageprocessing

A parallel digital optical cellular image processor (DOCIP) functionally comprises an array of identical I-bit processing elements or cells, a fixed interconnection network, and a control unit. Four interconnection network topologies are described, and include two variants of a mesh-connected array and two variants of a cellular hypercube network. The instruction sets of these single-instruction multiple-data (SIMD) machines are based on a mathematical morphological theory, binary image algebra (BIA), which provide an inherently parallel programming structure for their control. Physically, a DOCIP architecture uses a holographic optical element in a 3D free-space optical system to implement off-chip interconnections, and an optoelectronic spatial light modulator to implement a 2D array of nonlinear processing elements and (optionally) local on-chip interconnections. Two examples are given. The first, an experimental implementation of a single 54-gate cell of the DOCIP, uses an optically recorded hologram for within-cell optical interconnections, and a spatial light modulator for a 2D array of optically accessible gates. The second, a design for an efficient and more manufacturable architecture, uses a computer-generated diffractive optical element for cell-to-cell interconnections, and a 20 smart-pixel array of DOCIP cells, each cell having electronic logic and optical input/output     

一种改进的奇偶阵列结构运动估计器设计

提出了一种改进的奇偶阵列计算结构的运动估计器架构,该运动估计器利用了二维数据复用并能够实现全搜索法。设计了运动估计器的状态机控制逻辑,在其控制下,运动估计器的处理单元达到了100%的利用率。本运动估计器实现了高速、并行的运算,从而可以应用在高清视频的实时后处理等场合。     

基于FPGA的FIR升余弦滚降滤波器设计与实现

为了降低FIR滤波器对FPGA资源的消耗,同时能够直接验证其滤波性能。文中采用乘法器和加法器共享以及MEALY型状态机的实现方法,以及卷积、插零等算法,来实现FIR升余弦滚降滤波设计,同时给出了在Quartus II环境下的时序仿真结果。实践表明,此方法可以节省大量的FPGA资源,仅仅需要100多个LE逻辑单元,就可以有效解决FIR数字滤波器算法在FPGA设计中资源紧张的问题。     

基于FPGA的简易数字存储示波器设计

主要以简易数字存储示波器为例,介绍可编程逻辑器件在模数转换、数模转换及数据存储与处理中的设计方法。此系统由四部分组成,其中数据处理及存储单元用VHDL语言进行设计,利用MAX＋PLUSII软件进行电路仿真,并选用FP6A硬件实现;输入单元及输出单元采用AD976及AD669芯片实现;存储器RAM采用HM6264芯片实现。设计中采用了白顶向下的方法,将系统按逻辑功能划分模块,各模块使用VHDL语言进行设计,在ISE中完成软件的设计和仿真。     

一种智能用电管理装置的研发

一种智能用电管理装置，该装置分别与电力通信网络上的用电互动终端、用电设备和智能电表连接，该装置包括：网络通信单元，智能控制单元，用电采集单元，数据检测处理单元，利用网络通信单元，智能控制单元，用电采集单元，数据检测处理单元结合的构造，实现独立于用电设备使用，还可实时对用电信息进行监测采集和数据监测处理，从而提高了智能用电管理装置实时用电监测的性价比，实现用电安全监控管理功能。该装置已获得国家实用新型专利（专利名称：一种智能用电管理装置，专利号：201520825392.5）。     

The processing of hexagonally sampled two-dimensional signals

Two-dimensional signals are normally processed as rectangularly sampled arrays; i.e., they are periodically sampled in each of two orthogonal independent variables. Another form of periodic sampling, hexagonal sampling, offers substantial savings in machine storage and arithmetic computations for many signal processing operations. In this paper, methods for the processing of two-dimensional signals which have been sampled as two-dimensional hexagonal arrays are presented. Included are methods for signal representation, linear system implementation, frequency response calculation, DFT calculation, filter design, and filter implementation. These algorithms bear strong resemblances to the corresponding results for rectangular arrays; however, there are also many important differences. Some comparisons between the two methods for representing planar data will also be presented.     

Modular single-stage universal logic gate

First and second generation universal logic gate (ULG):IC's are described. The ULG comprises one-stage arrays of two identical cascade circuits. These ULG's are shown to realize all logic functions of four (and fewer) input variables in approximately the same propagation delay as a single ECL current switch emitter follower (CSEF) gate fabricated with the same processing technology. Substantial power and power-delay product advantages relative to CSEF arrays are demonstrated at comparable silicon area for realization of all four-input functions. The ULG was developed for implementing logic arrays with a minimum number of gating stages.     

一种逻辑加密卡安全体系的实现

介绍并讨论了一种逻辑加密卡安全体系实现的设计方法，针对加密卡成本较低、使用方便、安全性较好、用途广泛等要求，提出了包括密码认证体系和写保护体系在内的安全系统，给出了密码认证过程的几种模拟结果     

TDI-CCD相机成像电路设计

本文首先介绍了TDI-CCD的原理与结构,然后围绕IL-E2 TDI-CCD详细介绍了我们设计的TDI-CCD成像电路。时序控制器基于FPGA实现,产生CCD成像系统的控制时序和设置各种成像参数;功率驱动电路将时序发生单元产生的单一逻辑电平转换为TDI-CCD所需的各种电平,并提供给TDI-CCD容性负载瞬态电流的驱动能力;级数选择部分采用模拟开关实现;针对CCD输出的视频信号特点,设计了低噪声放大预处理电路;信号处理采用了集成相关双采样、可编程增益控制、数字化偏置控制、嵌位、A/D转换等功能于一体的CCD视频处理专用集成芯片TDA8783。本设计实现了CCD成像系统的控制和处理,得到了高质量的图像。     

Surface-acoustic-wave multiplexing techniques

Two approaches to frequency division multiplexing using SAW devices are described. The first one uses a 9-channel filter array, where the signal combining and splitting is performed using wide-band power splitters. Two of these filter arrays were used in a data link, with data rates up to 7.5 Mbit/s for a total data rate of 67.5 Mbit/s. The second approach uses offset multistrip couplers to channel a wide-band signal into various narrow-band outputs according to frequency. Consequently, this approach exhibits lower insertion loss and is especially suitable for a large number of channels. An 8-channel MSC multiplexer has been constructed with less than 10-dB insertion loss.