Compilation approach for coarse-grained reconfigurable architectures

Coarse-grained reconfigurable architectures can enhance the performance of critical loops and computation-intensive functions. Such architectures need efficient compilation techniques to map algorithms onto customized architectural configurations. A new compilation approach uses a generic reconfigurable architecture to tackle the memory bottleneck that typically limits the performance of many applications.     

A coarse-grained reconfigurable computing architecture with loop self-pipelining

Reconfigurable computing tries to achieve the balance between high efficiency of custom computing and flexibility of general-purpose computing. This paper presents the implementation techniques in LEAP, a coarse-grained reconfigurable array, and proposes a speculative execution mechanism for dynamic loop scheduling with the goal of one iteration per cycle and implementation techniques to support decoupling synchronization between the token generator and the collector. This paper also introduces the techniques of exploiting both data dependences of intra- and inter-iteration, with the help of two instructions for special data reuses in the loop-carried dependences. The experimental results show that the number of memory accesses reaches on average 3% of an RISC processor simulator with no memory optimization. In a practical image matching application, LEAP architecture achieves about 34 times of speedup in execution cycles, compared with general-purpose processors. Supported by the National Natural Science Foundation of China (Grant No. 60633050, 60621003) and the National High Technology Research and Development Program of China (Grant No. 2007AA01Z06)     

基于分布式粗粒度并行计算的遗传规划算法研究

针对经典遗传规划算法(CGP)存在容易早熟收敛、运行效率低的缺陷,提出一种将分布式计算与遗传规划算法结合的计算模型.该模型利用个体迁移策略实现对种群的优化,克服易早熟的缺陷.并且采用分布式计算能够有效地节省算法的运行时间.最后通过对语音数据预测误差的比较,验证了改进后算法的有效性.实验表明,基于分布式粗粒度并行计算的遗传规划算法(CGGP)计算性能优于经典遗传规划算法(CGP).     

Multi-level reconfigurable architectures in the switch model

In this paper, we propose a concept for multi-level reconfigurable architectures with more than two levels of reconfiguration, and study these architectures theoretically and experimentally. The proposed architectures are extensions of 2-level reconfigurable architectures where the reconfiguration operations on the lowest level correspond to the reconfiguration operations of standard 1-level reconfigurable architectures, and the reconfigurable units are simple switches. It is shown that finding an optimal number of reconfiguration levels and a corresponding reconfiguration scheme that minimizes the number of reconfiguration bits for a given algorithm can be done in polynomial time. But finding the optimal number of reconfiguration levels is NP-hard for heterogeneous multi-level architectures, where the number of reconfiguration levels varies for the different reconfigurable units. Experimental results for different test applications show that 3–4 reconfiguration levels are optimal with respect to the number of reconfiguration bits needed. The number of reconfiguration bits is reduced by 35–86% compared to 1-level reconfiguration and by 8–34% compared to 2-level reconfiguration. The heterogeneous architecture reduces the number of necessary reconfiguration bits by additional 1–5% and also needs less SRAM cells.     

Self-adaptive and reconfigurable distributed computing systems

In recent time, the applications of biologically-inspired computing models into various domains of computing fields have gained attention due to a set of advantages. The bio-inspired distributed computing paradigm offers benefits such as, self-detection and self-reconfiguration capabilities of the computing systems. The large scale distributed systems suffer from the arbitrary failure of nodes and dynamic formation of network partitions at any point of time. This paper proposes a novel membrane algorithm for self-detection and self-reconfiguration of large distributed systems on the event of arbitrary node failures resulting in network partitioning. The algorithm is distributed in nature and, it is designed based on the hybridization of biological membrane computing model and cell-signaling mechanisms of biological cells. This paper presents the problem definition, design and analysis of the algorithm. The performance of the algorithm is evaluated through simulation. A detailed comparative analysis of the algorithm with respect to the other contemporary algorithms is presented.     

End-user computing and information systems methodologies

End-user computing is a growing area within the information technology (IT) industry. The number and size of end-user-developed applications is steadily increasing, yet little attention is paid to the way in which such applications are developed, and their impact upon organizations. In this paper we examine the relationship between information systems methodologies and the end-user-computing environment. In particular, the potential benefits and disadvantages of the use of information systems methodologies for end-user-computing, and strategies by which such usage can be accomplished are discussed. This paper is partly the result of a research programme involving case studies in 34 UK organizations aimed at improving business systems.     

Continuity aspects of embedded reconfigurable computing

In embedded systems, dynamically reconfigurable computing can be partially modified at runtime without stopping the operation of the whole system. In this paper, we consider a reorganization mechanism for dynamically reconfigurable computing in embedded systems to guarantee that invariants of the design are respected. This reorganization is considered as a visual transformation of the logical configuration by the formulated rules. The invariant is recognized under the restructuring of the configuration using reconfiguration rules.     

Seamless hardware-software integration in reconfigurable computing systems

Ideally, reconfigurable-system programmers and designers should code algorithms and write hardware accelerators independently of the underlying platform. To realize this scenario, the authors propose a portable, hardware-agnostic programming paradigm, which delegates platform-specific tasks to a system-level virtualization layer. This layer supports a chosen programming model and hides platform details from users much as general-purpose computers do. We introduce multithreaded programming model for reconfigurable computing based on a unified virtual-memory image for both software and hardware application parts. We also address the challenge of achieving seamless hardware-software interfacing and portability with minimal performance penalties.     

Biomolecular computing and programming

Molecular computing is a discipline that aims at harnessing individual molecules at nanoscales for computational purposes. The best-studied molecules for this purpose to date have been DNA and bacteriorhodopsin. Biomolecular computing allows one to realistically entertain, for the first time in history, the possibility of exploiting the massive parallelism at nanoscales inherent in natural phenomena to solve computational problems. The implementation of evolutionary algorithms in biomolecules would bring full circle the biological analogy and present an attractive alternative to meet large demands for computational power. The paper presents a review of the most important advances in biomolecular computing in the last few years. Major achievements to date are outlined, both experimental and theoretical, and major potential advances and challenges for practitioners in the foreseeable future are identified. A list of sources and major events in the field has been compiled in the Appendix, although no exhaustive survey of the expanding literature is intended     

Evolution in dynamic architectures

This paper considers the evolution of dynamic architectures for modular computer systems. It concludes that a new system building block called a dynamic computer group (DC group) may be used for constructing both a multicomputer system with dynamic architecture and a new type of pipeline called a dynamic pipeline system.     

The case for reconfigurable hardware in wearable computing

Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.     

Design of the coarse-grained reconfigurable architecture DART with on-line error detection

This paper presents the implementation of the coarse-grained reconfigurable architecture (CGRA) DART with on-line error detection intended for increasing fault-tolerance. Most parts of the data paths and of the local memory of DART are protected using residue code modulo 3, whereas only the logic unit is protected using duplication with comparison. These low-cost hardware techniques would allow to tolerate temporary faults (including so called soft errors caused by radiation), provided that some technique based on re-execution of the last operation is used. Synthesis results obtained for a 90 nm CMOS technology have confirmed significant hardware and power consumption savings of the proposed approach over commonly used duplication with comparison. Introducing one extra pipeline stage in the self-checking version of the basic arithmetic blocks has allowed to significantly reduce the delay overhead compared to our previous design.     

Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor

This paper proposes a task-based hybrid parallel and hybrid pipeline(THPHP)scheme to implement multi-standard video algorithms,including MPEG-2,H.264,and audio video coding standard(AVS),on a heterogeneous coarse-grained reconfigurable processor,called the reconfigurable multimedia system(REMUS).The proposed schemes greatly improve decoding performance and satisfy the real-time requirements of various high-definition(HD)video decoding standards.In THPHP,we propose both a task-based hybrid parallel scheme,in which macro-block(MB)-level,block-level,and sub-block-level decoding tasks are parallelized to improve data processing throughput,and a hybrid pipeline scheme,in which slice-level,MB-level,block-level and sub-block-level computations are pipelined to improve efficiency.Computation-intensive tasks,such as motion compensation,intra prediction,inverse discrete cosine transform,reconstruction,and deblocking filter,are implemented on two reconfigurable processing units,which are the core computing engines of REMUS.Thanks to the proposed schemes,the implementations can achieve H.264 high profile(HP)1920×1080@30 fps streams,AVS Jizhun profile(JP)1920×1080@39 fps streams,and MPEG-2 main profile(MP)1920×1080@41 fps streams when working at 200 MHz frequency.Compared with XPP-III(a commercial reconfigurable processor),when implementing H.264 HD decoding,the performance and energy efficiency on REMUS are improved by1.81×and 14.3×,respectively.     

Design space exploration for partially reconfigurable architectures in real-time systems

In this paper, we introduce FoRTReSS (Flow for Reconfigurable archiTectures in Real-time SystemS), a methodology for the generation of partially reconfigurable architectures with real-time constraints, enabling Design Space Exploration (DSE) at the early stages of the development. FoRTReSS can be completely integrated into existing partial reconfiguration flows to generate physical constraints describing the architecture in terms of reconfigurable regions that are used to floorplan the design, with key metrics such as partially reconfigurable area, real-time or external fragmentation. The flow is based upon our SystemC simulator for real-time systems that helps develop and validate scheduling algorithms with respect to application timing constraints and partial reconfiguration physical behaviour. We tested our approach with a video stream encryption/decryption application together with Error Correcting Code and showed that partial reconfiguration may lead to an area improvement up to 38% on some resources without compromising application performance, in a very small amount of time: less than 30 s.     

Self-assembled architectures and the temporal aspects of computing

Despite the convenience of clean abstractions, technological trends are blurring the lines between design layers and creating new interactions between previously unrelated architecture layers. For example, virtual machines such as VMWare and Transmeta implement the application-software-visible architecture in virtual-machine software, allowing more flexibility in the hardware/software interface beneath the VM layer. Future technologies will likely further increase the interactions between design layers. Programmable self-assembly is an emerging fabrication technology that must be considered in the higher layers of computer system design. This technology offers an opportunity to perform computation during the fabrication process itself.     

Optofluidics: a novel generation of reconfigurable and adaptive compact architectures

The integration of microfluidics and microphotonics brings the ability to tune and reconfigure ultra-compact optical devices. This flexibility is essentially provided by three characteristics of fluids that are scalable at the micron-scale: fluid mobility, large ranges of index modulation, and abrupt interfaces that can be easily reshaped. Several examples of optofluidic devices are presented here to illustrate the achievement of flexible devices on (semi) planar and compact platforms. First, we report an integrated geometry for a compact and tunable interferometer that exploits a sharp and mobile air/water interface. We then describe a class of optically controlled devices that rely on the actuation of optically trapped micron-sized objects within a fluid environment. The last architecture results from the infiltration of photonic crystal devices with fluids. This produces tunable and reconfigurable photonic devices, like optical switches. Higher degrees of functionality could be achieved with sophisticated optofluidic platforms that associate complex microfluidic delivery and mixing schemes with microphotonic devices. Moreover, optofluidics offers new opportunities for realizing highly responsive and compact sensors.     

Traffic modeling in a reconfigurable broadband nomadic computing environment

Reconfiguring a network to counter variations in traffic is expected to greatly enhance optimal usage of network resources. But an important input to this method is the traffic fluctuations themselves. We have developed two models for this purpose to describe the time-dependent variations in traffic at a base station in a nomadic computing, wireless environment. The first model is rather simple and does not take into account details of human behavior. It takes into account the probabilities of choosing different applications. The model is also analyzed and experimented with to identify the important input parameters. The second model, a refined version of the first model, takes into account details of relevant human behavior (in the context of a wireless nomadic computing environment). Finally, we have compared the two models on the basis of their complexity and validity in different situations.