Direct e-beam writing of high aspect ratio nanostructures in PMMA: A tool for diffractive X-ray optics fabrication

We present a fast and reliable fabrication method of dense, periodic and high aspect ratio PMMA and metallic nanostructures. Biased lines are directly exposed by a 100 keV electron beam in thick layers of polymethyl-methacrylate (PMMA) resist to produce polymer mold which is later used to grow Au high aspect ratio structures by electroplating. Dense PMMA and Au nanostructures with aspect ratios >11 were manufactured in 520 nm and with aspect ratios >12 in ～1 μm thick layers of PMMA. This method was successfully applied to produce various X-ray optics devices, such as beam shaping condensers, Fresnel zone plates and diffraction gratings. The performance of a beam shaper was tested at 10 keV photon energy showing a good diffraction efficiency of 10%.     

MEMS器件制造工艺中的高深宽比硅干法刻蚀技术

硅的高深宽比刻蚀技术是MEMS领域中的一项关键工艺。在硅片上形成高深宽比沟槽并拥有垂直侧壁结构是现在先进MEMS器件的一个决定性要求。本文分别介绍了国际上近年来使用F基和Cl2等离子体获得高深宽比的刻蚀方法并进行了比较,总结了各自的优缺点及适用范围。     

Electron beam lithography at 10 keV using an epoxy based high resolution negative resist

The behaviour of a new epoxy based resist (mr-EBL 6000.1 XP) as a negative resist for e-beam lithography is presented. We demonstrate that it is possible to define sub-100 nm patterns when irradiating thin (120 nm) layers of resist with a 10 keV electron beam. The dependence of resolution and remaining thickness on electron dose, electron energy and photo acid generator (PAG) content is determined. After the electron beam lithography process, the resist is used as a mask for reactive ion etching. It presents a good etch resistance, that allows transfer of patterns to the substrate with resolution below 100 nm.     

Advanced etching of silicon based on deep reactive ion etching for silicon high aspect ratio microstructures and three-dimensional micro- and nanostructures

Different processes involving an inductively coupled plasma reactor are presented either for deep reactive ion etching or for isotropic etching of silicon. On one hand, high aspect ratio microstructures with aspect ratio up to 107 were obtained on sub-micron trenches. Application to photonic MEMS is presented. Isotropic etching is also used either alone or in combination with anisotropic etching to realize various 3D shapes.     

Study of metal assisted anisotropic chemical etching of silicon for high aspect ratio in crystalline silicon solar cells

Textured surface is commonly used to enhance the efficiency of silicon solar cells by reducing the overall reflectance and improving the light scattering. In this study, a comparison between isotropic and anisotropic etching methods was investigated. The deep funnel shaped structures with high aspect ratio are proposed for better light trapping with low reflectance in crystalline silicon solar cells. The anisotropic metal assisted chemical etching (MACE) was used to form the funnel shaped structures with various aspect ratios. The funnel shaped structures showed an average reflectance of 14.75% while it was 15.77% for the pillar shaped structures. The average reflectance was further reduced to 9.49% using deep funnel shaped structures with an aspect ratio of 1:1.18. The deep funnel shaped structures with high aspect ratios can be employed for high performance of crystalline silicon solar cells.     

Replication of high aspect ratio pillar array structures in biocompatible polymers for tissue engineering applications

We developed a simple two-step replication method to transfer arrays of high aspect ratio nanopillars into films of poly(l-d,l-lactic acid) (PLLA). Such structures are promising model surfaces for tissue engineering applications. From arrays of 1 μm high and 200 nm wide pillars produced with e-beam lithography and reactive ion etching negative replicas were first formed by polydimethylsiloxane (PDMS) casting. The final replicates were produced by solvent casting from 1% to 4% solutions of PLLA in chlorinated solvents on the PDMS templates. The silicon masters provide excellent stability and reusability, whereas the flexibility and low surface energy of the PDMS are necessary for the separation of the casts made with PLLA, a brittle material which is difficult to handle. AFM and SEM characterizations confirmed a high fidelity reproduction of the structures with aspect ratios of 1:5. In vitro tests using mouse neural stem cells seeded on nanopillars showed that the cells sense the nano-sized topography and respond accordingly by orienting themselves.     

A simple method for high yield fabrication of sharp silicon tips

A simple, high yield, method for the fabrication of sharp silicon tips is described. A triangular etch mask design is used to ensure that the tip forms with a single point. An anisotropic wet etch gives rise to a tip that continues to “self-sharpen” after the etch mask is released. The tip geometry comprises three converging {1 1 3} planes towards the apex with {3 1 3} planes forming at the base. The apex of each tip typically has a radius of curvature of <5 nm, which can be reduced to <2 nm by a subsequent oxide sharpening process. Tips of this kind have been successfully integrated into the fabrication of atomic force microscopy probes.     

Experimental analysis and optimization of a photo resist coating process for photolithography in wafer fabrication

This investigation is applied the Taguchi method and combination the analysis of variance (ANOVA) to the photo resist (PR) coating process for photolithography in wafer manufacturing. Plans of experiments via nine experimental runs are based on the orthogonal arrays. In this study, the thickness mean and the uniformity of thickness of the PR are adopted as the quality targets of the PR coating process. This partial factorial design of the Taguchi method provides an economical and systematic method for determining the applicable process parameters. Furthermore, the ANOVA prediction of the thickness mean and the uniformity of thickness for the PR has been applied in terms of the PR temperature, chamber humidity, spinning rate, and dispensation rate by means of the designs of experiments (DOE) method. The PR temperature and the chamber humidity are found to be the most significant factors in both the thickness mean and the uniformity of thickness for a PR coating process. Finally, the sensitivity study of optimum process parameters was also discussed.     

A new fabrication process of field emitter arrays with submicrongate apertures using local oxidation of silicon

The field emitter arrays with submicron gate apertures for low voltage operation have been successfully fabricated by modifying the conventional Spindt process. The key element of the new process is forming the gate insulator by local oxidation of silicon, resulting in the reduction of the gate hole size due to the lateral encroachment of oxide. The gate hole diameter of 0.55 μm has been obtained from the original mask pattern size of 1.55 μm. An anode current of 0.1 μA per emitter is measured at the gate voltage of about 53 V, while the gate current is less than 0.3% of the anode current. To obtain the same current level from a Spindt-type emitter with the same gate hole diameter as the mask pattern size, a gate bias of about 82 V is needed     

A novel fabrication process of a silicon field emitter array withthermal oxide as a gate insulator

We have successfully developed a fabrication process of a silicon field emitter array with a gate insulator formed by Si₃N₄ sidewall formation and subsequent thermal oxidation. This process overcomes some problems in the conventional fabrication, such as high etch rate, low breakdown field, and gate hole expansion arising from evaporation of gate oxide. Therefore, we could improve process stability and emission performance, and also reduce gate leakage current. The optimum process conditions were determined by process simulations using SUPREM-4. The turn-on voltage of the fabricated field emitters was approximately 38 V. An anode current of 0.1 μA (1 μA) per tip was measured for a 625-tip array at the gate bias of 80 V (100 V), and the gate current was less than 0.3% of the anode current at those emission levels     

一种应用于WIA-PA收发机的高精度抗温度工艺偏差的CMOS 信号功率指示器

本文针对工业无线传感网WIA-PA标准设计出一款应用于WIA-PA收发机中的高精度抗温度工艺偏差的CMOS 接收信号功率指示器。本文提出信号功率指示器的采用TSMC 0.18 um 1P6MRF CMOS工艺流片,有效面积为0.24mm2。经测试,本文提出的信号功率指示器在输入信号从-70dBm到0dBm(50欧电阻匹配),线性误差在±0.5 dB以内,动态范围为70dB,检测灵敏度为12.1mV/dB,相应的输出电压从0.81V变化到1.657V。在1.8V电源供电情况下,整体功耗不超过2mA。进一步,本文提出的信号功率指示器中集成的修调和补偿电路,使得最大线性误差在-40到85度内不超过±1.5 dB,工艺角引起的线性误差不超过±0.25 dB。该功率检测器体现出良好的抗温度和工艺偏差的性能。     

高深宽比金属光栅制备及中红外波段传感特性

利用纳米压印结合溅射和反应离子刻蚀工艺制备了具有高深宽比的金光栅,使用傅里叶变换红外光谱仪测得了反射谱线.测量结果显示,只在p偏振光垂直于光栅矢量方向入射条件下才存在共振反射峰,证明了“伪表面等离子体激元波”的存在.基于严格耦合波分析理论计算了金属光栅的反射率,研究了其作为中红外波段波长调制型表面等离子体共振传感器的可行性.数值计算表明负级次衍射光波对应的共振反射峰的移动能获得较高的波长灵敏度.对于深宽比为10的金光栅结构,+1级次和-3级次衍射光波对应的波长灵敏度分别为1600 nm/RIU和5000 nm/RIU,品质因子分别为20 RIU-1和60RIU-1.     

高厚径比板湿制程主要失效模式及预防控制

高层次、高厚径比板具有较高的附加值,现已成为我公司主要制作产品之一。文章主要是简述此类型板在我公司湿制程过程中出现的一些异于其它普通板的失效模式及其预防控制方式。     

Development of a fabrication process for parallel multijunction thin film silicon solar cells on wafer substrates

The parallel multijunction (PMJ) cell design theoretically enables high efficiency thin film polysilicon solar cells at lower cost. Since its initial proposal in 1994 the PMJ cell has been the subject of a number of theoretical studies, however, no detailed experimental investigation has yet been reported. Any systematic study of the PMJ solar cell will require suitably designed and fabricated devices to serve as experimental test‐beds. This paper reports the successful development of a fabrication sequence for PMJ cells in CVD‐epilayers on inert single‐crystal silicon substrates, producing cells with efficiencies up to 13%. The processing sequence is based on photolithography, anisotropic wet etching, high temperature furnace steps and evaporated metallisation. Full details of the processing sequence are provided, with explanations of particular process choices, including the method of parallel electrical connection of like‐polarity layers, the use of a thick photoresist (Shipley SJR5740), avoiding pitfalls, and procedures to minimise cell shunt behaviour. The establishment of this baseline fabrication sequence for PMJ cells opens up a wealth of opportunities for systematic studies of cell performance limiting mechanisms, such as junction recombination, and the implications of various cell design and processing options, particularly those likely to be of more commercial relevance, such as laser scribing, laser doping, rapid thermal processing and electroless metal plating. Copyright © 2000 John Wiley & Sons, Ltd.     

A micromachined, shadow-mask technology for the OMVPE fabrication of integrated optical structures

A micromachined, silicon shadow-mask technology is described which extends the capabilities of shadow-masked OMVPE for the fabrication of nonplanar micro-optical elements. The deep reactive ion etched (DRIE) shadow mask is inexpensive, reusable and produces smooth, nonplanar structures with precise control of position, shape and size. Direct fusion bonding of the mask to the substrate was found to be a reliable and reproducible method for attaching the mask to the substrate during growth. The DRIE shadow mask technology allows the deposition of microlenses with focal lengths out to 3 mm without the central flattening that was previously observed in shadow masked lenses grown under the epitaxial mask. We also describe novel applications of this technology in the fabrication of micromirrors and concentrically-variable Bragg reflectors, which should improve mode discrimination in large aperture VCSELs.     

A high port-count wavelength-selective switch using a large scan-angle, high fill-factor, two-axis MEMS scanner array

We present a high-port-count (scalable to 1 /spl times/ 32) wavelength-selective switch (WSS) using a large scan-angle, high fill-factor, two-axis analog micromirror array in conjunction with a densely packed two-dimensional array of fiber collimators. A partially populated (1 /spl times/ 9) WSS exhibits a fiber-to-fiber insertion loss of 5.57 /spl plusmn/ 1.4 dB and an extinction ratio of 51 /spl plusmn/ 11 dB. The channel spacing is 100 GHz.     

Transverse probe optical lifetime measurement as a tool for in-line characterization of the fabrication process of a silicon solar cell

In this paper an all-optical measurement procedure for the characterization of minority carrier recombination lifetime and surface recombination velocity is presented as a reliable tool to monitor the fabrication process of a standard crystalline silicon solar cell. In the methodology presented here, there are no stringent requirements concerning the state of wafer surface. The IMEC (Interuniversity Microelectronics Centre, Leuven, Belgium) fabrication process is taken as an example of the capability of this method to monitor the whole process from the silicon wafer to the finished cell. It is shown that the cell process does not degrade the bulk recombination lifetime and that the effect of the external surfaces is effectively screened.     

A novel insulated gate technology for ingaas high electron mobility transistors using silicon interlayer based passivation technique

A novel insulated gate technology for InGaAs high electron mobility transistors (HEMT) is described. It utilizes a silicon interface control layer (Si ICL)-based passivation structure. By applying an HF surface treatment, the technology becomes applicable to the air-exposed surfaces of InGaAs and InAlAs. The basic metal-insulator-semiconductor structures were fabricated and characterized in detail by x-ray photoelectron spectroscopy analysis and capacitance-voltage measurements. The interface has been shown to be essentially free from interface states. InGaAs insulated gate HEMTs (IGHEMT) were then success-fully fabricated. The fabricated recessed gate IGHEMTs have good gate control of the drain current with good pinch-off characteristics. A highest effective mobility of 2010 cm²/Vs was obtained. The devices show extremely low gate leakage currents below lnA/mm.     

Study of the high throughput flexographic process for silicon solar cell metallisation

A commercially available silver paste was modified to match the flexographic process requirements. Rotational and oscillatory rheological tests were carried out to assess the printability and spreading behaviour of the resulting inks. Then, a multifactorial approach was used on a laboratory‐scale printing press to adapt the flexographic process for the front side metallisation of Cz‐Si solar cells, especially for the seed layer deposit of two layer contacts. To quickly identify the significant process parameters, a fractional design of experiment based on a screening approach at two levels was performed. Afterwards, two full factorial designs of experiments were implemented. While the first one allows a better understanding of the effect of the main factors and interactions, the second allows a fine tuning and a confirmation of the first results. Additionally, this methodology allows corroborating the influence of the ink rheological properties on the printing results. Following the process study and optimisation, a seed layer with an average width of 25 µm was printed at a high 0.3 m/s throughput. Additional results suggest that the line width and the throughput can be further improved, which underlines the potential of flexography for photovoltaic applications. Finally, the light‐induced process was used to thicken the seed layer after a standard firing‐through step, leading to an encouraging 17.9% efficiency on Cz‐Si solar cells. Copyright © 2015 John Wiley & Sons, Ltd.     

Design of a 10 bit high resolution,high speed time-to-digital converter using a two-step pulse-train time amplifier

Ahigh resolution and fast conversion rate time-to-digital converter (TDC) design based on time amplifier (TA) is proposed. The pulse-train TA employs a two-step scheme. The input time interval is first amplified by a N-times TA and the effective time is extracted in pulse-train using a time-register. Then the resulted interval is further amplified by the other pulse-train amplifier to obtain the final result. The two-step TA can thus achieve large gain that is critical for high resolution TDC. Simulation results in 1.2 V, 65 nm technology showed that for a 10 bit TDC, a resolution of 0.8 ps and a conversion rate of 150 MS/s are achieved while consuming 2.1 mW power consumption.