Optical and electrical characteristics of 17 keV X-rays exposed TiO2 films and Ag/TiO2/p-Si MOS device

This work presents the effect of varied doses of X-rays radiation on the Ag/TiO₂/p-Si MOS device. The device functionality was observed to depend strongly on the formation of an interfacial layer composed of SiO_x and TiO_y, which was confirmed by the spectroscopic ellipsometry. The XRD patterns showed that the as prepared TiO₂ films had an anatase phase and its exposure to varied doses of 17 keV X-rays resulted in the formation of minute rutile phase. In the X-rays exposed films, reduced Ti³⁺ state was not observed; however a fraction of Ti–O bonds disassociated and little oxygen vacancies were created. It was observed that the device performance was mainly influenced by the nature and composition of the interfacial layer formed at the TiO₂/Si interface. The spectroscopic ellipsometry was used to determine the refractive indices of the interfacial layer, which was 2.80 at λ=633 nm lying in between that of Si (3.87) and TiO₂ (2.11). The dc and frequency dependent electrical measurements showed that the interface defects (traps) were for both types of charge carriers. The presence of SiO_x was responsible for the creation of positive charge traps. The interface trap density and relaxation time (τ) were determined and analyzed by dc and frequency dependent (100 Hz–1 MHz) ac-electrical measurements. The appearance of peak in G/ω vs log (f) confirmed the presence of interface traps. The interface traps initially increased up to exposure of 10 kGy and then decreased at high dose due to compensation by the positive charge traps in SiO_x part of the interface layer. It was observed that large number of interface defects was active at low frequencies and reduced to a limiting value at high frequency. The values of relaxation time, τ ranged from 4.3±0.02×10⁻⁴ s at 0 V and 7.6±0.2×10⁻⁵ s at −1.0 V.     

Impact of local structural and electrical properties of grain boundaries in polycrystalline HfO2 on reliability of SiOx interfacial layer

Using nanometer-resolution characterization techniques, we present a study of the local structural and electrical properties of grain boundaries (GBs) in polycrystalline high-κ (HK) dielectric and their role on the reliability of underlying interfacial layer (IL). A detailed understanding of this analysis requires characterization of HK/IL dielectrics with nanometer scale resolution. In this work, we present the impact of surface roughness, thickness and GBs containing high density of defects, in polycrystalline HfO₂ dielectric on the performance of underlying SiO_x (x ⩽ 2) IL using atomic force microscopy and simulation (device and statistical) results. Our results show SiO_x IL beneath the GBs and thinner HfO₂ dielectric experiences enhanced electric field and is likely to trigger the breakdown of the SiO_x IL.     

Epitaxial growth of nonpolar GaN films on r-plane sapphire substrates by pulsed laser deposition

Single-crystalline nonpolar GaN epitaxial films have been successfully grown on r-plane sapphire (Al₂O₃) substrates by pulsed laser deposition (PLD) with an in-plane epitaxial relationship of GaN[1-100]//Al₂O₃[11-20]. The properties of the ~500 nm-thick nonpolar GaN epitaxial films grown at temperatures ranging from 450 to 880 °C are studied in detail. It is revealed that the surface morphology, the crystalline quality, and the interfacial property of as-grown ~500 nm-thick nonpolar GaN epitaxial films are firstly improved and then decreased with the growth temperature changing from 450 to 880 °C. It shows an optimized result at the growth temperature of 850 °C, and the ~500 nm-thick nonpolar GaN epitaxial films grown at 850 °C show very smooth surface with a root-mean-square surface roughness of 5.5 nm and the best crystalline quality with the full-width at half-maximum values of X-ray rocking curves for GaN(11-20) and GaN(10-11) of 0.8° and 0.9°, respectively. Additionally, there is a 1.7 nm-thick interfacial layer existing between GaN epitaxial films and r-plane sapphire substrates. This work offers an effective approach for achieving single-crystalline nonpolar GaN epitaxial films for the fabrication of nonpolar GaN-based devices.     

Effect of high-temperature annealing on lanthanum aluminate thin films grown by ALD on Si(1 0 0)

Amorphous lanthanum aluminate thin films were deposited by atomic layer deposition on Si(1 0 0) using La(ⁱPrCp)₃, Al(CH₃)₃ and O₃ species. The effects of post-deposition rapid thermal annealing on the physical and electrical properties of the films were investigated. High-temperature annealing at 900 °C in N₂ atmosphere leads to the formation of amorphous La-aluminosilicate due to Si diffusion from the substrate. The annealed oxide exhibits a uniform composition through the film thickness, a large band gap of 7.0 ± 0.1 eV, and relatively high dielectric constant (κ) of 18 ± 1.     

0.6nm-EOT high-k gate stacks with HfSiOx interfacial layer grown by solid-phase reaction between HfO2 and Si substrate

We have developed a process for forming an ultra-thin HfSiO_x interfacial layer (HfSiO_x-IL) for high-k gate stacks. The HfSiO_x-IL was grown by the solid-phase reaction between HfO₂ and Si-substrate performed by repeating the sequence of ALD HfO₂ deposition and RTA. The HfSiO_x-IL grown by this method enables the formation of very uniform films consisting of a few mono-layers, and the dielectric constant of the HfSiO_x-IL is about 7. The FUSI-NiSi/HfO₂ gate stacks with HfSiO_x-IL have achieved 0.6 nm EOT, a very low gate leakage currents between 1 A/cm² and 5 × 10⁻² A/cm², an excellent subthreshold swing of 66mV/dec, and a high peak mobility of 160 cm²/Vs compared to the reference samples without HfSiO_x-IL. These results indicate that the HfSiO_x-IL has a good quality compared to the SiO₂ interfacial layer grown by oxygen diffusion through HfO₂ films.     

Reliability/Uniformity improvement induced by an ultrathin TiO2 insertion in Ti/HfO2/Pt resistive switching memories

Reliability/Uniformity of resistance switching in Ti/HfO₂/Pt memory structure was improved by inserting an interfacial layer of 5 nm-thick TiO₂ between Ti and 45 nm-thick HfO₂. As a native oxide of Ti, TiO₂, effectively limits the disorder migration of oxygen from HfO₂ to Ti layer, and provides the more chemically-stable and morphologically-uniform interfaces with both the Ti electrode and the HfO₂ layer. Meanwhile, more stable resistive switching was observed in Ti/TiO₂/HfO₂/Pt than that in Ti/HfO₂/Pt memory, and the random variation during endurance test observed in Ti/HfO₂/Pt was also greatly limited in Ti/TiO₂/HfO₂/Pt memory. From these results, a thin TiO₂ insertion between the Ti electrode with the HfO₂ active layer, could greatly improve the reliability/uniformity of the Ti/HfO₂/Pt memory devices.     

Impact of the gate stack on the electrical performances of 3D multi-channel MOSFET (MCFET) on SOI

In this study, we integrate and compare the electrical performances of metal/high-K embedded gates in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO₂, TiN/SiO₂ or N⁺ poly-Si/SiO₂ are compared to a planar reference. In particular, we investigate electron and hole mobility behaviours (300 K down to 20 K) in embedded and planar structures, the gate leakage current and the negative bias temperature instability (NBTI). Despite a lower mobility, TiN/HfO₂ gate stack demonstrates the best I_ON/I_OFF compromise and exhibits NBTI life time higher than 10 years up to 1.3 V.     

Mechanism of mobility enhancement in Ge p-channel metal-oxide-semiconductor field-effect transistor due to introduction of Al atoms into SiO2/GeO2 gate stack

In this paper, we present comprehensive results on Al-postmetallization annealing (Al-PMA) effect for the SiO₂/GeO₂ gate stack on a Ge substrate, which were fabricated by a physical vapor deposition method. The effective oxide thickness of metal-oxide-semiconductor (MOS) capacitor (CAP) was ~7 nm, and the Al-PMA was performed at a temperature in the range of 300–400 °C. The flat band voltage (V_FB), the hysteresis (HT), the interfacial states density (D_it), and the border traps density (D_bt) for MOSCAPs were characterized by a capacitance–voltage method and a constant-temperature deep-level transient spectroscopy method. The MOSCAP without Al-PMA had an electrical dipole of ~−0.8 eV at a SiO₂/GeO₂ interface, which was disappeared after Al-PMA at 300 °C. The HT, D_it, and D_bt were decreased after Al-PMA at 300 °C and were maintained in the temperature range of 300–400 °C. On the other hand, the V_FB was monotonically shifted in the positive direction with an increase in PMA temperature, suggesting the generation of negatively charged atoms. Structural analyses for MOSCAPs without and with Al-PMA were performed by a time-of-flight secondary ion mass spectroscopy method and an X-ray photoelectron spectroscopy method. It was confirmed that Al atoms diffused from an Al electrode to a SiO₂ film and reacted with GeO₂. The dipole disappearance after Al-PMA at 300 °C is likely to be associated with the structural change at the SiO₂/GeO₂ interface. We also present the device performances of Al-gated p-channel MOS field-effect transistors (FET) with PMA treatments, which were fabricated using PtGe/Ge contacts as source/drain. The peak field-effect mobility (μ_h) of the p-MOSFET was reached a value of 468 cm²/Vs after Al-PMA at 325 °C. The μ_h enhancement was explained by a decrease in the total charge densities at/near the GeO₂/Ge interface.     

Ultra-low-energy ion-beam-synthesis of Ge nanocrystals in thin ALD Al2O3 layers for memory applications

Structural and electrical properties of ALD-grown 5 and 7 nm-thick Al₂O₃ layers before and after implantation of Ge ions (1 keV, 0.5–1 × 10¹⁶ cm^?2) and thermal annealing at temperatures in the 700–1050 °C range are reported. Transmission Electron Microscopy reveals the development of a 1 nm-thick SiO₂-rich layer at the Al₂O₃/Si substrate interface as well as the formation of Ge nanocrystals with a mean diameter of ～5 nm inside the implanted Al₂O₃ layers after annealing at 800 °C for 20 min. Electrical measurements performed on metal–insulator–semiconductor capacitors using Ge-implanted and annealed Al₂O₃ layers reveal charge storage at low-electric fields mainly due to location of the Ge nanocrystals at a tunnelling distance from the substrate and their spatial dispersion inside the Al₂O₃ layers.     

Temperature dependence of electrical properties for MOS capacitor with HfO2/SiO2 gate dielectric stack

We investigated the temperature dependence of C–V and I–V characteristics in p-type Metal Oxide Semiconductor (MOS) capacitors with HfO₂/SiO₂ dielectric stacks. Dramatic degradation in the C–V characteristics at/over the measurement temperature of 125 °C was observed, which was caused by the increased effective oxide thickness, oxide trapped charge density, and interfacial density of state (D_it) with rising temperature during bias temperature stress. In the accumulation region, the leakage current density displayed strong temperature dependence in the ?3 V<Vg<0 V region, as expected for the direct tunneling compared to the trap-assisted component (DT+TAT) effect. The conduction mechanism was transformed into Fowler–Nordheim (FN) tunneling (weak T and Vg dependence) from DT+TAT (strong T and Vg dependence) at Vg <?3 V, which was confirmed by FN tunneling fitting. According to the conventional Shockley–Read–Hall model, the different levels in D_it were found at various measurement temperatures to interpret the strong temperature dependence and weak Vg dependence inversion current property.     

Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications

Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiO_xN_y metal oxide NPs embedded in the HfO_xN_y high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O₂/N₂ ambient. Well-isolated TiO_xN_y NPs with a diameter of 5–20 nm, a surface density of ～3 × 10¹¹ cm^?2, and a charge trap density of around 2.33 × 10¹² cm^?2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping.     

Effect of the film thickness on the crystal structure and ferroelectric properties of (Hf0.5Zr0.5)O2 thin films deposited on various substrates

In this work, the effect of the film thickness on the crystal structure and ferroelectric properties of (Hf_0.5Zr_0.5)O₂ thin films was investigated. The thin films were deposited on (111) Pt-coated SiO₂, Si, and CaF₂ substrates with thermal expansion coefficients of 0.47, 4.5, and 22×10⁻⁶/°C, respectively. From the X-ray diffraction measurements, it was found that the (Hf_0.5Zr_0.5)O₂ thin films deposited on the SiO₂ and CaF₂ substrates experienced in-plane tensile and compressive strains, respectively, in comparison with the films deposited on the Si substrates. For films deposited on all three substrates, the volume fraction of the monoclinic phase increased with increasing film thickness, with the SiO₂ substrate having the lowest monoclinic phase volume fraction at all film thicknesses tested. The grain size of the films, which is an important factor for the formation of the ferroelectric phase, remained almost constant at about 10 nm in diameter regardless of the film thickness and type of substrate utilized. Ferroelectricity was observed for the 17 nm-thick films deposited on SiO₂ and Si substrates, and the maximum remanent polarization (P_r) value of 9.3 µC/cm² was obtained for films deposited on the SiO₂ substrate. In contrast, ferroelectricity with P_r=4.4 µC/cm² was observed only for film on SiO₂ substrate in case of 55 nm-thick films. These results suggest that the films under in-plane tensile strain results in the larger ferroelectricity for 17 nm-thick films and have a ferroelectricity up to 55 nm-thick films.     

Experimental study for high effective mobility with directly deposited HfO2/La2O3 MOSFET

We experimentally examine the effective mobility in nMOSFETs with La₂O₃ gate dielectrics without SiO_x-based interfacial layer. The reduced mobility is mainly caused by fixed charges in High-k gate dielectrics and the contribution of the interface state density is approximately 30% at N_s = 5 × 10¹¹ cm^?2 in the low 10¹¹ cm^?2 eV^?1 order. It is considered that one of the effective methods for improving mobility is to utilize La-silicate layer formed by high temperature annealing. However, there essentially exists trade-off relationship between high temperature annealing and small EOT.     

Microwave dielectric properties of (1 − x)(Mg0.95Co0.05)TiO3– xCa0.6La0.8/3TiO3 ceramics with V2O5 addition

The microstructures and the microwave dielectric properties of the (1 − x)(Mg_0.95Co_0.05)TiO₃–xCa_0.6La_0.8/3TiO₃ ceramic system were investigated. In order to achieve a temperature-stable material, we studied a method of combining a positive temperature coefficient material with a negative one. Ca_0.6La_0.8/3TiO₃ has dielectric properties of dielectric constant ε_r ∼ 109, Q × f value ∼ 17,600 GHz and a large positive τ_f value ∼ 213 ppm/°C. (Mg_0.95Co_0.05)TiO₃ ceramics possesses high dielectric constant (ε_r ∼ 16.8), high quality factor (Q × f value ∼ 230,000 GHz), and negative τ_f value (−54 ppm/°C). As the x value varies from 0.1 to 0.8, (1 − x)(Mg_0.95Co_0.05)TiO₃–xCa_0.6La_0.8/3TiO₃ ceramic system has the dielectric properties as follows: 21.55 < ε_r < 75.44, 21,000 < Q × f < 90,000 and −10 < τ_f < 140. By appropriately adjusting the x value in the (1 − x)(Mg_0.95Co_0.05)TiO₃–xCa_0.6La_0.8/3TiO₃ ceramic system, zero τ_f value can be achieved. With x = 0.15, a dielectric constant ε_r ∼ 25.78, a Q × f value ∼ 84,000 GHz (at 9 GHz), and a τ_f value ∼ 2 ppm/°C were obtained for 0.85(Mg_0.95Co_0.05)TiO₃–0.15Ca_0.6La_0.8/3TiO₃ ceramics sintered at 1400 °C for 4 h. For practical application in communication systems, it is desirable to be able to sinter at lower temperatures. Therefore, V₂O₅ was as a sintering aid for lowering the sintering temperature of0.85(Mg_0.95Co_0.05)TiO₃–0.15Ca_0.6La_0.8/3TiO₃ ceramics. At the same time, the 0.85(Mg_0.95Co_0.05)TiO₃–0.15Ca_0.6La_0.8/3TiO₃ ceramic system with 0.5 wt% V₂O₅ can be obtained good properties at the microwave frequencies for 1200 °C.     

Highly ordered C60 films on epitaxial Fe/MgO(0 0 1) surfaces for organic spintronics

Hybrid interfaces between ferromagnetic surfaces and carbon-based molecules play an important role in organic spintronics. The fabrication of devices with well defined interfaces remains challenging, however, hampering microscopic understanding of their operation mechanisms. We have studied the crystallinity and molecular ordering of C₆₀ films on epitaxial Fe/MgO(0 0 1) surfaces, using X-ray diffraction and scanning tunneling microscopy (STM). Both techniques confirm that fcc molecular C₆₀ films with a (1 1 1)-texture can be fabricated on epitaxial bcc-Fe(0 0 1) surfaces at elevated growth temperatures (100–130 °C). STM measurements show that C₆₀ monolayers deposited at 130 °C are highly ordered, exhibiting quasi-hexagonal arrangements on the Fe(0 0 1) surface oriented along the [1 0 0] and [0 1 0] directions. The mismatch between the surface lattice of the monolayer and the bulk fcc C₆₀ lattice prevents epitaxial overgrowth of multilayers.     

Paramagnetic Ge dangling bond type defects at (1 0 0)Si1−xGex/SiO2 interfaces (Invited Paper)

The work addresses the occurrence of Ge dangling bond type point defects at Ge_xSi_1?x/insulator interfaces as evidenced by conventional electron spin resonance (ESR) spectroscopy. Using multifrequency ESR, we report on the observation and characterization of a first nontrigonal Ge dangling bond (DB)-type interface defect in SiO₂/(1 0 0)Ge_xSi_1?x/SiO₂/(1 0 0)Si heterostructures (0.27 ? x ? 0.93) manufactured by the condensation technique, a selective oxidation method enabling Ge enrichment of a buried epitaxial Si-rich SiGe layer. The center, exhibiting monoclinic-I (C_2v) symmetry is observed in highest densities of ～7 × 10¹² cm^?2 of Ge_xSi_1?x/SiO₂ interface for x ～ 0.7, to disappear for x outside the ]0.45–0.87[ interval, with remarkably no copresence of Si P_b-type centers. Neither are trigonal Ge DB centers observed, enabling unequivocal spectral analysis. Initial study of the defect passivation under annealing in molecular H₂ has been carried out. On the basis of all data the defect is depicted as a Ge P_b1-type center, i.e., distinct from a trigonal basic Ge P_b(0)-type center (Ge₃Ge). The modalities of the defect’s occurrence as unique interface mismatch healing defect is discussed, which may widen our understanding of interfacial DB centers in general.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Direct bonding of Si wafer pairs with SiO2 and Si3N4 films with a fast linear annealing

2000 Å-SiO₂/Si(1 0 0) and 560 Å-Si₃N₄/Si(1 0 0) wafers, that are 10 cm in diameter, were directly bonded using a rapid thermal annealing method, so-called fast linear annealing (FLA), in which two wafers scanned with a high-power halogen lamp. It was demonstrated that at lamp power of 550 W, corresponding to the surface temperature of ∼450°C, the measured bonded area was close to 100%. At the same lamp power, the bond strength of the SiO₂∥Si₃N₄ wafer pair reached 2500 mJ/m², which was attained only above 1000°C with conventional furnace annealing for 2 h. The results clearly show that the FLA method is far superior in producing high-quality directly bonded Si wafer pairs with SiO₂ and Si₃N₄ films (Si/SiO₂∥Si₃N₄/Si) compared to the conventional method.     

Degradation kinetics of ultrathin HfO2 layers on Si(1 0 0) during vacuum annealing monitored with in situ XPS/LEIS and ex situ AFM

The evolution of HfO₂(3–5 nm)/SiO₂(0.5 nm)/Si(1 0 0) stacks during vacuum annealing was monitored in situ with the combination of X-ray photoelectron spectroscopy and low energy ion scattering techniques and supplemented with atomic force microscopy analysis to investigate the mechanism that triggers HfO₂ degradation with Hf silicide formation. The reduction of SiO₂ interfacial layer and the formation of local paths for SiO escape into vacuum are believed to be critical at vacuum annealing above T > 850 °C for the reaction between HfO₂ and Si to start and eventually lead to the degradation of the former.     

Scaling the MOSFET gate dielectric: From high-k to higher-k? (Invited Paper)

We discuss options for metal–oxide-semiconductor field-effect transistor (MOSFET) gate stack scaling with thin titanium nitride metal gate electrodes and high-permittivity (‘high-k’) gate dielectrics, aimed at gate-first integration schemes. Both options are based on further increasing permittivity of the dielectric stack. First, we show that hafnium-based stacks such as TiN/HfO₂ can be scaled to capacitance equivalent thickness in inversion (T_inv) of 10 Å and equivalent oxide thickness (EOT) of 6 Å by using silicon nitride instead of silicon oxide as a high-k/channel interfacial layer. This is based on the higher dielectric constant of Si₃N₄ and on its resistance to oxidation. Although the nitrogen introduces positive fixed charges, carrier mobility is not degraded. Secondly, we investigate whether Ti-based ‘higher-k’ dielectrics have the potential to ultimately replace Hf. We discuss oxygen loss from TiO₂ as a main challenge, and identify two migration pathways for such oxygen atoms: In addition to well-known down-diffusion and channel Si oxidation, we have newly observed oxygen up-diffusion through the TiN metal gate, forming SiO₂ at the poly-Si contact. We further address the performance of Si₃N₄ and HfO₂ as oxygen barrier layers.