Characterization of CoxNiyO hybrid metal oxide nanoparticles as charge trapping nodes in nonvolatile memory devices

The Co_xNi_yO hybrid metal oxide nanoparticles (HMONs) embedded in the HfO_xN_y high-k dielectric as charge trapping nodes of the nonvolatile memory devices have been formed via the chemical vapor deposition using the Co/Ni acetate calcined and reduced in the Ar/NH₃ ambient. A charge trap density of 8.96 × 10¹¹ cm^?2 and a flatband voltage shift of 500 mV were estimated by the appearance of the hysteresis in the capacitance–voltage (C–V) measurements during the ±5 V sweep. Scanning electron microscopy image displays that the Co_xNi_yO HMONs with a diameter of ～10–20 nm and a surface density of ～1 × 10¹⁰ cm^?2 were obtained. The mechanism related to the writing characteristics are mainly resulted from the holes trapping. Compared with those devices with the Co_xNi_yO HMONs formed by the dip-coated technique, memory devices with the Co_xNi_yO HMONs fabricated by the drop-coated technique show improved surface properties between the Co_xNi_yO HMONs and the HfON as well as electrical characteristics.     

Characterization of various alloying metal oxide nanoparticles embedded in HfOxNy as charge trapping nodes in nonvolatile memory devices

This work compares Co_xMo_yO, Co_xFe_yO and Fe_xMo_yO alloying metal oxide nanoparticles (AMONs) that were individually embedded in HfO_xN_y high-k dielectric as charge trapping nodes. They were formed by chemical vapor deposition using Co/Mo, Co/Fe and Fe/Mo acetate, respectively, calcined and reduced in Ar/NH₃ ambient. The effects of various pre-treatments on Co_xMo_yO, Co_xFe_yO and Fe_xMo_yO AMONs preparation were investigated. The results indicate that the larger charge trap density, larger memory window and better programming characteristics of Co_xMo_yO AMONs are attributable to their higher surface density and smaller diameter. The average collected charge in each Co_xMo_yO AMON is the smallest among three AMONs, revealing that a local leakage path is associated with the least charge loss. The main mechanism that governs the programming characteristics involves the trapping of holes.     

Formation of stacked ruthenium nanocrystals embedded in SiO2 for nonvolatile memory applications

n metal oxide semiconductor (MOS)capacitors fabricated by the former method, which are much better than 4.6 Ⅴ and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.     

面向非挥发存储器应用的叠层Ru纳米晶材料的制备与特性

Two methods are proposed to fabricate stacked ruthenium （Ru） nanocrystals （NCs）： rapid thermal annealing （RTA） for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density of Ru NCs are 2-4 nm and 3 × 10^12 cm^-2 for the former method, compared to 3-7 nm and 2 ×10^12 cm^-2 for the latter. Because of the higher surface trap density and more uniform electron tunneling path between upper and lower Ru NCs, a 5.2 V memory window and 1 V after a period of 10 years are observed in metal oxide semiconductor （MOS） capacitors fabricated by the former method, which are much better than 4.6 V and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.     

A nonvolatile semiconductor memory device in 6H-SiC for harsh environment applications

An electrically erasable programmable read-only memory (EEPROM) cell fabricated on a 6H-SiC substrate is reported. It is the first fully functional SiC EEPROM device. This device uses a generic double-polysilicon-gate configuration. It has been tested at both room temperature and elevated temperatures, up to 200/spl deg/C, to demonstrate full programmability. The threshold voltage shifts between programmed and erased states, at all tested temperatures, are larger than 4.5 V. In both states, the device functions satisfactorily as an n-type MOSFET. Charge retention time is more than 24 h at room temperature.     

Organic bistable memory device using MoO3 nanocrystal as a charge trapping center

Organic bistable memory devices (OBDs) with MoO₃ as a nanocrystal inside organic layer were developed and bistability of MoO₃ based OBDs was investigated. High on/off ratio over 200 was obtained at a low reading voltage of 1 V. MoO₃ OBDs could be electrically switched between high conductance state and low conductance state over more than 100 cycles and space charge limited conduction mechanism dominated switching behavior in MoO₃ OBDs.     

A highly robust process integration with scaled ONO interpolydielectrics for embedded nonvolatile memory applications

We have developed a process sequence for a flash EEPROM memory embedded in an advanced microcontroller circuit. This process simultaneously forms a thick top oxide on the interpoly ONO dielectric in the memory array and a stacked gate-oxide for the logic transistors. We have fabricated one-transistor, flash bit-cells with good data retention characteristics that incorporate a 17 nm ONO film along with high-quality stacked gate oxides     

Si-nanoclusters embedded into epitaxial rare earth oxides: Potential candidate for nonvolatile memory applications

Using an unconventional approach, single crystalline Si-nanoclusters (Si-NCs) with uniform size and higher density were embedded into epitaxial rare earth oxide with two-dimensional spatial arrangements at a defined distance from the substrate using solid source molecular beam epitaxy (MBE) technique.The incorporated Si-NCs with average size of 5 nm and density of 2 × 10¹² cm⁻² exhibit charge storage capacity with promising retention (∼10⁷ s) and endurance (10⁵ write/erase cycles) characteristics. The Pt/Gd₂O₃ (Si-NC)/Si (MOS) basic memory cells with embedded Si-nanoclusters display large programming window (∼1.5-2 V) and fast writing speed. With such properties demonstrated, we believe that the Si-NCs embedded in epitaxial Gd₂O₃ could be potential candidate for high density nonvolatile memory devices in the future.     

A 2-bit highly scalable nonvolatile memory cell with two electrically isolated charge trapping sites

A highly scalable 2-bit nonvolatile memory (NVM) cell using two electrically isolated charge trapping sites is proposed and demonstrated by numerical device simulation. The operational mechanisms including read, program, erase and inhibit in an array structure are studied in detail. This double storage capability per single cell and highly scalable structure is very suitable for high density nanometric NVM applications.     

Gadolinium-based metal oxide for nonvolatile memory applications

In this study, the memory characteristic of a gadolinium (Gd)-based oxide charge storage layer was demonstrated. The metal/oxide/high-k/oxide/silicon (MOHOS)-type memories were fabricated by using two different charge storage layers. The Gd₂O₃ nanocrystal (Gd₂O₃-NC) was used as a charge storage layer due to the discrete nodes, while the HfGdO high-k material was used as a charge storage layer due to the existence of discrete traps. In the case of Gd₂O₃-NC memory, a combination of X-ray photoelectron spectroscopy (XPS) and ultraviolet (UV)–visible spectrophotometer analysis was used in this study to extract the valence band location and the band-gap of the Gd₂O₃-NC layer. The retention characteristic was also analyzed to extract the trapping level in Gd₂O₃-NC, based on the relationship between trapping energy and discharging time. A band diagram was created to characterize the memory effect of the Gd₂O₃-NC memory. In the case of HfGdO SONOS-type memory, the electrical and physical studies were conducted for HfGdO charge-trapping layers deposited by a dual-sputtered method for silicon–oxide–nitride–oxide–silicon (SONOS)-type nonvolatile memory. The Hf/Gd dual-sputtered power ratio and the Ar/O₂ gas flow ratio were optimized. It was observed that the nonstoichiometric GdO (2 0 0) structure may be the main charge-trapping site for the memory. The memory samples with Hf/Gd = 150/150 and Ar/O₂ = 20/5 exhibited better electrical performance. A physical model is proposed to further explain the retention mechanism.     

Effect of thickness of polymer electret on charge trapping properties of pentacene-based nonvolatile field-effect transistor memory

In this report, a set of pentacene-based organic field-effect transistor (OFET) memory devices using different thicknesses (ranged from 17.8 to 100.4 nm) of Poly (N-vinylcarbazole) (PVK) as charge trapping layers were fabricated, and the dependences of thickness on charge trapping behaviors were systematically investigated. As the thickness increased, the charge trapping capacity shows a Gaussian distributed growth behavior while the surface tunneling distance demonstrates the property of exponential decrease, which is ascribed to the synergistic effects of potential redistribution of trapped charge carriers and the co-existence of direct tunneling and Fowler–Nordheim (FN) tunneling. The optimum thickness (d_ot) to possess the most efficient charge trapping properties, which means a reasonably low programming voltage and high charge trapping capacity with good bias stress stability, is approximately 40 ± 5 nm. By calculating the threshold thickness (d_th) of PVK for an ultrathin memory, we proposed a model of superficial tunneling distance to deconstruct the continuous chargeable polymer electret-based OFET memory. Our work provided a quantitative evaluation method and can improve the understanding of charge trapping process from the aspect of electret thickness.     

Nb-doped Ga2O3 as charge-trapping layer for nonvolatile memory applications

The charge-trapping properties of Nb-doped Ga₂O₃ are investigated by using an Al/Al₂O₃/GaNbO/SiO₂/Si structure. Compared with the memory capacitor with pure Ga₂O₃, the one with lightly Nb-doped Ga₂O₃ shows better charge-trapping characteristics, including larger memory window (5.5 V at ± 6 V sweeping voltage), higher programming and erasing speeds due to its higher trapping efficiency resulted from increased trap density induced by the Nb doping. The sample with heavily Nb-doped Ga₂O₃ also shows improvements compared with the one with pure Ga₂O₃, but not as large as those for the lightly Nb-doped sample due to defects generated by excessive Nb doping. Erase saturation phenomenon is observed in all the samples, and can be suppressed by hole traps created by the Nb doping.     

Overcoming the “retention vs. voltage” trade-off in nonvolatile organic memory: Ag nanoparticles covered with dipolar self-assembled monolayers as robust charge storage nodes

Organic non-volatile memory devices with significantly enhanced retention are explored with C₆₀ thin-film transistors containing silver nanoparticles (Ag-NPs) within gate dielectrics as charge storage nodes. Dipolar self-assembled monolayers covering Ag-NPs effectively prevent stored charges from being lost by providing an additional energy threshold for back-tunneling process. This enables long retention even with ultrathin tunneling dielectric layers, providing a simple means to realize long retention without causing an excessive increase in operation voltage.     

Electrical switching and conduction mechanisms of nonvolatile write-once-read-many-times memory devices with ZnO nanoparticles embedded in polyvinylpyrrolidone

We reported on the influence of zinc oxide nanoparticles (ZnO NPs) on the electrical bistable behavior of nonvolatile write-once-read-many-times (WORM) memory devices based on an indium-tin oxide/polyvinylpyrrolidone (PVP):ZnO NPs/aluminum (ITO/PVP:ZnO/Al) structure. The maximum ON/OFF current ratio of the nonvolatile WORM memory devices was approximately 3 × 10³ and the devices remained in the ON state even after the applied voltage was turned off. In addition, reliability studies for response time and once write/continuous read operations of the optimal ZnO NPs concentration are presented. The response times of both rise-time and fall-time were about 3 and 6 μs respectively. The conduction mechanisms of all voltage regions of the device were analyzed by theoretical models and electron trapping in the ZnO NPs of the electron tunneling among a PVP matrix was discussed.     

新型多位非均匀沟道电荷俘获型存储器及新型虚拟源端的NAND阵列结构

为了解决传统多位存储NAND型存储器中位与位互相干扰的问题,本文提出了一种新型的用于多位存储的非均匀沟道电荷俘获型存储器及新型NAND结构。该器件能够很好地抑制SBE效应从而提供3比特/单元的存储能力。由于n-缓冲区的存在,由SBE效应导致的阈值电压漂移能够减小到400mV,在3比特/单元的存储能力下最小阈值电压窗口可以达到750mV。本器件还引入了富硅氮氧化硅层最为电荷俘获层,从而很好地提高了器件的电荷保持特性。     

Novel multi-bit non-uniform channel charge trapping memory device with virtual-source NAND flash array

In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device,this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory(NUC-CTM) device with virtual-source NAND-type array architecture,which can effectively restrain the second-bit effect(SBE) and provide 3-bit per cell capability.Owing to the n~- buffer region,the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between ...     

Hafnium aluminum oxide as charge storage and blocking-oxide layers in SONOS-type nonvolatile memory for high-speed operation

The charge storage and program/erase mechanisms in polysilicon-oxide-nitride-oxide-silicon (SONOS) memory structures with charge-storage layers of different materials are investigated in this paper. In particular, the use of a HfAlO charge-storage layer in a SONOS-type memory structure is proposed. Compared to other high-/spl kappa/ charge-storage layers, HfAlO has the advantage of high-speed program/erase of HfO/sub 2/ as well as the good charge-retention time of Al/sub 2/O/sub 3/, which makes HfAlO a promising candidate for the charge-storage layer in a SONOS-type memory. The use of HfAlO with different HfO/sub 2/ and Al/sub 2/O/sub 3/ compositions as a blocking-oxide layer in SONOS-type structures is also investigated.     

Synergistic effect in organic field-effect transistor nonvolatile memory utilizing bimetal nanoparticles as nano-floating-gate

A solution-processed bimetal nano-floating-gate, with a combination of stabilized Ag and Pt nanoparticles, is utilized to achieve high-performance organic field-effect transistor nonvolatile memories. The device based on the Ag–Pt nano-floating-gate shows the synergistic superiority in memory performance compared with the corresponding Ag-only and Pt-only devices. The Ag and Pt nanoparticles are found to prefer hole and electron trapping, respectively. Upon the blending of the Ag and Pt nanoparticles, both hole and electron trapping are significantly enhanced and thus realize a large memory window. The dipole enhancement induced local work function change for both Ag and Pt is proposed to be responsible for the synergistic effect, and this physical picture is supported by the electronic structure results. It is concluded that using a hybrid nano-floating-gate is a promising strategy to optimize the device performance of organic field-effect transistor nonvolatile memories.     

Resistance switching of the nonstoichiometric zirconium oxide for nonvolatile memory applications

The resistance switching behavior and switching mechanism of nonstoichiometric zirconium oxide thin films were investigated for nonvolatile memory application. The Pt/ZrO/sub x//p/sup +/-Si sandwich structure fabricated by reactive sputtering shows two stable resistance states. By applying proper bias, resistance switching from one to another state can be obtained. The composition in ZrO/sub x/ thin films were confirmed from X-ray photoelectron spectroscope (XPS) analysis, which showed three layers such as top stoichiometric ZrO/sub 2/ layer with high resistance, transition region with medium resistance, and conducting ZrO/sub x/ bulk layer. The resistance switching can be explained by electron trapping and detrapping of excess Zr/sup +/ ions in transition layer which control the distribution of electric field inside the oxide, and, hence the current flow.