Interfacial layer quality effects on low-frequency noise (1/f) in p-MOSFETs with advanced gate stacks

The effects of interfacial layer quality on the low-frequency noise behavior of p-channel MOSFETs with high-κ gate dielectric and metal gate are investigated. Devices with chemically grown SiO₂ interfacial layers (0.8 nm) are compared with N₂O (0.8 nm) interfacial oxides. A 0.4 nm SiO₂ interfacial layer device is used for comparison purposes. A cross-over kind of behavior has been observed in N₂O devices, which occur at lower gate voltages (1.2–1.3 V) when normalized spectral densities and input referred noise are investigated. This behavior is found to be closely related to the observed transconductance variation in these devices. The dominant mechanism of 1/f noise is found to be Hooge’s mobility fluctuations. Hooge’s parameter, as a figure of merit, shows an increase for 0.4 nm devices when compared to 0.8 nm devices, while 0.8 nm N₂O devices confirm their cross-over nature.     

Application of combinatorial methodologies for work function engineering of metal gate/high-κ advanced gate stacks

This paper uses combinatorial methodologies to investigate the effect of TaN-AlN metal gate electrode composition on the work function, for (TaN-AlN)/Hf-Si-O/SiO₂/Si capacitors. We demonstrate the efficacy of the combinatorial technique by plotting work function for more than thirty Ta_1-xAl_xN_y compositions, with x varying from 0.05 to 0.50. The work function is shown to continuously decrease, from about 4.9 to about 4.7 eV, over this range. Over the same range, oxide fixed charge is seen to go from about -2.5 × 10¹² cm⁻³ to about zero. The work functions reported here are about 0.1 eV higher than in a previous study, but are still about 0.2 eV smaller than required for PMOS device applications.     

Abrupt breakdown in dielectric/metal gate stacks: a potential reliability limitation?

In downscaled poly-Si gate MOSFET devices reliability margin is gained by progressive wearout. When the poly-Si gate is replaced with a metal gate, the slow wearout phase observed in ultrathin SiON and HfSiON dielectrics with poly-Si gate disappears, and with it, the reliability margin. We demonstrate for several combinations of dielectric and gate materials that the large abrupt current increase (/spl Delta/I) as compared to poly-Si is not likely due to process issues, but is an intrinsic property of the dielectric/metal gate stack. The occurrence of large /spl Delta/I is a potential limitation for the reliability of metal gate devices.     

Impact of the interfacial layer on the low-frequency noise (1/f) behavior of MOSFETs with advanced gate stacks

The impact of the interfacial layer thickness on the low-frequency (LF) noise (1/f noise) behavior of n- and p-channel MOSFETs with high-/spl kappa/ gate dielectrics and metal gates is investigated. Decreasing the interfacial layer thickness from 0.8 to 0.4 nm affects the 1/f noise in two ways. 1) The mobility fluctuations mechanism becomes the main source of 1/f noise not only on pMOS devices, as usually observed, but also on nMOS devices. 2) A significant increase of the Hooge's parameter is observed for both types of MOSFETs. These experimental findings indicate that bringing the high-/spl kappa/ layer closer to the Si-SiO/sub 2/ interface enhances the 1/f noise mainly due to mobility fluctuations.     

The progress and challenges of threshold voltage control of high-k/metal-gated devices for advanced technologies (Invited Paper)

This paper discusses recent progress in and challenges of threshold voltage control for advanced high-k/metal-gated (HKMG) devices. It presents the impact on threshold voltage (V_t) control of incorporating La and Al into HKMG devices. A dipole moment model explaining V_t tuning of HfSiON/metal-gated MOSFETs is proposed. In addition, a dual channel scheme that allows La₂O₃ capping in NMOS and a SiGe channel in PMOS to achieve acceptable V_t for HKMG CMOS devices will be discussed. Also shown is the impact of the robustness of the SiO₂/Si interface on the HKMG MOSFET V_t-equivalent oxide thickness (EOT) roll-off. Finally, techniques to improve the interface quality of a HKMG stack will be discussed.     

Process dependence of BTI reliability in advanced HK MG stacks

Bias temperature instabilities (BTI) reliability is investigated in advanced dielectric stacks. We show that mobility performance and NBTI reliability are strongly correlated and that they are affected by the diffusion of nitrogen species N at the Si interface. PBTI, more sensitive to bulk oxide traps, is strongly reduced in very thin dielectric films. Reducing the metal gate thickness favors the reduction of mobility degradations and NBTI, but, also strongly enhances PBTI, due to a complex set of reactions in the gate oxide. Trade off must be found to obtain a great trade off between device performance and reliability requirements.     

Some issues in advanced CMOS gate stack performance and reliability

This paper summarizes and analyzes some of our previous works on the advanced gate stacks for CMOS transistors focused on the following two topics: 1. Frequency dependence of Dynamic Bias Temperature Instability (DBTI) and the transistor degradation mechanism, 2. A novel way for metal gate Effective Work Function (EWF) modulation by incorporation of lanthanum elements in HfO₂ gate dielectric.     

Modulation of the effective work function of fully-silicided (FUSI) gate stacks

A systematic analysis of the different methods of work function (WF) tuning for gate stacks using fully silicided (FUSI) gate electrodes is presented. We show that FUSI gates have the potential to meet the WF requirements for future nodes, including high performance applications, achieving band edge WF, with total WF range of up to ∼900 meV. The introduction of dopants (such as Sb, As, P, B) by ion implantation is shown to be effective to tune the WF of NiSi or Ni₃Si₂ on SiO₂ or SiON by ∼550 meV, but is ineffective on HfSiON or for Ni-richer silicides. Different silicide phases can be used for Ni FUSI gates on HfSiON dielectrics, taking advantage of the higher WF of metal-rich silicides, achieving a WF range of ∼400 meV. This method is not effective, however, on SiON dielectrics. The introduction of Lanthanides by several techniques (such as dielectric cap deposition, ion implantation into poly-Si, or at metal deposition) that result in the modification of the dielectric, is found, for Ni FUSI gates, to achieve low WF (∼4.0 eV) suitable for NMOS. Similarly, incorporation of Al can be used to achieve PMOS type WF, as well as the use of metal-rich Ni and/or Pt based FUSI gates (with WF as high as 5.0 eV).     

Theoretical models for work function control (Invited Paper)

We have studied Fermi level pinning (FLP) of Hf-based high-k gate stacks based on thermodynamics based on an O vacancy model. Our study shows that FLP cannot be avoided when the system is under thermal equilibrium. O exposure to aim O vacancy elimination is not effective, since O vacancy elimination condition is equivalent to the Si substrate oxidation which leads to the increase in Equivalent oxide thickness (EOT). We also studied the mechanism of FLP induced by the reduction with H₂ anneal. FLP with H₂ anneal is governed by the O vacancy annihilation reaction by reducing SiO₂ interface layer. Based on these considerations, we propose some recipes for obtaining band-edge-work-function metals.     

Density functional theory of high-k dielectric gate stacks

Density functional theory is the method of choice in theoretical materials science. It has also proved to be a useful tool in device engineering, particularly at nanoscale and when novel materials are involved. In this paper, we briefly review recent theoretical results in the area of the advanced gate stack materials engineering.     

Improvements of ozone surface treatment on the electrical characteristics and reliability in HfO2 gate stacks

In this study, we improved the interfacial properties of high-κ gate stacks with the surface treatment of ozonated water prior to deposition of hafnium oxide (HfO₂). We demonstrated that the Ozone-oxide improved the electrical properties of the HfO₂ gate stack interface in terms of its smoother interface, lower leakage current density, narrower hysteresis width, superior charge trapping effect, and reliability. From these experimental results, we believe that treatment with ozone is an efficient method for the preparation of high-quality interfaces between HfO₂ and silicon surfaces.     

Charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes

A detailed study on charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al/sub 2/O/sub 3/ film, whereas for gate injection mainly hole trapping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence (q/sub inj/ /spl sim/ 1 mC/cm/sup 2/). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al/sub 2/O/sub 3/ thickness. In the case of substrate injection, reliability is limited by the bulk of the Al/sub 2/O/sub 3/ layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.     

Reliability issues and modeling of Flash and post-Flash memory (Invited Paper)

Flash memory, in particular NAND, has been an enabling technology for portable applications for the last two decades. The strength of Flash is its excellent scaling capability, allowing an ever increasing density at a decreasing cost and maintained reliability. However, the geometrical scaling of the cell exacerbates charge loss and fluctuation effects. On the other hand, new post-Flash memory technologies are being proposed, with different storage concepts and reliability physics. This review discusses the major reliability issues for Flash, with emphasis on the physical mechanisms and modeling. The reliability of charge trap and resistive memories, such as phase change and resistive switching memories, is addressed.     

Roadmap for 22 nm and beyond (Invited Paper)

The down-scaling is still the most important and effective way for achieving the high-performance logic CMOS operation with low power, regardless of its concern for the technological difficulties, and thus, the past shrinking trend of the gate-length has been very aggressive. In this paper, logic CMOS technology roadmap for ‘22 nm and beyond’ is described with ITRS (International Technology Roadmap for Semiconductor) as a reference. In the ITRS 2008 Update published just recently, there has been some significant change in the trend of the gate length. The future gate-length shrinking trend predicted in the past several versions of the ITRS has been too aggressive even for the most advanced semiconductor companies to catch up, and thus, the predicted trend has been amended to be less aggressive from the ITRS 2008 Update, resulting in the delay in the gate-length shrinkage for 3 years in the short term and 5 years in the long term from those predicted in ITRS 2007. Corresponding to this, the pace of the introduction of new technologies becomes slower. For the long term, the limit of the downsizing is a big concern. The limit is expected to be at the gate length of around 5 nm because of the too huge off-leakage current in the entire chip. Until that we will have probably six more generations or ‘technology nodes’, considering that we are now in the so-called 45 nm generation. It would take probably 20–30 years until we reach the final limit, because the duration between the generations will become longer when approaching the limit. In order to suppress the off-leakage current, double gate (DG) or fin-FET type MOSFETs are the most promising. Then, it is a natural extension for DG FETs to evolve to Si-nanowire MOSFETs as the ultimate structure of transistors for CMOS circuit applications. Si-nanowire FETs are more attractive than the conventional DG FETs because of higher on-current conduction due to their quantum nature and also because of their adoptability for high-density integration including that of 3D. Then, what will come next after reaching the final limit of the downsizing? The answer is new algorithm. In the latter half of this century, the application of algorithm used for the natural bio system such as the brains of insects and even human will make the integrated circuits operation tremendously high efficiency. Much higher performance with ultimately low power consumption will be realized.     

High-k dielectrics for future generation memory devices (Invited Paper)

The requirements and development of high-k dielectric films for application in storage cells of future generation flash and Dynamic Random Access Memory (DRAM) devices are reviewed. Dielectrics with k-value in the 9–30 range are studied as insulators between charge storage layers and control gates in flash devices. For this application, large band gaps (>6 eV) and band offsets are required, as well as low trap densities. Materials studied include aluminates and scandates. For DRAM metal–insulator–metal (MIM) capacitors, aggressive scaling of the equivalent oxide thickness (with targets down to 0.3 nm) drives the research towards dielectrics with k-values >50. Due to the high aspect ratio of MIMCap structures, highly conformal deposition techniques are needed, triggering a substantial effort to develop Atomic Layer Deposition (ALD) processes for the deposition of metal gates and high-k dielectrics. Materials studied include Sr- and Ba-based perovskites, with SrTiO₃ as one of the most promising candidates, as well as tantalates, titanates and niobates.     

Integration of Gd silicate/TiN gate stacks into SOI n-MOSFETs

In this work we describe the gate first integration of gadolinium silicate (GdSiO) high-k dielectrics and metal gate electrodes into SOI n-MOSFETs. Fully functional devices are achieved and compared to reference devices with standard SiO₂. Analysis of electron transport in these gate stacks is performed by specific MOSFET test structures that enable extraction of intrinsic inversion channel mobility. Attractive peak mobilities of 170 cm²/Vs have been found for GdSiO.     

Bond strain and defects at interfaces in high-k gate stacks

The performance and reliability of aggressively-scaled field effect transistors are determined in large part by electronically-active defects and defect precursors at the Si–SiO₂, and internal SiO₂–high-k dielectric interfaces. A crucial aspect of reducing interfacial defects and defect precursors is associated with bond strain-driven bonding interfacial self-organizations that take place during high temperature annealing in inert ambients. The interfacial self-organizations, and intrinsic interface defects are addressed through an extension of bond constraint theory from bulk glasses to interfaces between non-crystalline SiO₂, and (i) crystalline Si, and (ii) non-crystalline and crystalline alternative gate dielectric materials.     

Surface passivation and implications on high mobility channel performance (Invited Paper)

We review our recent studies of the passivation of the GaAs and InGaAs surface using a combination of in situ and ex situ surface analysis and capacitor measurements. We find that the control of Ga-oxides in particular appears to play an important role in understanding the characteristics of III–V MOS devices.     

Impact of the TiN electrode deposition on the HfO2 band gap for advanced MOSFET gate stacks

The impact of the deposition of a TiN electrode on the high-k oxide HfO₂ has been investigated, focussing on the dielectric band gap. After the gate elaboration, a non-destructive approach combining Spectroscopic Ellipsometry (SE), Reflection Electron Energy Loss Spectroscopy (REELS) and X-ray Photoelectron Spectroscopy (XPS) was developed to probe the buried metal/high-k interface. The overall optical band gap is 5.9 ± 0.1 eV with no change after the metal gate deposition. A local reduction of 1 eV is measured near the TiN layer, due to N diffusion at the interface creating N 2p states at the top of the HfO₂ valence band. Increased disorder and defects are identified in the high-k after gate elaboration by XPS, REELS and SE.     

Reliability of charge trapping memories with high-k control dielectrics (Invited Paper)

In this paper, we evaluate the potentiality of high-k materials (Al₂O₃, HfO₂ and HfAlO) for interpoly application in non-volatile memories. A study of the leakage currents of high-k based capacitors allowed to discuss the retention performances at room and high temperatures of high-k interpoly dielectrics. High-k materials are then integrated as control dielectrics in silicon nanocrystal and SONOS (Si/SiO₂/Si₃N₄/SiO₂/Si) memories. The role of the high-k layer on the memory performances is discussed; a particular attention being devoted to the retention characteristics. Analytical models, combined with experimental results obtained on various structures allowed to analyze the mechanisms involved during retention.