Integration of Gd silicate/TiN gate stacks into SOI n-MOSFETs

In this work we describe the gate first integration of gadolinium silicate (GdSiO) high-k dielectrics and metal gate electrodes into SOI n-MOSFETs. Fully functional devices are achieved and compared to reference devices with standard SiO₂. Analysis of electron transport in these gate stacks is performed by specific MOSFET test structures that enable extraction of intrinsic inversion channel mobility. Attractive peak mobilities of 170 cm²/Vs have been found for GdSiO.     

Scaling the MOSFET gate dielectric: From high-k to higher-k? (Invited Paper)

We discuss options for metal–oxide-semiconductor field-effect transistor (MOSFET) gate stack scaling with thin titanium nitride metal gate electrodes and high-permittivity (‘high-k’) gate dielectrics, aimed at gate-first integration schemes. Both options are based on further increasing permittivity of the dielectric stack. First, we show that hafnium-based stacks such as TiN/HfO₂ can be scaled to capacitance equivalent thickness in inversion (T_inv) of 10 Å and equivalent oxide thickness (EOT) of 6 Å by using silicon nitride instead of silicon oxide as a high-k/channel interfacial layer. This is based on the higher dielectric constant of Si₃N₄ and on its resistance to oxidation. Although the nitrogen introduces positive fixed charges, carrier mobility is not degraded. Secondly, we investigate whether Ti-based ‘higher-k’ dielectrics have the potential to ultimately replace Hf. We discuss oxygen loss from TiO₂ as a main challenge, and identify two migration pathways for such oxygen atoms: In addition to well-known down-diffusion and channel Si oxidation, we have newly observed oxygen up-diffusion through the TiN metal gate, forming SiO₂ at the poly-Si contact. We further address the performance of Si₃N₄ and HfO₂ as oxygen barrier layers.     

Gentle FUSI NiSi metal gate process for high-k dielectric screening

In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

Integration of functional epitaxial oxides into silicon: from high-k application to nanostructures

We will present results for crystalline gadolinium oxides on silicon in the cubic bixbyite structure grown by solid source molecular beam epitaxy. Additional oxygen supply during growth improves the dielectric properties significantly. Experimental results for Gd₂O₃-based MOS capacitors grown under optimized conditions show that these layers are excellent candidates for application as very thin high-k materials replacing SiO₂ in future MOS devices. We also will present a new approach for nanostructure formation which is based on solid-phase epitaxy of the Si quantum-well combined with simultaneous vapor-phase epitaxy of the insulator on top of the quantum-well. Ultra-thin single-crystalline Si buried in a single-crystalline insulator matrix with sharp interfaces was obtained by this approach on Si(111). Finally, the incorporation of crystalline Si islands into single-crystalline oxide layers will be demonstrated.     

Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO₂ formation and silicidation and equivalent oxide thickness (EOT) of 5 Å is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO₂-SiO₂ intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6 Å with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.     

Damascene TiN-Gd2O3-gate stacks: Gentle fabrication and electrical properties

In this work, we present MOS capacitors and field effect transistors with a crystalline gadolinium oxide (Gd₂O₃) gate dielectric and metal gate electrode (titanium nitride) fabricated in a gentle damascene gate last process. Details of the gate last process and initial results on MOS devices with equivalent oxide thicknesses (EOT) of 3.0 nm and 1.5 nm, respectively, are shown.     

Influence of dry and wet cleaning on the properties of rapid thermal grown and deposited gate dielectrics

Various silicon surface cleaning processes for rapid thermal in-situ polysilicon/ oxide/silicon stacked gate structures have been evaluated. Metal-oxide-semiconductor capacitors were fabricated to assess the effects of cleaning on the quality of gate oxide structures produced by both rapid thermal oxidation (RTO) and rapid thermal chemical vapor deposition (RTCVD). Excellent electrical properties have been achieved for both RTO and RTCVD gate oxides formed on silicon wafers using either an ultraviole/zone (UV/O₃) treatment or a modified RCA clean. On the contrary, poor electrical properties have been observed for RTO and RTCVD gate oxides formed on silicon wafers using a high temperature bake in Ar, H₂, or high vacuum ambient. It has also been found that the electrical properties of the RTCVD gate oxides exhibit less dependence upon cleaning conditions than those of RTO gate oxides. This work demonstrates that initial surface condition prior to gate oxide formation plays an important role in determining the quality of RTO and RTCVD gate oxides.     

Investigation of the SiSiO2 interface by surface inversion currents

An analytical solution for the current-voltage characteristics of inversion layers on p-type silicon (including drift and diffusion) is presented. The method is developed to give information on the equilibrium surface potential and to provide accurate values of the electron mobility and fixed oxide charge. Since the experimental samples are bare SiSiO₂ structures the data obtained are not influenced by the presence of a gate electrode as in usual MOS structures.     

Analysis of slow traps centres in submicron MOSFETs by random telegraph signal technique

In this paper, we present a comprehensive study of slow single traps, situated inside the gate oxide of small area (W×L=0.5×0.1 μm²) metal–oxide–semiconductor (MOS) transistors. The gate oxide of the analyzed transistors, which have been used for memory-cell applications, is composed of two SiO₂ layers—a deposited high-temperature oxide (HTO) and the thermal oxide. The interface between the two gate oxides is shown to play a significant role in the channel conduction: we observed that the presence of individual traps situated inside the gate oxide, at some angstroms from the interface with the channel, is inducing discrete variations in the drain current. Using random telegraph signal (RTS) analysis, for various temperatures and gate bias, we have determined the characteristics of these single traps: the energy position within the silicon bandgap, capture cross section and the position within the gate oxide.     

Recent development of gallium oxide thin film on GaN

Gallium nitride (GaN) has attracted much attention due to its outstanding characteristics. It may replace conventional semiconductor materials, such as silicon, that are approaching their physical limitation in terms of power handling, maximum frequency and operation temperature. The native oxide of GaN [gallium oxide (Ga₂O₃)] has become a potential candidate of gate oxide in GaN-based high power metal-oxide-semiconductor devices. In this paper, properties of Ga₂O₃ as gate oxide are reviewed. Recent development of various techniques being used to grow or deposit Ga₂O₃ on GaN are also discussed and compared, with the main focus on thermal oxidation technique and oxide formation mechanism.     

Vertical silicon-on-nothing FET: Threshold voltage calculation using compact capacitance model

The threshold voltage (V_th) model of the novel vertical fully-depleted silicon-on-nothing FET (VFD SONFET) structure is extracted from the compact capacitance equivalent circuit. Due to the absence of the transistor substrate in the VFD SONFET, the channel region is coupled to the source and drain through the buried oxide. Electrostatically, the VFD SONFET resembles the SOI device with thick buried oxide and recessed source/drain, and the developed model can also be applied to these structures. This property is modeled by two-dimensional buried oxide capacitance (C_BOX), which competes for the inversion charge with gate oxide capacitance (C_GOX). Therefore, the V_th is primarily influenced by the ratio of buried and gate oxide capacitances, with the negligible effect of the silicon body equivalent capacitance and the silicon body charge. The relative impact of C_BOX increases with the down-scaling of the effective channel length. In the VFD SONFET structure, the inversion channel can be formed at the back interface of the channel region, due to its coupling to the n⁺ source and drain regions. However, it is shown by the model that the V_th value is minimally changed in this case, due to a small potential change in the silicon channel. The model accurately predicts V_th in comparison to physical simulations, especially in the long channel region, whereas accuracy drops for shorter channels. The maximum absolute deviation is below 50 mV for the channel lengths above 30 nm.     

Silicon-gate CMOS devices with 300 Å gate oxides

Polycrystalline silicon gate (phosphorus doped) complementary MOS structures were fabricated with gate oxide thicknesses down to 300 Å. Measurements of the oxide fixed charge, Q_ss, and of the back-gate bias dependence of the threshold voltage indicate an absence of phosphorus diffusion through the gate oxide during conventional processing.     

Charge carrier generation/trapping mechanisms in HfO2/SiO2 stack

We have investigated electrical stress-induced charge carrier generation/trapping in a 4.2 nm thick (physical thickness T_phy) hafnium oxide (HfO₂)/silicon dioxide (SiO₂) dielectric stack in metal-oxide-semiconductor (MOS) capacitor structures with negative bias on the gate. It is found that electron trapping is suppressed in our devices having an equivalent oxide thickness (EOT) as low as 2.4 nm. Our measurement results indicate that proton-induced defect generation is the dominant mechanism of generation of bulk, border and interface traps during stress. In addition, we have shown that constant voltage stress (CVS) degrades the dielectric quality more than constant current stress (CCS).     

Improvements of ozone surface treatment on the electrical characteristics and reliability in HfO2 gate stacks

In this study, we improved the interfacial properties of high-κ gate stacks with the surface treatment of ozonated water prior to deposition of hafnium oxide (HfO₂). We demonstrated that the Ozone-oxide improved the electrical properties of the HfO₂ gate stack interface in terms of its smoother interface, lower leakage current density, narrower hysteresis width, superior charge trapping effect, and reliability. From these experimental results, we believe that treatment with ozone is an efficient method for the preparation of high-quality interfaces between HfO₂ and silicon surfaces.     

The electrical properties of anodically grown silicon dioxide films

An electrochemical technique has been used to grow anodic silicon dioxide films of thicknessess between 80 Å and 1100 Å on n-type silicon. The properties of the anodic oxide and the associated Si/SiO₂ interfaces have been studied by forming metal-oxide-semiconductor (MOS) capacitors using the anodically grown oxide as the dielectric. MOS transistors have also been fabricated on n-type silicon using anodic gate oxides 100 Å to 1000 Å thick. Their properties and possible applications are discussed.     

Experimental observations of temperature-dependent flat band voltage transients on high-k dielectrics

In this work, we show the existence of flat band voltage transients in ultrathin Gd₂O₃ dielectric films on silicon, one of the high-k dielectrics nowadays proposed to substitute silicon oxide as the dielectric gate on the future complementary metal-oxide-semiconductor circuit generations. These transients were obtained by recording the gate voltage while keeping the capacitance constant at the value measured at initial flat band condition. The dependencies of transient time constant and amplitude on dielectric thickness and temperature suggest that there are tunnelling assisted processes involved. Time constant appears to be independent on the temperature, whereas the amplitude of the transients is thermally activated with energies in the range of soft-optical phonons usually reported for high-k dielectrics. In the case of gadolinium oxide a phonon energy of 55 ± 10 meV has been obtained. Leakage current behaviour at high electric fields confirms that conduction is governed by a phonon-assisted tunnelling mechanism between localized states in the band gap of the insulator.     

Studies of the quality of GdSiO-Si interface

In this paper nMOS transistors with GdSiO gate dielectric are studied using electrical methods (C-V, I-V and charge pumping) in order to assess the quality of the dielectric-semiconductor interface. Mobility is estimated using the split C-V technique and the influence of voltage stress on interface trap generation and charge build-up in the oxide is investigated. Generation of additional interface traps is observed during negative voltage stress only, which may be attributed to hole tunneling from the semiconductor to electron traps. Multi-frequency charge pumping measurements reveal the presence of border traps.     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.