Mechanism of positive charge generation in the bulk of HfAlO/SiO2 stack

We have investigated electrical stress-induced positive charge buildup in a hafnium aluminate (HfAlO)/silicon dioxide (SiO₂) dielectric stack (equivalent oxide thickness = 2.63 nm) in metal–oxide–semiconductor (MOS) capacitor structures with negative bias on the TaN gate. Various mechanisms of positive charge generation in the dielectric have been theoretically studied. Although, anode hole injection (AHI) and valence band hole tunneling are energetically favorable in the stress voltage range studied, the measurement results can be best explained by the dispersive proton transport model.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

Bottom gate organic thin-film transistors fabricated by ultraviolet transfer embossing with improved device performance

Ultraviolet transfer embossing is optimized to fabricate bottom gate organic thin-film transistors (OTFTs) on flexible plastic substrates, achieving significant improved device performance (μ = 0.01–0.02cm²/Vs; on/off ratio = 10⁴) compared with the top gate OTFTs made previously by the same method (μ = 0.001–0.002 cm²/Vs; on/off ratio = 10²). The performance improvement can be ascribed to the reduced roughness of the dielectric-semiconductor interface (R_rms = 0.852 nm) and thermally cross-linked PVP dielectric which leads to reduced gate leakage current and transistor off current in the bottom-gated configuration. This technique brings an alternative great opportunity to the high-volume production of economic printable large-area OTFT-based flexible electronics and sensors.     

Facile synthetic route to implement a fully bendable organic metal–insulator–semiconductor device on polyimide sheet

Triblock copolymer surfactant, HO(CH₂CH₂O)₂₀(CH₂CH(CH₃)O)₇₀(CH₂CH₂O)₂₀H (i.e. P123)-based nanocrystalline (nc)-TiO₂ thin film had been synthesized on organic flexible polyimide (PI) sheet for their application in organic metal–insulator–semiconductor (MIS) device. The nc-TiO₂ film over PI was successfully deposited for the first time by a systematic solution proceeds dip-coating method and by the assistance of triblock copolymer surfactant. The effect of annealing temperature (270 °C, 5 h) on the texture, morphology and time-induced hydrophilicity was studied by X-ray diffraction (XRD), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS) and contact angle system, respectively, to examine the chemical composition of the film and the contact angle. The surface morphology of the semiconducting layer of organic pentacene was also investigated by using AFM and XRD, and confirmed that continuous crystalline film growth had occurred on the nc-TiO₂ surface over flexible PI sheet. The semiconductor–dielectric interface of pentacene and nc-TiO₂ films was characterized by current–voltage and capacitance–voltage measurements. This interface measurement in cross-link MIS structured device yielded a low leakage current density of 8.7 × 10^?12 A cm^?2 at 0 to ?5 V, maximum capacitance of 102.3 pF at 1 MHz and estimated dielectric constant value of 28.8. Furthermore, assessment of quality study of nc-TiO₂ film in real-life flexibility tests for different types of bending settings with high durability (c.a. 30 days) demonstrated a better comprehension of dielectric properties over flexible PI sheet. We expected them to have a keen interest in the scientific study, which could be an alternate opportunity to the excellent dielectric–semiconductor interface at economic and low temperature processing for large-area flexible field-effect transistors and sensors.     

Electrical characterization of MFeOS gate stacks for ferroelectric FETs

We investigated the electrical characterization of metal–ferroelectric–oxide semiconductor (MFeOS) structures for nonvolatile memory applications. Al/PZT/Si and Al/PZT/SiO₂/Si capacitors were fabricated using lead zirconate titanate (PZT; 35:65) as the ferroelectric layer. The maximum C–V memory window was 6 V for metal–ferroelectric semiconductor (MFeS) structures and 2.95 and 6.25 V for MFeOS capacitors with a buffer layer of 2.5 and 5 nm, respectively. Comparative data reveal a higher dielectric strength and lower leakage characteristic for an MFeOS structure with a 5-nm SiO₂ buffer layer compared to an MFeS structure. We also observed that the leakage characteristic was influenced by the annealing conditions.     

Effect of the work function of gate electrode on hysteresis characteristics of organic thin-film transistors with Ta2O5/polymer as gate insulator

Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta₂O₅) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode. The hysteresis characteristics were studied by the repetitive gate voltage sweep of OTFTs, and capacitance–voltage (C–V) and trap loss-voltage (G_p/ω?V) measurements of metal–insulator–semiconductor (MIS) devices. It is proved that the hysteresis characteristics of OTFTs are relative to the electron injection from gate metal to Ta₂O₅ insulator. The electron barrier height between gate metal and Ta₂O₅ is enhanced by using Au as gate electrode, and then the electron injection from gate metal to Ta₂O₅ is reduced. Finally, low hysteresis OTFTs were fabricated using Au as gate electrode.     

High dielectric constant TiO2 film grown on polysilicon by liquid phase deposition

In this study, titanium dioxide (TiO₂) films were grown on polycrystalline silicon by liquid phase deposition (LPD) with ammonium hexafluoro-titanate and boric acid as sources. The film structure is amorphous as examined by X-ray diffraction (XRD). A uniform composition of LPD-TiO₂ was observed by SIMS examination. The leakage current density of an Al/LPD-TiO₂/poly-Si/p-type Si metal–oxide–semiconductor (MOS) structure is 1.9 A/cm² at the negative electric field of 0.7 MV/cm. The dielectric constant is 29.5 after O₂ annealing at 450 °C. The leakage current densities can be improved effectively with a thermal oxidized SiO₂ added at the interface of LPD-TiO₂/poly-Si. The leakage current density can reach 3.1×10⁻⁴ A/cm² at the negative electric field of 0.7 MV/cm and the dielectric constant is 9.8.     

Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications

The outstanding electron transport properties of InGaAs and InAs semiconductor materials, makes them attractive candidates for future nano-scale CMOS. In this paper, the ON state and OFF state performance of 30 nm gate length InGaAs/InAs/InGaAs buried composite channel MOSFETs using various high-K dielectric materials is analyzed using Synopsys TCAD tool. The device features a composite channel to enhance the mobility, an InP spacer layer to minimize the defect density and a heavily doped multilayer cap. The simulation results show that MOSFETs with Al₂O₃/ZrO₂ bilayer gate oxide exhibits higher gm/I_D ratio and lower sub threshold swing than with the other dielectric materials. The measured values of threshold voltage (V_T), on resistance (R_ON) and DIBL for Lg = 30 nm In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As composite channel MOSFET having Al₂O₃/ZrO₂ (EOT = 1.2 nm) bilayer dielectric as gate oxide are 0.17 V, 290 Ω-µm, and 65 mV/V respectively. The device displays a transconductance of 2 mS/µm.     

Dielectric surface-polarity tuning and enhanced operation stability of solution-processed organic field-effect transistors

The electrical performance of triethylsilylethynyl anthradithiophene (TES-ADT) organic field-effect transistors (OFETs) was significantly affected by dielectric surface polarity controlled by grafting hexamethyldisilazane and dimethyl chlorosilane-terminated polystyrene (PS-Si(CH₃)₂Cl) to 300-nm-thick SiO₂ dielectrics. On the untreated and treated SiO₂ dielectrics, solvent–vapor annealed TES-ADT films contained millimeter-sized crystals with low grain boundaries (GBs). The operation and bias stability of OFETs containing similar crystalline structures of TES-ADT could be significantly increased with a decrease in dielectric surface polarity. Among dielectrics with similar capacitances (10.5–11 nF cm⁻²) and surface roughnesses (0.40–0.44 nm), the TES-ADT/PS-grafted dielectric interface contained the fewest trap sites and therefore the OFET produced using it had low-voltage operation and a charge-carrier mobility ∼1.32 cm² V⁻¹ s⁻¹, on–off current ratio >10⁶, threshold voltage ∼0 V, and long-term operation stability under negative bias stress.     

A low voltage SANOS nonvolatile semiconductor memory (NVSM) device

In this paper, we present a new Polysilicon–Aluminum Oxide–Nitride–Oxide–Silicon (SANOS) device structure suitable for future nonvolatile semiconductor memories. Replacing SiO₂ with a high-K material, Al₂O₃ (K_f = 9) as the top blocking layer of the conventional SONOS device increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer with its dielectric constant during write and erase operations. Therefore, this new device can achieve lower programming voltages and faster programming speed than the conventional SONOS device. We have fabricated SANOS capacitors with 2 nm tunnel oxide, 5 nm silicon nitride and 8 nm aluminum oxide and studied the programming speed and charge retention characteristics of the new devices. These new SANOS devices achieve a 2 V reduction in the programming voltages with 2.1 V initial memory window.     

Characteristics of ZnOV2O5MnO2Nb2O5Er2O3 semiconducting varistors with sintering processing

The effects of sintering temperature on the microstructure, electrical properties, and dielectric characteristics of ZnOV₂O₅MnO₂Nb₂O₅Er₂O₃ semiconducting varistors have been studied. With increase in sintering temperature the average grain size increased (4.5–9.5 μm) and the density decreased (5.56–5.45 g/cm³). The breakdown field decreased with an increase in the sintering temperature (6214–982 V/cm). The samples sintered at 900 °C exhibited remarkably high nonlinear coefficient (50). The donor concentration increased with an increase in the sintering temperature (0.60×10¹⁸–1.04×10¹⁸ cm^?3) and the barrier height exhibited the maximum value (1.15 eV) at 900 °C. As the sintering temperature increased, the apparent dielectric constant increased by more than four-fold.     

Device characteristics of AlGaN/GaN MIS–HEMTs with high-k HfxZr1−xO2 (x = 0.66, 0.47, 0.15) insulator layer

This study investigates the characteristics of AlGaN/GaN MIS–HEMTs with Hf_xZr_1−xO₂ (x = 0.66, 0.47, and 0.15) high-k films as gate dielectrics. Sputtered Hf_xZr_1−xO₂ with a dielectric constant of 20–30 and a bandgap of 5.2–5.71 eV was produced. By increasing the Zr content of HfZrO₂, the V_TH shifted from −1.8 V to −1.1 V. The highest Hf content at this study reduced the gate leakage by approximately one order of magnitude below that of those Zr-dominated HFETs. The maximum I_DS currents were 474 mA/mm, 542 mA/mm, and 330 mA/mm for Hf content of 66%, 47%, 15% at V_GS = 3 V, respectively.     

Improving the electrical and hysteresis performance of amorphous igzo thin-film transistors using co-sputtered zirconium silicon oxide gate dielectrics

The use of co-sputtered Zirconium Silicon Oxide (Zr_xSi_1−xO₂) gate dielectrics to improve the performance of α-IGZO TFT is demonstrated. Through modulating the sputtering power of the SiO₂ and ZrO₂ targets, the control of dielectric constant in a range of 6.9–31.6 is shown. Prevention of polycrystalline formation of the Zr_xSi_1−xO₂ film up to 600 °C annealing and its effectiveness in reducing leakage currents and interface trap density are presented. Moreover, it is revealed that the Zr_0.85Si_0.15O₂ dielectric could lead to significantly improved TFT performance in terms of subthreshold swing (SS=81 mV/dec), field-effect mobility (μ_FE=51.7 cm²/Vs), and threshold voltage shift (ΔV_TH=0.03 V).     

Novel GaAs enhancement-mode/depletion-mode pHEMTs technology using high-k praseodymium oxide interlayer

In this study, a novel metal–semiconductor gate enhancement-mode (E-mode) and a metal–insulator-metal–semiconductor (MIMS) gate depletion-mode (D-mode) AlGaAs/InGaAs pseudomorphic high electron mobility transistor (pHEMT) on a single GaAs substrate have been developed by using high dielectric constant praseodymium insulator layer. The epitaxial layers were design for an enhancement-mode pHEMT after gate recess process. To achieve E/D-mode pHEMTs on single GaAs wafer, traditional Pt/Ti/Au metals were deposited as Schottky contact for E-mode pHEMTs and Pr/Pr₂O₃/Ti/Au were deposited as MIMS-gate for D-mode pHEMTs. This AlGaAs/InGaAs E-mode pHEMTs exhibit a gate turn-on voltage (V_ON) of +1 V and a gate-to-drain breakdown voltage of ?5.6 V, and these values were +7 V and ?34 V for MIMS-gate D-mode pHEMTs, respectively. Therefore, this high-k insulator in D-mode pHEMT is beneficial for suppressing the gate leakage current. Comparing to previous E/D-mode pHEMT technology, this E-mode pHEMTs and MIMS-gate D-mode pHEMTs exhibit a highly potential for high uniformity GaAs logic circuit applications due to its single recess process.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

High performance inkjet-printed C60 fullerene thin-film transistors: Toward a low-cost and reproducible solution process

We have demonstrated high performance inkjet-printed n-channel thin-film transistors (TFTs) using C₆₀ fullerene as a channel material. Highly uniform amorphous C₆₀ thin-film patterns were fabricated on a solution-wettable polymer gate dielectric layer by inkjet-printing and vacuum drying process. Fabricated C₆₀ TFTs shows great reproducibility and high performance; field-effect mobilities of 2.2–2.4 cm² V^?1 s^?1, threshold voltages of 0.4–0.6 V, subthreshold slopes of 0.11–0.16 V dec^?1 and current on/off ratio of 10⁷–10⁸ in a driving voltage of 5 V. This is due to the efficient annealing process that extracting the solvent residue and the formation of low trap-density gate dielectric surface.     

Microwave dielectric properties of (1 − x)(Mg0.95Co0.05)TiO3– xCa0.6La0.8/3TiO3 ceramics with V2O5 addition

The microstructures and the microwave dielectric properties of the (1 − x)(Mg_0.95Co_0.05)TiO₃–xCa_0.6La_0.8/3TiO₃ ceramic system were investigated. In order to achieve a temperature-stable material, we studied a method of combining a positive temperature coefficient material with a negative one. Ca_0.6La_0.8/3TiO₃ has dielectric properties of dielectric constant ε_r ∼ 109, Q × f value ∼ 17,600 GHz and a large positive τ_f value ∼ 213 ppm/°C. (Mg_0.95Co_0.05)TiO₃ ceramics possesses high dielectric constant (ε_r ∼ 16.8), high quality factor (Q × f value ∼ 230,000 GHz), and negative τ_f value (−54 ppm/°C). As the x value varies from 0.1 to 0.8, (1 − x)(Mg_0.95Co_0.05)TiO₃–xCa_0.6La_0.8/3TiO₃ ceramic system has the dielectric properties as follows: 21.55 < ε_r < 75.44, 21,000 < Q × f < 90,000 and −10 < τ_f < 140. By appropriately adjusting the x value in the (1 − x)(Mg_0.95Co_0.05)TiO₃–xCa_0.6La_0.8/3TiO₃ ceramic system, zero τ_f value can be achieved. With x = 0.15, a dielectric constant ε_r ∼ 25.78, a Q × f value ∼ 84,000 GHz (at 9 GHz), and a τ_f value ∼ 2 ppm/°C were obtained for 0.85(Mg_0.95Co_0.05)TiO₃–0.15Ca_0.6La_0.8/3TiO₃ ceramics sintered at 1400 °C for 4 h. For practical application in communication systems, it is desirable to be able to sinter at lower temperatures. Therefore, V₂O₅ was as a sintering aid for lowering the sintering temperature of0.85(Mg_0.95Co_0.05)TiO₃–0.15Ca_0.6La_0.8/3TiO₃ ceramics. At the same time, the 0.85(Mg_0.95Co_0.05)TiO₃–0.15Ca_0.6La_0.8/3TiO₃ ceramic system with 0.5 wt% V₂O₅ can be obtained good properties at the microwave frequencies for 1200 °C.     

Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications

Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiO_xN_y metal oxide NPs embedded in the HfO_xN_y high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O₂/N₂ ambient. Well-isolated TiO_xN_y NPs with a diameter of 5–20 nm, a surface density of ～3 × 10¹¹ cm^?2, and a charge trap density of around 2.33 × 10¹² cm^?2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping.     

Magnetic and electric properties of BFO–NFO nanocomposites

Multiferroic nanocomposites of (1−x)BiFeO₃–xNiFe₂O₄ for x=0.2, 0.4, and 0.6 were prepared by a sol gel technique. The synthesized nanocomposites were characterized by X-ray diffraction (XRD). XRD confirmed, they being nanocomposites having desired phase with crystallite size ranging from 14.0 nm to 3.6 nm. The morphological analysis was done with the help of Transmission electron microscopy (TEM), which revealed the particle size to be in the range of 10–7 nm. Polarization–electric field (P–E) loop tracer was used to determine the ferroelectric properties of the nanocomposites. The dielectric constant at room temperature was analyzed upto 1 MHz frequency and was found to increase with increasing concentration. In order to investigate the magnetic behavior, a superconducting quantum interference device (SQUID) was used. The nanocomposites were analyzed by increasing the magnetic field up to 25 kOe and the magnetization was found to increase from 6 emu/g for x=0.2–10 emu/g for x=0.6, which was found to be optimum for the technological applications. The appropriate combination of two phases gave rise to higher magnetization.