Nanotopography produced by using a vacuum pin chuck and the flattening ability around its periphery

In next-generation lithography, the problems of nanotopography and peripheral flatness deterioration caused by the flattening of a wafer with a current vacuum pin chuck must be solved. This paper describes the factors contributing to nanotopography and flatness deterioration, and determines the flattening ability around the periphery using a current pin chuck. It is shown that the nanotopography induced by clamping is very small after polishing of the chuck surface, but may increase above 10 nm due to pin wear. Since the ring seal used to prevent the leakage is 20–40 nm higher than the pins, the peripheral flatness of the wafer deteriorates. In addition, it is found that flattening a heavily warped wafer up to the wafer edge is difficult. As such, the current ring-seal-type chuck should be replaced with a static-pressure-seal-type chuck.     

Analysis on photonic crystal fibers with circular air holes in elliptical configuration

In this paper, two novel structures of photonic crystal fibers (PCFs) containing elliptical rings of circular air holes are presented. The circular air holes in both structures are arranged in seven elliptical rings, but the number of holes in each ring is different for these structures. Moreover, air hole diameter and hole-to-hole pitch are altered along the distance from the center of the fiber’s cross section. Properties, such as birefringence and confinement loss, of these structures with different numbers of air hole rings are numerically analyzed by using the multipole method. Numerical results show that a high birefringence of 1.626 × 10⁻³ can be reached at the wavelength of 1.55 μm, and a low confinement loss on the order of 10⁻⁸ dB/m can be achieved at the same wavelength. Furthermore, it is also found that elliptic ratio obviously affects birefringence and confinement loss, but the number of air hole rings has little impact on birefringence.     

Flatness characterization of EUV mask chucks

For future extreme ultra violet (EUV) lithography at a wavelength of about 13 nm, flatness of the mask surface is an issue, since out-of-plane deviations sensitively transfer to in-plane distortions. Electrostatic clamping devices of extreme flatness and high stiffness are required. At Fraunhofer IOF, manufacturing processes for EUV mask chucks made from low thermal expansion materials are investigated. Since the chucking surface is finally structured into a pin array, flatness characterization is not trivial. The paper reports on flatness characterization of a mask chuck prototype at various stages of surface manufacturing. We present measurement results obtained with sophisticated commercial tools based on optical and tactile principles and discuss limitations encountered in both cases as well as possible strategies for improvement.     

Splitter plate application on the circular and square pin fin heat sinks

The main aim of this work is devoted to present a numerical analysis for studying effect of splitter on the hydro-thermal behavior of a pin fin heat sink. The concept of application of pins in the heat sinks arises from increasing the heat transfer area to reach maximum rate of heat losses in a limited space. On the other hand, flow separation behind the pin will enhance the pressure drop. To avoid or weaken the flow separation and reduce the pressure drop through the heat sink, a thin plate is located on the back of the pin. Two common pin fin heat sinks with circular and square pin shapes are compared together with and without splitters. Results showed that the use of splitter improves the hydro-thermal performance of both circular and square pins, so that the maximum improvement will be occurred for the case of Q = 10 W and V = 4.5 m/s. Results indicates that for circular pin fin heat sink with splitter pressure drop reduces by 13.4%, thermal resistance decreases by 36.8% and profit factor grows by 20%. Also for square pins the same results of 8.5% reduction for pressure drop, 23.8% reduction for thermal resistance and 14% increase in profit factor are observed. Also reliability analysis showed that for low-frequency and bipolar power transistor, the number of failure is reduced for circular and square splitter pin fin heat sinks.     

Carbon nanosheets derived from soluble pitch molecules and their applications in organic transistors

We report a synthesis method for carbon nanosheets (CNSs) using pitch prepared by reforming a commercially available naphtha cracking bottom oil, which is often used as a carbon fiber precursor. The pitch solution is spin-coated on a silicon wafer without using a catalyst support. After stabilization and carbonization, the CNSs as thin as 2 nm show an electrical conductivity of approximately 30,000 S/m. Although the CNSs do not have a well-developed graphitic structure, as observed using Raman spectroscopy and transmission electron microscopy, they are conductive enough for use as electrodes in an organic thin film transistor.     

Dynamic behavior in self-assembly process of cylindrical phase PS-b-PMMA block copolymer

Self-assembly through phase separation in block copolymers (BCPs) thin films represents an attractive route to create spontaneously ordered patterns at the sublithographic range. The cost effectiveness, the fast parallel processing time as well as the compatibility with the standard microelectronics technologies make it among the most promising techniques to meet the ever challenging feature size requirements in nanotechnologies. In the present work, we investigate the behavior of cylinder forming poly (styrene-b-Methyl-Methacrylate) PS-b-PMMA self-assembly on a chemically neutralized 300 mm Silicon wafer. The effects of the process parameters such as the annealing temperature and time, the film thickness, and the BCPs periodicity on the holes formation after PMMA removal were studied in systematic fashion using statistical analysis of the Critical Dimension- Scanning Electron Microscope (CD-SEM) images,focusing mainly on the Critical Diameter (CD) and circularity of holes. In particular, it was found that both (CD) in the narrow range of 10–15 nm and a hole circularity of (0.8–0.9) in excess of 96% can be achieved on the whole wafer under appropriate processing conditions. The obtained results were correlated to the self-assembly process and shed some light on the dynamic of the phase separation process of BCPs. The level of reproducibility and control achieved on a 300 mm silicon wafer, hold a promise for future applications in nanotechnology.     

Combined electron beam and UV lithography in SU-8

We present combined electron beam and UV lithography (CEUL) in SU-8 as a fast and flexible lithographic technique for prototyping of functional polymer devices and pattern transfer applications. CEUL is a lithographic technique suitable for defining both micrometer and nanometer scale features in a single polymer film on the wafer scale. The height of the micrometer and nanometer scale features is matched within 30 nm. As a pattern transfer application, we demonstrate stamp fabrication and thermal nanoimprint of a 2-dimensional array of 100 nm wide lines with a pitch of 380 nm in connection with micrometer scale features.     

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100 μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100 μm can decrease the wafer warpage by 51.4%.     

Direct bonding of Si wafer pairs with SiO2 and Si3N4 films with a fast linear annealing

2000 Å-SiO₂/Si(1 0 0) and 560 Å-Si₃N₄/Si(1 0 0) wafers, that are 10 cm in diameter, were directly bonded using a rapid thermal annealing method, so-called fast linear annealing (FLA), in which two wafers scanned with a high-power halogen lamp. It was demonstrated that at lamp power of 550 W, corresponding to the surface temperature of ∼450°C, the measured bonded area was close to 100%. At the same lamp power, the bond strength of the SiO₂∥Si₃N₄ wafer pair reached 2500 mJ/m², which was attained only above 1000°C with conventional furnace annealing for 2 h. The results clearly show that the FLA method is far superior in producing high-quality directly bonded Si wafer pairs with SiO₂ and Si₃N₄ films (Si/SiO₂∥Si₃N₄/Si) compared to the conventional method.     

Experiment and numerical analysis for edge and corner bonded PoP bottom package assemblies under four-point bending

This paper presents the four-point bend test results for edge and corner bonded 0.5 mm pitch lead-free package stackable very thin fine pitch ball grid arrays (PSvfBGAs) as package-on-package (PoP) bottom packages on a standard IPC/JEDEC bend test board. The tests were carried out based on the above standard with a 30 mm loading span, 90 mm support span and 7.5 mm/s crosshead speed. The daisy chain resistance, strain, crosshead displacement and load of each PSvfBGA were measured and a 20% increase in the resistance was used as the failure criterion. Materials used in this study were a UV-cured acrylic edge bond adhesive, a thermal-cured epoxy edge bond adhesive and a thermal-cured epoxy corner bond adhesive. The test results show that all of them can improve the bend performance significantly; especially the edge bond high module epoxy increased the crosshead displacement, strain and bending force when mechanical damage occurred by 33.46%, 26.74% and 3.05% respectively. Failure analysis indicated that the predominant failure site was PCB pad lift/cratering regardless of with or without adhesives. The 3D quarter finite element model was also built to further study the improvement mechanism of bend performance by these adhesives.     

Void-free and high-speed filling of through ceramic holes by copper electroplating

In order to achieve void-free and high-speed filling for through ceramic holes (TCHs) to prepare direct plated copper (DPC) ceramic substrates, copper electroplating technology combined with nano-carbon coating process was used in this work. The nano-carbon coating process was adopted to form a nano-carbon film as a conductive layer on the hole wall. For the TCH electroplating, an ameliorative plating additive mixture was proposed, which consists of accelerator thiazolyl dithio-propane sodium sulfonate (SH110), leveler nitrotetrazolium blue chloride (NTBC) and inhibitor polyethylene glycol (PEG, MW = 8000). Experimental results indicate that the optimized formula of the additives is 6 ppm SH110, 5 ppm NTBC, and 200 ppm PEG. By this optimized formula, the filling speed was further improved by duly increasing current densities. Consequently, TCHs with high aspect ratios (ARs) of 6.25 (500 μm depth and 80 μm diameter) were completely and void-free filled at the high current density of 1.5 ASD for 2 h, which promotes the development of vertical interconnection for DPC ceramic substrates and enhances their reliability for high power packages.     

A MEMS-based pneumatic micro-conveyor for planar micromanipulation

This paper present a two dimensional pneumatic actuator based on silicon MEMS technology for objects micro-manipulation using tilted air jets. The device is composed of three layers stacked together, two micro-machined silicon wafers and a Pyrex glass wafer. The system is composed of a set of micro-conveyors in about 9 mm × 9 mm area. Each micro-conveyor has four nozzles and can generate tilted air-jets which allow four conveyance directions. An experiment of the conveyance of a silicon chip of 3 mm diameter and weighing approximately 2 mg was performed with pulsed air flow.     

Sub-micron imaging on high-topography wafers using spray coating and projection lithography

We propose a method to image inside deep trenches (50 μm) using spray-coated resist and the ASML PAS 5500/100 system with the new functionality multi-step imaging. Multi-step imaging allows extending the focus offset range of the PAS 5500/100 system from ±30 μm to ±200 μm. Isolated trenches and contact holes were both imaged inside the deep trenches and on the surface of the wafer to study the versatility of the new functionality. A resolution of 700 nm in 3 μm thick photoresist, at the bottom of 50 μm deep, 200 μm wide trench, was obtained with this process. Finally, multi-focus exposure that consists in exposing the same image several times at various focus offsets was performed in order to image thick photoresist on high topographic substrates.     

Auxiliary components for kilopixel transition edge sensor arrays

We have fabricated transition edge sensor bolometer focal plane arrays sensitive to mm-submillimeter (0.1–3 THz) radiation for the Atacama Cosmology Telescope (ACT), which will probe the cosmic microwave background at 145, 215, and 280 GHz. Central to the performance of these bolometers is a set of auxiliary resistive components. Here we discuss shunt resistors, which allow for tight optimization of bolometer time constant and sensitivity. Our shunt resistors consist of AuPd strips grown atop interdigitated superconducting MoN_x wires. We can tailor the shunt resistance by altering the dimensions of the AuPd strips and the pitch and width of the MoN_x wires and can fabricate all of the shunts necessary for a kilopixel focal plane bolometer array on a single 4″ wafer. By modeling the resistance dependence of these parameters, a variety of different 0.75 ± 0.05 mOhm shunt resistors have been fabricated. This variety includes different shunts which have MoN_x wires with wire width equal to 1.5 and 10 μm and pitch equal to 4.5 and 26 μm, respectively. Our ability to set the resistance of the shunts hints at the scalability of our design. We have also integrated a SiO₂ capping layer into our shunt resistor fabrication scheme, which inhibits metal corrosion and eventual degradation of the shunt. Consequently, their robustness coupled with their high packing density makes these resistive components attractive for future kilopixel detector arrays.     

A study of S doped ZnSb

We report on S-doping of ZnSb for S concentrations ranging from 0.02 at% to 2.5 at%. There are no previous reports on S-doping. ZnSb is a thermoelectric material with some advantages for the temperature range 400 K–600 K. The solid solubility of S in ZnSb was estimated to be lower than 0.1% from observations of precipitates by scanning microscopy. Hall and Seebeck measurements were performed as a function of temperature from 6 K to 623 K. The temperature dependence of the electrical properties suggests that S introduces neutral scattering centers for holes in the p-type material. An increase in hole concentration by S is argued by defect reactions involving Zn vacancies.     

Fabrication of inverted pyramid structure by Cesium Chloride self-assembly lithography for silicon solar cell

Inverted pyramids were fabricated through a method combining cesium chloride (CsCl) self-assembly technology and anisotropy corrosion of silicon solar cells. Ti film with nanoporous masks was formed by lift-off the CsCl nanoislands for the inverted pyramids. The pyramids were then formed by anisotropy corrosion of alkaline solution. The average diameter and morphology of the pyramids were controlled by varying the average diameter of CsCl nanoislands from 400 nm to 1.5 µm and by varying the etching time of alkaline solution from 2 to 8 min. The inverted-pyramid texture could suppress reflection to below 10% at wavelengths from 400 to 1000 nm, which was much lower than that of planar wafer. A solar cell fabricated from the pyramids had higher short-circuit current density (J_sc) and photovoltaic conversion efficiency (PCE) compared with those of planar solar cells for the good antireflection property. The solar cell showed a PCE of 15.25%, a J_sc of 38.35 mA/cm², and an open-circuit voltage of 555.7 mV.     

Nano-dot arrays with a bit pitch and a track pitch of 25 nm formed by EB writing for 1 Tb/in2 storage

The possibility of forming very fine pits or dots with a bit pitch (BP) and a track pitch (TP) of 25 nm was investigated using a conventional electron-beam (EB) writing system and positive and negative EB resists ZEP520 and calixarene, respectively. In our experiments, we obtained very small dots with a diameter of around 13 nm, and ultrahigh-density dot arrays with a BP and a TP of 25 nm using calixarene resist. Calixarene resist is very suitable for the formation of ultrahigh-packed dot array patterns, and promises to open the way toward 1 trillion bits/in² storage. We believe that calixarene is more suitable for ultrahigh-density pattern formation than ZEP520 because of its exposure intensity distribution function and its resist structure.     

Studies on various chip-on-film (COF) packages using ultra fine pitch two-metal layer flexible printed circuits (two-metal layer FPCs)

Various fine pitch chip-on-film (COF) packages assembled by (1) anisotropic conductive film (ACF), (2) nonconductive film (NCF), and (3) AuSn metallurgical bonding methods using fine pitch flexible printed circuits (FPCs) with two-metal layers were investigated in terms of electrical characteristics, flip chip joint properties, peel adhesion strength, heat dissipation capability, and reliability. Two-metal layer FPCs and display driver IC (DDI) chips with 35 μm, 25 μm, and 20 μm pitch were prepared. All the COF packages using two-metal layer FPCs assembled by three bonding methods showed stable flip chip joint shapes, stable bump contact resistances below 5 mΩ, good adhesion strength of more than 600 gf/cm, and enhanced heat dissipation capability compared to a conventional COF package using one-metal layer FPCs. A high temperature/humidity test (85 °C/85% RH, 1000 h) and thermal cycling test (T/C test, ?40 °C to + 125 °C, 1000 cycles) were conducted to verify the reliability of the various COF packages using two-metal layer FPCs. All the COF packages showed excellent high temperature/humidity and T/C reliability, however, electrically shorted joints were observed during reliability tests only at the ACF joints with 20 μm pitch. Therefore, for less than 20 μm pitch COF packages, NCF adhesive bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for over 25 μm pitch COF applications. Furthermore, we were also able to demonstrate double-side COF using two-metal layer FPCs.     

Full wafer microlens replication by UV imprint lithography

The fabrication of microlenses is of great interest for several applications in the field of optics like wafer level cameras, homogenization of light, and coupling of light into glass fibers. Especially for low-cost optical products, microlenses have to be fabricated with a high throughput at an adequate quality. One way to fulfil these requirements is the patterning of microlenses by UV imprint lithography (UV-IL). Within this work, microlenses were replicated into the UV curing material PAK-01 by step and stamp UV-IL on silicon substrates with a diameter of 150 mm. The resulting substrates were used as masters to cast PDMS templates. These PDMS templates can be used for high throughput full wafer UV-IL. Additionally, quartz substrates with a diameter of 100 mm were patterned which could be directly used as so called “optowafers”. Master and patterned microlenses were inspected by scanning electron microscopy and with a white light profilometer. The results clearly demonstrate the excellent quality of the replication process and the capability of UV-IL to pattern microlenses on full wafer level for high throughput applications.     

New challenges for 300 mm Si technology: 3D interconnects at wafer scale by aligned wafer bonding

A new alignment technique is proposed for wafer level 3D interconnects fabrication: the SmartView^®. This original procedure is using alignment keys located in the bonding interface and enables an alignment precision of 1 μm. The method uses two top–bottom microscope pairs for observing the alignment keys and a minimal Z-axis travel during wafer alignment procedure. After the alignment procedure, the wafers are secured for subsequent wafer bonding procedures. The alignment process is presented in detail, as well as the integration of such an equipment in high production systems able to run wafers up to 300 mm diameter.