An evaluation of contamination from plasma immersion ion implantation on silicon device characteristics

Silicon devices including diodes, metal oxide semiconductor capacitors, and p-channel metal oxide semiconductor transistors were fabricated by plasma immersion ion implantation (PHI) doping technique using a microwave multipolar bucket plasma system. B₂H₆ diluted in helium (1%) was used as the gas source. The contamination by helium, hydrogen, iron, sodium, and aluminum impurities was evaluated by secondary ion mass spectrometry measurements. During PHI processing in an aluminum chamber with a stainless steel wafer holder, no aluminum and a dose of 4.1 x 10¹²/cm² of Fe were detected. Most of Fe ions were shielded by a thin layer of SiO₂ during the device fabrications. Good quality devices have been demonstrated including low reverse current of 15 nA/cm² (V_R = -5 V) in diodes and reasonable lifetimes of the minority carriers such as t_g = 55.0 μsec and = τ_r 54.2 μsec.     

等离子体浸没离子注入介质材料鞘层演化规律

等离子体浸没离子注入(Plasma-immersion-ion-implantation,简称PIII)已被广泛应用于金属、半导体以及绝缘介质材料改性等领域.通过一维流体力学模型,利用C语言实现编程,对一维平面介质靶鞘层特性进行了数值模拟,得到了鞘层的演化规律,模拟的结果可以为优化实际的工艺参数提供参考.     

Performance improvement of flash memory using AlN as charge-trapping Layer

Potential of high-k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si₃N₄) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of high-k dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high-k AlN films with SiO₂ as a blocking oxide in p-Si/SiO₂/AlN/SiO₂/poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented.     

Trench doping conformality by plasma immersion ion implantation(PIII)

Plasma immersion ion implantation (PIII) is a technique which can be used to conformally dope sidewalls of Si trenches. Using junction staining techniques and subsequently calibrating the observed stained depth to measured dose, dopant distributions inside Si trenches with aspect ratios ranging from 1 to 12 are studied for various bias voltages from 5 to 20 kV. Unlike conventional collimated beam implantation, PIII was able to conformally dope all aspect ratios studied with no evidence of abrupt discontinuities in the dopant distribution along the trench surface as a result of beam shadowing by trench geometry. Furthermore, it is shown that the higher implant biases results in more directional trajectories. Thus, dopant distributions along irregular geometries can be controlled by PDIII process conditions     

Enhanced operation and retention characteristics in charge-trapping flash memory device with a novel Si/Ge super-lattice channel

Charge-trapping flash memory devices with super-lattice channels having different stacking structures and thicknesses of Ge top-layer are investigated in this work. Both programming and erasing speeds are significantly improved for devices with super-lattice channels. Programming speed increases with increasing thickness of Ge layer in the super-lattice channel. The enhancement on programming speed can be achieved up to 40 times or better. For devices with Ge top-layer on super-lattice channel, a further enhancement is observed with increasing Ge thickness. The retention characteristic of devices with super-lattice channel is better than that with Si-channel devices owing to the slightly increased thickness of tunneling oxide.     

Plasma immersion ion implantation doping using a microwavemultipolar bucket plasma

Using plasma immersion ion implantation, silicon has been doped with boron in a high-voltage pulsed microwave multipolar bucket plasma system. Diborane gas (1%) diluted in helium is used as an ion source. A sheet resistance of 57 Ω/□ and an implanted dose of 1.9×10¹⁵/cm² are obtained in 10 min. when the target potential is pulsed to -10 kV with a 1% duty cycle. The boron profile in the silicon substrate is different from that predicted for a conventional 10-keV ion implantation. Silicon p-n junctions fabricated by this technique are of good quality     

Application of plasma immersion ion implantation doping tolow-temperature processed poly-Si TFTs

This work applied, for the first time, plasma immersion ion implantation (PIII) for source/drain doping on low-temperature processed polysilicon thin-film transistors (poly-Si TFTs). Experimental results indicate that PIII doping can provide adequate dopant concentration and junction depth for source/drain. In addition, H₂-diluted phosphorus PIII can promote dopant activation more efficiently during RTA at 600°C than with conventional ion implantation (II) technology. The excellent characteristics of PIII doped poly-Si TFTs resemble those of conventional II doped ones     

n/p ultra-shallow junction formation with plasma immersion ion implantation

n⁺/p ultra-shallow junctions formed by PH₃ plasma immersion ion implantation (PIII) have been studied and diodes with good electrical characteristics have been obtained. The influence of annealing conditions and carrier gas on junction depth and sheet resistance have been studied. It is found that a higher content of H and/or He in silicon can slow down the diffusion of phosphorus and the activation ability of implanted dopant ions in silicon; a shallower junction can been obtained with He rather than H₂ as the carrier gas; and the influence of annealing at 850°C for 20 s on sheet resistance is opposite to that of annealing at 900°C for 6 s on sheet resistance. In addition, mechanisms of unusual electrical characteristics for some diodes are discussed and analyzed in this paper.     

PMOS integrated circuit fabrication using BF3 plasma immersion ion implantation

The feasibility of plasma immersion ion implantation (PHI) for multi-implant integrated circuit fabrication is demonstrated. Patterned Si wafers were immersed in a BF₃ plasma forp-type doping steps. Boron implants of up to 3 × 10¹⁵ atoms/cm² were achieved by applying microsecond negative voltage (-2 to -30 kV) pulses to the wafers at a frequency of 100 Hz to 1 kHz. After implantation the wafers were annealed using rapid thermal annealing (RTA) at 1060° C for 20 sec to activate the dopants and to recrystallize the implant damaged Si. For the PMOS process sequence both the Si source-drain and polycrystalline Si (poly-Si) gate doping steps were performed using PIII. The functionality of several types of devices, including diodes, capacitors, and transistors, were electrically measured to evaluate the compatibility of PIII with MOS process integration.     

Effects of aluminum incorporation on hafnium oxide film using plasma immersion ion implantation

The effects of aluminum implantation on HfO₂ thin films using plasma immersion ion implantation (Al–PIII samples) are investigated. X-ray photoelectron spectroscopy measurements reveal that most of the implanted aluminum atoms accumulated near the surface region of the oxide film. The greatly reduced leakage current, smaller flatband shift and steep transition from the accumulation to the depletion region in the capacitance–voltage characteristics for Al–PIII samples indicate that both bulk oxide and interface traps are significantly reduced by aluminum incorporation. Even though the aluminum concentration at the Si/HfO₂ interface is very low the results indicate that trace amount of aluminum at the interface leads to significant improvements in both material and electrical characteristics of the thin HfO₂ films.     

Photovoltaic effect in a structure based on amorphous and nanoporous silicon formed by plasma immersion ion implantation

A p-i-n structure with photovoltaic properties was proposed and fabricated by plasma immersion ion implantation. Implantation of helium ions with an energy of 1 to 5 keV with subsequent annealing creates a region of nanoporous silicon at a depth of ～20 to 80 nm from the silicon substrate surface. A nanocrystalline structure of this layer results in high light absorption and a change in the band-gap energy, which leads to the formation of a heterojunction. The upper layer of the modified region was additionally doped with boron to create a p region. The resulting structure showed a photovoltaic effect (0.15 V, 6.4 mA/cm²) under illumination with light equivalent to sunlight in terms of the spectral range and intensity.     

Effects of nitrogen incorporation by plasma immersion ion implantation on electrical characteristics of high-k gated MOS devices

Nitridation treatments are generally used to enhance the thermal stability and reliability of high-k dielectric. It is observed in this work that, the electrical characteristics of high-k gated MOS devices can be significantly improved by a nitridation treatment using plasma immersion ion implantation (PIII). Equivalent oxide thickness, (EOT) and interface trap density of MOS devices are reduced by a proper PIII treatment. At an identical EOT, the leakage current of devices with PIII nitridation can be reduced by about three orders of magnitude. The optimal process conditions for PIII treatment include nitrogen incorporation through metal gate, ion energy of 2.5 keV, and implantation time of 15 min.     

Performance and reliability improvement of flash device by a novel programming method

The operating methods of flash memory device are worth studying due to the reliability issue. A novel programming method based on a new current mechanism is developed in this work to improve the performance and reliability of flash memory. Experimental results show that this novel programming method with higher gate current injection efficiency not only increases the operating speed but also improves the reliability. This reliability improvement can be attributed to the reduction of oxide-trap-charge generation and threshold-voltage shift.     

Improved electrical characteristics of high-k gated MOS devices by nitrogen incorporation with plasma immersion ion implantation (PIII)

High-k gate dielectric process is the key technology for nano-scale MOS device. A nitridation treatment on silicon surface is promising for characteristic improvement on high-k dielectric. It is found in this work that the electrical characteristics of high-k gated MOS devices can be improved by a nitridation treatment at silicon surface using plasma immersion ion implantation (PIII) at low ion energy and with a short implantation time. A shallow nitrogen profile at Si surface is known to be favorable for further enhancement of device properties.     

Thermal stability of tantalum nitride diffusion barriers for Cu metallization formed using plasma immersion ion implantation

Plasma immersion ion implantation (PIII) technique was employed to form Tantalum nitride diffusion barrier films for copper metallization on silicon. Tantalum coated silicon wafers were implanted with nitrogen at two different doses. A copper layer was deposited on the samples to produce Cu/Ta(N)/Si structure. Samples were heated at various temperatures in nitrogen ambient. Effect of nitrogen dose on the properties of the barrier metal was investigated by sheet resistance, X-ray diffraction and scanning electron microscopy measurements. High dose nitrogen implanted tantalum layer was found to inhibit the diffusion of copper up to 700 °C.     

N type doping of inp by ion implantation

Results are reported on the electrical properties of semi-insulating InP implanted with⁷⁸Se and³²S at different energies and doses. The implants were into both room temperature and heated substrates and annealed over the temperature range from 400°C to 760°C. Pronounced differ-ences have been found in the annealing temperature depend-ence between hot and room temperature implants. In most cases hot implants can be activated at much lower temp-eratures than previous reported results would indicate, making ion implantation, in principle, compatible with a wider range of device processing techniques. The role of dielectric coatings as both implantation barriers and annealing encapsulants has also been investigated.     

Ultra-shallow np junction formed by PH3 and AsH3 plasma immersion ion implantation

Ultra-shallow 28–88 nm n⁺p junctions formed by PH₃ and AsH₃ plasma immersion ion implantation (PIII) have been studied. The reverse leakage current density and intrinsic bulk leakage current density of the diodes are found to be as low as 4.2 nA cm⁻² and 2.4 nA cm⁻², respectively. The influences of pre-annealing condition and the carrier gas on the junction depth and the sheet resistance are also studied. It is found that the increase of H or He content in the PH₃ PIII can slow down the phosphorus diffusion and shallower junction can been obtained. Annealing conditions have pronounced effect on the sheet resistance. It was found that sample annealed at 850 °C for 20 s has reverse results to that annealed at 900 °C for 6 s. For AsH₃ PIII samples, it is observed that two-step annealing is more effective to activate the dopant and a lower reverse current density resulted.     

Performance improvement of SONOS memory by bandgap engineering of charge-trapping layer

A significant improvement in device performance and reliability characteristics of silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory has been achieved. Superior endurance characteristic shows no sign of degradation even after 10/sup 6/ program/erase cycles and an extrapolated ten-year detection window of 1.4 V has been attained from retention measurement. The dramatic improvement results from a bandgap engineering of the SiN charge-trapping layer. With a gradual variation of the Si/N ratio from bottom to top of nitride film rather than uniform standard composition, a large number of highly accessible trapping levels are created in addition to the deepened barrier height between nitride and tunnel oxide that reduces back-tunneling probability. The proposed technique shall be valuable in pushing Flash memory technology into the next generation.     

Characteristics of sub-100-nm p+/n junctions fabricatedby plasma immersion ion implantation

Plasma immersion ion implantation (PIII) is an efficient method for fabricating high-quality p⁺/n diodes with junction depths below 100 nm. SiF₄ is implanted to create an amorphous Si layer to retard B channeling and diffusion, and then BF₃ is implanted. Ultrashallow p⁺/n junctions are formed by annealing at 1060 °C for 10 s. With the shallow implants, no extended defects are observed in device or peripheral areas due to rapid outdiffusion of fluorine. Diode electrical characteristics yield forward ideality factor of 1.05-1.06 and leakage current density below 2 nA/cm ² in the diode bulk. Minority-carrier lifetime below the junction is greater than 250 μs