共查询到20条相似文献,搜索用时 31 毫秒
1.
《Microelectronics Reliability》2014,54(9-10):1883-1886
Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (VGS) and high drain voltage (VDS), reduction of the ON-resistance (RON) is observed. At stress times at which RON almost reaches its constant level, an increase of the drain leakage in OFF state (VDS = −60 V, VGS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS. 相似文献
2.
Ultraviolet transfer embossing is optimized to fabricate bottom gate organic thin-film transistors (OTFTs) on flexible plastic substrates, achieving significant improved device performance (μ = 0.01–0.02cm2/Vs; on/off ratio = 104) compared with the top gate OTFTs made previously by the same method (μ = 0.001–0.002 cm2/Vs; on/off ratio = 102). The performance improvement can be ascribed to the reduced roughness of the dielectric-semiconductor interface (Rrms = 0.852 nm) and thermally cross-linked PVP dielectric which leads to reduced gate leakage current and transistor off current in the bottom-gated configuration. This technique brings an alternative great opportunity to the high-volume production of economic printable large-area OTFT-based flexible electronics and sensors. 相似文献
3.
We make a two-dimensional transient analysis of field-plate AlGaN/GaN high electron mobility transistors (HEMTs) with a Fe-doped semi-insulating buffer layer, which is modeled that as deep levels, only a deep acceptor located above the midgap is included (EC − EDA = 0.5 eV, EC: energy level at the bottom of conduction band, EDA: deep acceptor's energy level). And the results are compared with a case having an undoped semi-insulating buffer layer in which a deep donor above the midgap (EC − EDD = 0.5 eV. EDD: the deep donor's energy level) is considered to compensate a deep acceptor below the midgap (EDA − EV = 0.6 eV, EV: energy level at the top of valence band). It is shown that the drain-current responses when the drain voltage is lowered abruptly are reproduced quite similarly between the two cases with different types of buffer layers, although the time region where the slow current transients occur is a little different. The lags and current collapse are reduced by introducing a field plate. This reduction in lags and current collapse occurs because the deep acceptor's electron trapping is reduced under the gate region in the buffer layer. The dependence of drain lag, gate lag and current collapse on the field-plate length and the SiN layer thickness is also studied, indicating that the rates of drain lag, gate lag and current collapse are quantitatively quite similar between the two cases with different types of buffer layers when the deep-acceptor densities are the same. 相似文献
4.
《Microelectronics Reliability》2014,54(6-7):1282-1287
This study investigates the characteristics of AlGaN/GaN MIS–HEMTs with HfxZr1−xO2 (x = 0.66, 0.47, and 0.15) high-k films as gate dielectrics. Sputtered HfxZr1−xO2 with a dielectric constant of 20–30 and a bandgap of 5.2–5.71 eV was produced. By increasing the Zr content of HfZrO2, the VTH shifted from −1.8 V to −1.1 V. The highest Hf content at this study reduced the gate leakage by approximately one order of magnitude below that of those Zr-dominated HFETs. The maximum IDS currents were 474 mA/mm, 542 mA/mm, and 330 mA/mm for Hf content of 66%, 47%, 15% at VGS = 3 V, respectively. 相似文献
5.
Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to LG = 0.5 μm, LG = 0.25 μm and LG = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (ID-VGS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of ET = EV + 0.9 eV (carbon) with concentrations of NIT = 5 × 1016cm− 3, NIT = 5 × 1017cm− 3 and NIT = 5 × 1018cm− 3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm. 相似文献
6.
《Microelectronics Journal》2007,38(6-7):783-786
For low power applications, the increase of gate leakage current, caused by direct tunneling in ultra-thin oxide films, is the crucial factor eliminating conventional SiO2-based gate dielectrics in sub-90 nm CMOS technology development. Recently, promising performance has been demonstrated for poly-Si/high-k and poly-Si/SiON gate stacks in addressing gate leakage requirements for low power applications. However, the use of poly-Si gate electrodes on high-k created additional issues such as channel mobility and reliability degradations, as well as Fermi level pinning of the effective gate work function. Therefore, oxynitride gate dielectrics are being proposed as an intermediate solution toward the sub-65/45 nm nodes. Apparently, an enhanced SiON gate dielectric stack was developed and reported to achieve high dielectric constant and good interfacial properties. The purpose of this paper is to provide a comprehensive review some of the device performance and limitation that high-k and oxynitride as dielectric materials are facing for sub-65/45 nm node. 相似文献
7.
《Microelectronics Reliability》2014,54(11):2383-2387
This paper investigates voltage-dependent degradation of HfSiON/SiO2 nMOSFETs under conditions of positive bias temperature instability (PBTI), and proposes a PBTI degradation model that can use data from acceleration tests to predict device lifetime accurately. Experimental results show that the PBTI stress generated shallow traps in HfSiON and the exponent of power-law for threshold-voltage shift increased exponentially with an increase of PBTI stress voltage. An enhancement factor that represents creation of shallow charge traps in gate dielectric by PBTI stress was included in the proposed model. The proposed model predicted operational lifetime tL = 1.64 × 1010 s, which agreed well with the tL = 1.92 × 1010 s measured at low gate stress voltage, whereas the conventional model overestimates tL by an order of magnitude, demonstrating that the proposed model is very useful on shortening the measurement time for estimating tL of high-k nMOSFETs. 相似文献
8.
C. Le Royer L. Clavelier C. Tabone K. Romanjek C. Deguet L. Sanchez J.-M. Hartmann M.-C. Roure H. Grampeix S. Soliveres G. Le Carval R. Truche A. Pouydebasque M. Vinet S. Deleonibus 《Solid-state electronics》2008,52(9):1285-1290
We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart CutTM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO2/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (ION, IOFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μh ~ 250 cm2/V/s, ION = 436 μA/μm for LG = 105 nm), and OFF current densities comparable or better than those reported in the literature. 相似文献
9.
Emilie Bernard T. Ernst B. Guillaumot N. Vulliet X. Garros V. Maffini-Alvaro P. Coronel T. Skotnicki S. Deleonibus 《Solid-state electronics》2008,52(9):1297-1302
In this study, we integrate and compare the electrical performances of metal/high-K embedded gates in 3D multi-channel CMOSFETs (MCFETs) on SOI. The electrical characteristics of embedded gates obtained by filling cavities with TiN/HfO2, TiN/SiO2 or N+ poly-Si/SiO2 are compared to a planar reference. In particular, we investigate electron and hole mobility behaviours (300 K down to 20 K) in embedded and planar structures, the gate leakage current and the negative bias temperature instability (NBTI). Despite a lower mobility, TiN/HfO2 gate stack demonstrates the best ION/IOFF compromise and exhibits NBTI life time higher than 10 years up to 1.3 V. 相似文献
10.
Chunhong Li Feng Pan Xiujin Wang Lijuan Wang He Wang Haibo Wang Donghang Yan 《Organic Electronics》2009,10(5):948-953
Organic thin-film transistors (OTFTs) using high dielectric constant material tantalum pentoxide (Ta2O5) and benzocyclobutenone (BCBO) derivatives as double-layer insulator were fabricated. Three metals with different work function, including Al (4.3 eV), Cr (4.5 eV) and Au (5.1 eV), were employed as gate electrodes to study the correlation between work function of gate metals and hysteresis characteristics of OTFTs. The devices with low work function metal Al or Cr as gate electrode exhibited high hysteresis (about 2.5 V threshold voltage shift). However, low hysteresis (about 0.7 V threshold voltage shift) OTFTs were attained based on high work function metal Au as gate electrode. The hysteresis characteristics were studied by the repetitive gate voltage sweep of OTFTs, and capacitance–voltage (C–V) and trap loss-voltage (Gp/ω?V) measurements of metal–insulator–semiconductor (MIS) devices. It is proved that the hysteresis characteristics of OTFTs are relative to the electron injection from gate metal to Ta2O5 insulator. The electron barrier height between gate metal and Ta2O5 is enhanced by using Au as gate electrode, and then the electron injection from gate metal to Ta2O5 is reduced. Finally, low hysteresis OTFTs were fabricated using Au as gate electrode. 相似文献
11.
C.P. Chen T.D. Lin Y.J. Lee Y.C. Chang M. Hong J. Kwo 《Solid-state electronics》2008,52(10):1615-1618
A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In0.2Ga0.8As on GaAs using TiN as gate metal and Ga2O3(Gd2O3) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at Vg = 4 V and Vd = 2 V, a low gate leakage of <10?7 A/cm2 at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at Vg = 3 V, Vd = 2 V, and an on/off ratio of ~105 in drain current. For comparison, a TiN/Ga2O3(Gd2O3)/In0.2Ga0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10?8–10?9 A/cm2, well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ~16 and a low interfacial density of state of ~(2~6) × 1011 cm?2 eV?1, and an atomically sharp smooth Ga2O3(Gd2O3)/In0.2Ga0.8As interface. 相似文献
12.
《Microelectronics Journal》2014,45(2):144-151
Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO2) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (gm), output conductance (gd), transconductance generation factor (gm/ID), early voltage (VEA), intrinsic gain (AV), cut off frequency (fT), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V−1, 39.589 V−1) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×105 GHz/V, 1.72×105 GHz/V) for two different values of VDS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5. 相似文献
13.
This paper proposes a fast and accurate method to measure the constants a and n of the power law ∆ Vth = atn for HfSiON/SiO2 dielectric nMOSFETs under positive bias temperature instability (PBTI), where ∆ Vth is a shift of threshold voltage, and t is stress duration. The proposed method requires one nMOSFET only, uses a voltage ramp stress (VRS), measures ∆ Vth vs. t data during VRS, uses a regression method to fit the data for each VRS pulse to the power law to obtain a and n at each stress voltage Vg,str, then obtains five voltage-independent constants for the power law after fitting the curves of a and n vs. Vg,str to empirical models. The five voltage-independent constants agreed very well with those obtained using the constant voltage stress (CVS) method. After obtaining the voltage-independent constants, the lifetime tL at an operating voltage Vop was estimated using the power law. The estimated tL = 1.67 × 108 s was quite close to tL = 1.74 × 108 s estimated using CVS, and to tL = 1.72 × 108 s estimated by extrapolating the ΔVth vs. t curve measured at Vg,str = Vop = 1.2 V to ΔVth = 200 mV. The time required for measurement was 900 s, compared to 30,000 s for the CVS method. These experimental results show that the proposed VRS-regression method is very useful for screening nMOSFETs under PBTI. 相似文献
14.
《Microelectronics Reliability》2014,54(6-7):1133-1136
It was found that the electrical properties of CeO2/La2O3 stack are much better than a single layer La2O3 film. A thin CeO2 capping layer can effectively suppress the oxygen vacancy formation in the La2O3 film. This work further investigates the current conduction mechanisms of the CeO2 (1 nm thick)/La2O3 (4 nm thick) stack. Results show that this thin stacked dielectric film still has a large leakage current density; the typical 1−V leakage can exceed 1 mA/cm2 at room temperature. The large leakage current should be due to both the oxide defect centers as well as the film structure. Results show that at low electric field (<0.2 MV/cm), the thermionic emission induced current conduction in this stacked structure is quite pronounced as a result of interface barrier lowering due to the capping CeO2 film which has a higher k value than that of the La2O3 film. At higher electric fields, the current conduction is governed by Poole–Frenkel (PF) emission via defect centers with an effective energy level of 0.119 eV. The temperature dependent current–voltage characteristics further indicate that the dielectric defects may be regenerated as a result of the change of the thermal equilibrium of the redox reaction in CeO2 film at high temperature and the drift of oxygen under the applied electric field. 相似文献
15.
M. Bouya N. Malbert N. Labat D. Carisetti P. Perdu J.C. Clément B. Lambert M. Bonnet 《Microelectronics Reliability》2008,48(8-9):1366-1369
The study is carried out on AlGaN/GaN HEMTs presenting current collapse effect at Vds lower than 6 V. This effect is completely recovered by illuminating the component with light of 710 nm wavelength (1.75 eV). The spectral analysis of the light emission in the visible near infrared spectrum shows a bell-shape with superimposed distinct emission peaks. These features suggest that the electroluminescence (EL) signal is due to the direct intraband of electrons and inelastic intraband transition of electrons due to scattering by charged centres. Photoionisation experiments have been conducted to determine the light wavelengths/energies that separately change the drain current and the gate leakage current. 相似文献
16.
《Solid-state electronics》2006,50(7-8):1413-1419
The effects of AlxGa1−xN aluminum fraction x and SiC surface pre-treatment on AlGaN/4H–SiC heterojunction interfaces are experimentally investigated. From capacitance vs. voltage measurements, the conduction band offsets are found to be ΔEC ≈ 0.30 for x ≈ 0.3 and ΔEC ≈ 0.56 for x ≈ 0.5. Forward bias ideality factors are reasonable at 3.3 for Al0.3Ga0.7N diodes, but >9 for Al0.5Ga0.5N diodes, suggesting a higher level of interface charge related to the higher aluminum fraction. Reverse bias leakage is acceptably low, with breakdown occurring at VA > 200 V reverse bias for all tested devices. The effect of 1500 °C hydrogen etching of the SiC substrate prior to AlxGa1−xN growth is also investigated, and found to have little effect for x = 0.3 but a beneficial effect for x = 0.5. 相似文献
17.
J.M.J. Lopes E. Durğun Özben M. Roeckerath U. Littmark R. Lupták St. Lenk M. Luysberg A. Besmehn U. Breuer J. Schubert S. Mantl 《Microelectronic Engineering》2009,86(7-9):1646-1649
In this contribution we present results on the structural and electrical properties of amorphous REScO3 (RE = La, Gd, Tb, Sm) and LaLuO3 thin films. The study reveals that these oxides are potential candidates for so-called higher-k dielectrics for forthcoming MOSFET generations. High dielectric constants up to 32, low leakage currents and low interface trap densities are determined for amorphous thin films prepared by pulsed-laser deposition, molecular beam deposition and e-gun evaporation. Moreover, we show that LaLuO3 gate stacks annealed up to 1050 °C maintain low leakage current densities without substantial EOT increase. Finally, promising results for n-MOSFETs with GdScO3 as gate dielectric processed on strained silicon-on-insulator substrates are also shown. 相似文献
18.
Piyas Samanta Chin-Lung Cheng Yao-Jen Lee Mansun Chan 《Microelectronic Engineering》2009,86(7-9):1767-1770
We have investigated electrical stress-induced positive charge buildup in a hafnium aluminate (HfAlO)/silicon dioxide (SiO2) dielectric stack (equivalent oxide thickness = 2.63 nm) in metal–oxide–semiconductor (MOS) capacitor structures with negative bias on the TaN gate. Various mechanisms of positive charge generation in the dielectric have been theoretically studied. Although, anode hole injection (AHI) and valence band hole tunneling are energetically favorable in the stress voltage range studied, the measurement results can be best explained by the dispersive proton transport model. 相似文献
19.
Hsien-Chin Chiu Shao-Wei Lin Chia-Shih Cheng Chien-Cheng Wei 《Solid-state electronics》2008,52(5):725-729
Si-based field-plate 0.13 μm gate length metal-oxide-semiconductor field effect transistor (Si MOSFET) with field-plate (FP) lengths of 0.1 μm, 0.2 μm, and 0.3 μm have been fabricated and investigated. The field-plate metals were connected to gate electrode in this study to improve device gate resistance (Rg) resulting in the better microwave performance. By increasing the length of field-plate metal extension (LFPE), the off-state drain-to-source surface leakage current can be suppressed. Besides, low surface traps in FP NMOS also leads to a higher drain-to-source current (Ids) especially at high current regime compared to standard device. The power added efficiency (PAE) was 56.3% for LFPE of 0.3 μm device, and these values where 54.7% and 53.8% for LFPE of 0.2 μm and 0.1 μm devices, respectively. Wider field-plate metal extension exhibits highly potential for low noise amplifier and high efficiency power amplifier applications. 相似文献
20.
We demonstrate high-performance flexible polymer OFETs with P-29-DPP-SVS in various geometries. The mobilities of TG/BC OFETs are approximately 3.48 ± 0.93 cm2/V s on a glass substrate and 2.98 ± 0.19 cm2/V s on a PEN substrate. The flexible P-29-DPP-SVS OFETs exhibit excellent ambient and mechanical stabilities under a continuous bending stress of 1200 times at an R = 8.3 mm. In particular, the variation of μFET, VTh and leakage current was very negligible (below 10%) after continuous bending stress. The BG/TC P-29-DPP-SVS OFETs on a PEN substrate applies to flexible NH3 gas sensors. As the concentration of NH3 increased, the channel resistance of P-29-DPP-SVS OFETs increased approximately 100 times from ∼107 to ∼109 Ω at VSD = −5 V and VGS = −5 V. 相似文献