Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications

The outstanding electron transport properties of InGaAs and InAs semiconductor materials, makes them attractive candidates for future nano-scale CMOS. In this paper, the ON state and OFF state performance of 30 nm gate length InGaAs/InAs/InGaAs buried composite channel MOSFETs using various high-K dielectric materials is analyzed using Synopsys TCAD tool. The device features a composite channel to enhance the mobility, an InP spacer layer to minimize the defect density and a heavily doped multilayer cap. The simulation results show that MOSFETs with Al₂O₃/ZrO₂ bilayer gate oxide exhibits higher gm/I_D ratio and lower sub threshold swing than with the other dielectric materials. The measured values of threshold voltage (V_T), on resistance (R_ON) and DIBL for Lg = 30 nm In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As composite channel MOSFET having Al₂O₃/ZrO₂ (EOT = 1.2 nm) bilayer dielectric as gate oxide are 0.17 V, 290 Ω-µm, and 65 mV/V respectively. The device displays a transconductance of 2 mS/µm.     

Monte Carlo simulations of InGaAs nano-MOSFETs

The potential performance of sub-50 nm n-type implant free III-V MOSFETs with an In_0.75Ga_0.25As channel is studied using Monte Carlo (MC) device simulations. The simulated I_D-V_G characteristics of the In_0.75Ga_0.25As implant free MOSFETs are compared with equivalent In_0.3Ga_0.7As implant free MOSFETs and with a state-of-the-art silicon CMOS transistors. The study is based on careful calibration of the MC simulator against experimental data obtained from a δ-doped In_0.52Ga_0.48As/ In_0.53Ga_0.47As/In_0.75Ga_0.25As heterostructure with a high-κ gate dielectric. At 0.8 V supply voltage, the 30 nm gate length In_0.75Ga_0.25As implant free III-V MOSFET delivers a drive current of 1730 μA/μm as compared to the 1550 μA/μm obtained in the equivalent In_0.3Ga_0.7As implant free MOSFET. When this high indium channel transistor is scaled to 20 and 15 nm gate lengths the drive current at 0.8 V supply voltage increases to 2465 and 2745 μA/μm, respectively, making it a good candidate for high performance, low power digital applications at the 22 nm technology generation and beyond.     

Hall and photoluminescence studies of effects of the thickness of an additional In0.3Ga0.7As layer in the center of In0.15Ga0.85As/Al0.25Ga0.75As/GaAs high electron mobility transistors

In order to reduce the noise and carrier–donor scattering and thereby increase the carrier mobility of the pseudomorphic AlGaAs/InGaAs high electron mobility transistors (pHEMTs), we have grown Al_0.25Ga_0.75As/In_0.15Ga_0.85As/In_0.3Ga_0.7As/GaAs pHEMTs with varied In_0.3Ga_0.7As thickness, and studied the effects of the In_0.3Ga_0.7As thickness on the electron mobility and sheet density by Hall measurements and photoluminescence measurements. We calculated the electron and hole subbands and obtained good agreement between calculated and measured PL energies. It was found that the additional In_0.3Ga_0.7As layer could be used to reduce the carrier–donor scattering, but due to the increased interface roughness as the In_0.3Ga_0.7As layer becomes thicker, the interface scattering reduced the electron mobility. An optimal thickness of the In_0.3Ga_0.7As was found to be 2 nm.     

Interface studies of ALD-grown metal oxide insulators on Ge and III–V semiconductors (Invited Paper)

Atomic layer deposited (ALD) HfO₂/GeO_xN_y/Ge(1 0 0) and Al₂O₃/In_0.53Ga_0.47As(1 0 0) ? 4 × 2 gate stacks were analyzed both by MOS capacitor electrical characterization and by advanced physical characterization to correlate the presence of electrically-active defects with chemical bonding across the insulator/channel interface. By controlled in situ plasma nitridation of Ge and post-ALD annealing, the capacitance-derived equivalent oxide thickness was reduced to 1.3 nm for 5 nm HfO₂ layers, and mid-gap density of interface states, D_it = 3 × 10¹¹ cm^?2 eV^?1, was obtained. In contrast to the Ge case, where an engineered interface layer greatly improves electrical characteristics, we show that ALD-Al₂O₃ deposited on the In_0.53Ga_0.47As (1 0 0) ? 4 × 2 surface after in situ thermal desorption in the ALD chamber of a protective As cap results in an atomically-abrupt and unpinned interface. By avoiding subcutaneous oxidation of the InGaAs channel during Al₂O₃ deposition, a relatively passive gate oxide/III–V interface is formed.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

Compound semiconductor MOSFETs

Enhancement mode, high electron mobility MOSFET devices have been fabricated using an oxide high-κ gate dielectric stack developed using molecular beam epitaxy. A template layer of Ga₂O₃, initially deposited on the surface of the III-V device unpins the GaAs Fermi level while a (Gd_xGa_1−x)₂O₃ bulk ternary layer forms the highly resistive layer to reduce leakage current through the dielectric stack. A midgap interface state density of ∼2 × 10¹¹ cm⁻² eV⁻¹ and a dielectric constant of 20 are determined using electrical measurements.. N-channel MOSFETs with a gate length of 1 μm and a source-drain spacing of 3 μm show a threshold voltage, saturation current and transconductance of 0.11 V, 380 mA/mm and 250 mS/mm, respectively.     

Germanium surface and interfaces (Invited Paper)

Germanium surface and interfaces are modeled based on the requirement that surface charge neutrality is satisfied. It is found that Ge interfaces have remarkable electronic properties stemming from the fact that the energy gap is low and the CNL is located very low in the gap close to the valence band. Because of this, acceptor defects (probably dangling bonds) are easily filled building a negative charge at the interface which easily inverts the surface of n-type Ge at no gate bias and for low doping N_D and moderate to high interface state density D_it. This has important consequence in the electrical characteristics of Ge transistors. In p-channel FETs, an undesired positive threshold voltage V_T of +0.2 to +0.5 V is predicted depending on N_D, D_it and the equivalent oxide thickness. In n-channel FETs, inversion is inhibited and V_T could become higher than 1 V if the D_it is well in excess of 10¹³ eV^?1 cm^?2.     

Comparative assessment of InGaAs sub-channel and InAs composite channel double gate (DG)-HEMT for sub-millimeter wave applications

This work analyses the impact of channel material, channel thickness (T_CH) and gate length (L_g) on the various performance device metrics of Double-gate (DG) High Electron Mobility Transistor (HEMT) by using 2D Sentaurus TCAD simulation. A comparison between In_0.53Ga_0.47As/In_0.7Ga_0.3As/In_0.53Ga_0.47As sub-channel and In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As composite channel DG-HEMT along with SG-HEMT is made by characterizing the device with structural and geometrical parameters suitable for applications requiring high frequency operations. The DG-In_0.53Ga_0.7As/In_0.7Ga_0.3As/In_0.53Ga_0.7As sub-channel/DG-In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As composite channel HEMT with channel thickness of 13 nm and barrier thickness (T_B) of 2 nm with L_g = 30 nm are seen offering a positive threshold voltage (V_T) of 0.298/0.21 V, transconductance (g_m) of 3.09/3.3 mS/µm, with cut-off frequency (f_T) and maximum oscillation frequency (f_max) of 776/788 GHz and 905/978 GHz, respectively at V_ds = 0.5 V is obtained. If the channel thickness of the DG-InAs composite channel device is scaled and reduced to 10 nm, the RF performances are further enhanced to 809 GHz (f_T) and 1030 GHz (f_max). Compared to DG-InGaAs sub-channel device, the device with thin DG-InAs composite channel device shows a better performance in terms of drain current (I_ds), analog/RF performance thereby making it preferable for future THz applications.     

In0.75Ga0.25As channel layers with record mobility exceeding 12,000 cm2/Vs for use in high-κ dielectric NMOSFETs

In_0.75Ga_0.25As channel layers with a record mobility exceeding 12,000 cm²/Vs for use in high-κ dielectric NMOSFETs have been fabricated. The device structures which have been grown by molecular beam epitaxy on 3″ semi-insulating InP substrate comprise a 10 nm strained In_0.75Ga_0.25As channel layer and a high-κ oxide based dielectric layer (κ ≅ 20). Electron mobilities of 12,033 and 7,042 cm²/Vs have been measured for sheet carrier concentrations n_s of 2.5 × 10¹² and 6 × 10¹² cm⁻², respectively.     

Investigation of scalability of In0.7Ga0.3As quantum well field effect transistor (QWFET) architecture for logic applications

In this paper, the scalability of In_0.7Ga_0.3As QWFET is investigated using two-dimensional numerical drift-diffusion simulation. Numerical drift-diffusion simulations were calibrated using experimental results on short-channel In_0.7Ga_0.3As QWFETs [7] to include the effects of velocity overshoot. Logic figures of merit (sub-threshold slope, saturated threshold voltage, drain induced barrier lowering, I_ON/I_OFF ratio over a specified gate swing, effective injection velocity and intrinsic switching delay) extracted from the numerical simulations are in excellent agreement with the experimental data. Three alternate QWFET device architectures are proposed and thoroughly investigated for 15 nm node and beyond logic applications. Amongst them, double-gate In_0.7Ga_0.3As QWFET shows the best scalability in terms of logic figures of merit, thus making it an ideal candidate for the design and demonstration of the ultimate scaled transistor.     

Band offsets at interfaces of (1 0 0)InxGa1−xAs (0 ⩽ x ⩽ 0.53) with Al2O3 and HfO2

The electron energy band alignment at interfaces of In_xGa_1?xAs (0 ? x ? 0.53) with atomic-layer deposited insulators Al₂O₃ and HfO₂ is characterized using combined measurements of internal photoemission of electrons and photoconductivity. The measured energy of the In_xGa_1?xAs valence band top is found to be only marginally influenced by the semiconductor composition. This result suggests that the observed bandgap narrowing from 1.42 to 0.75 eV when the In content increases from 0 to 0.53 occurs mostly through downshift of the semiconductor conduction band bottom. Electron states originating from the interfacial oxidation of In_xGa_1?xAs lead to reduction of the electron barrier at the semiconductor/oxide interface.     

Analysis of the electrical characteristics of power LDMOSFETs having different design parameters under various temperature

In this paper, we have investigated the electrical characteristics of power lateral double-diffused MOSFETs (LDMOSFETs) having different gate lengths (2.1–3 μm) and drift lengths (6.6–12.6 μm) in the temperature range 100–500 K. The results of this study indicate that gate length and drift region length have a great effect on electrical characteristics, but they have little effect on temperature dependence. The specific on-resistance and the off-state breakdown voltage increase with temperature. The result shows that the specific on-resistance increases exponentially with the exponent 2.2 and, by contrast, the off-state breakdown voltage increases linearly with a slope of 100 mV/K (drift region concentration of measured device: 2×10¹⁵ cm⁻³). As a result, R_on/BV, known for a figure of merit of power device, increases with temperature.     

Oxide and interface trap densities estimation in ultrathin W/La2O3/Si MOS capacitors

A novel interpretation for conductance spectra obtained by conductance method of La₂O₃ gated MOS capacitors has been proposed. Two distinct peaks, one with broad spectrum ranging from 10 k to 200 kHz and the other near 1 kHz with a single time constant spectrum, have been observed at depletion condition. The former spectrum can be assigned as the interface traps (D_it) located at the interface between La-silicate and the Si substrate by statistical surface potential fluctuation model. On the other hand, as the latter slow trap signal shows strong influence with the thickness of La-silicate layer, it can be assigned as the trappings (D_slow) at the interface between La₂O₃ and La-silicate. Finally, the D_it and D_slow trends on annealing temperature are summarized.     

Mechanism of mobility enhancement in Ge p-channel metal-oxide-semiconductor field-effect transistor due to introduction of Al atoms into SiO2/GeO2 gate stack

In this paper, we present comprehensive results on Al-postmetallization annealing (Al-PMA) effect for the SiO₂/GeO₂ gate stack on a Ge substrate, which were fabricated by a physical vapor deposition method. The effective oxide thickness of metal-oxide-semiconductor (MOS) capacitor (CAP) was ~7 nm, and the Al-PMA was performed at a temperature in the range of 300–400 °C. The flat band voltage (V_FB), the hysteresis (HT), the interfacial states density (D_it), and the border traps density (D_bt) for MOSCAPs were characterized by a capacitance–voltage method and a constant-temperature deep-level transient spectroscopy method. The MOSCAP without Al-PMA had an electrical dipole of ~−0.8 eV at a SiO₂/GeO₂ interface, which was disappeared after Al-PMA at 300 °C. The HT, D_it, and D_bt were decreased after Al-PMA at 300 °C and were maintained in the temperature range of 300–400 °C. On the other hand, the V_FB was monotonically shifted in the positive direction with an increase in PMA temperature, suggesting the generation of negatively charged atoms. Structural analyses for MOSCAPs without and with Al-PMA were performed by a time-of-flight secondary ion mass spectroscopy method and an X-ray photoelectron spectroscopy method. It was confirmed that Al atoms diffused from an Al electrode to a SiO₂ film and reacted with GeO₂. The dipole disappearance after Al-PMA at 300 °C is likely to be associated with the structural change at the SiO₂/GeO₂ interface. We also present the device performances of Al-gated p-channel MOS field-effect transistors (FET) with PMA treatments, which were fabricated using PtGe/Ge contacts as source/drain. The peak field-effect mobility (μ_h) of the p-MOSFET was reached a value of 468 cm²/Vs after Al-PMA at 325 °C. The μ_h enhancement was explained by a decrease in the total charge densities at/near the GeO₂/Ge interface.     

Effects of post-annealing on the passivation interface characteristics of AlGaN/GaN high electron mobility transistors

We examined the effects of post-annealing in forming-gas ambient on the spin-on-dielectric (SOD)-buffered passivation as well as the conventional plasma-enhanced chemical vapor deposition (PECVD) Si₃N₄ passivation structure in association with the quantitative analysis of defects at the passivation interfaces of AlGaN/GaN high electron mobility transistors (HEMTs). Before the annealing, the interface state densities (D_it) of the PECVD Si₃N₄ are one-order higher (10¹²–10¹³ cm⁻² eV⁻¹) than those of the SOD SiO_x (10¹¹–10¹² cm⁻² eV⁻¹) as derived from C–V characterization. Clear reduction in D_it from the PECVD Si₃N₄ is extracted to a level of 10¹¹–10¹² cm⁻² eV⁻¹ with a stronger absorption from Si–N peak in Fourier transform infrared spectroscopy spectra after the post-annealing. On the other hand, negligible difference in D_it value is obtained from the SOD SiO_x. In this paper we propose that much lower measurement levels (~156 mA/mm) before the annealing and substantial recovery (~13% increase) after the annealing in maximum drain current density of the AlGaN/GaN HEMTs with Si₃N₄ passivations are due to the original higher density before the annealing and greater reduction in D_it of the PECVD Si₃N₄ after the annealing. Significant reduction after the annealing in gate–drain leakage current (from ~10⁻³ to ~10⁻⁵ A, 100-μm gate width) of the HEMTs with the Si₃N₄ passivation is also supposed to be attributed to the reduction of D_it.     

Microwave performance of field-plate 0.13-μm MOS transistors with varying field-plate extension

Si-based field-plate 0.13 μm gate length metal-oxide-semiconductor field effect transistor (Si MOSFET) with field-plate (FP) lengths of 0.1 μm, 0.2 μm, and 0.3 μm have been fabricated and investigated. The field-plate metals were connected to gate electrode in this study to improve device gate resistance (R_g) resulting in the better microwave performance. By increasing the length of field-plate metal extension (L_FPE), the off-state drain-to-source surface leakage current can be suppressed. Besides, low surface traps in FP NMOS also leads to a higher drain-to-source current (I_ds) especially at high current regime compared to standard device. The power added efficiency (PAE) was 56.3% for L_FPE of 0.3 μm device, and these values where 54.7% and 53.8% for L_FPE of 0.2 μm and 0.1 μm devices, respectively. Wider field-plate metal extension exhibits highly potential for low noise amplifier and high efficiency power amplifier applications.     

Performance analysis of long Ge channel double gate (DG) p MOSFETs with high-k gate dielectrics based on carrier concentration formulation

In this paper, electrical behavior of symmetric double gate Ge channel MOSFETs with high-k dielectrics is reported on the basis of carrier concentration formalism. The model relies on the solution of Poisson-Boltzmann equations subject to suitable boundary conditions taking into account the effect of interface trap charge density (D_it) and the Pao-Sah’s current formulation considering field dependent hole mobility. It is continuous as it holds good for sub-threshold, weak and strong inversion regions of device operation. The proposed model has been employed to calculate the drain current of DG MOSFETs for different values of gate voltage and drain voltage along with various important device parameters such as transconductance, output conductance, and transconductance per unit drain current for a wide range of interface trap charge density, equivalent oxide thickness (EOT) and bias conditions. Moreover, most of the important device parameters are compared with their corresponding Si counter parts. Accuracy of the model has been verified by comparing analytical results with the numerical simulation data. A notable improvement of the drive current and transconductance for Ge devices is observed with reference to Si devices, particularly when D_it is small.     

Characterization of P-channel power trench MOSFETs with polycrystalline silicon germanium gate electrode for faster switching

Electrical switching characteristics using polycrystalline silicon–germanium (poly-Si_l?xGe_x) gate for P-channel power trench MOSFETs was investigated. Switching time reduction of over 22% was observed when the boron-doped poly-Si gate was replaced with a similarly boron-doped poly-SiGe gate on the P-channel power MOSFETs. The fall time (T_f) on MOSFETs with poly-SiGe gate, was found to be ～11 ns lesser than the poly-Si gate MOSFET which is ～60% improvement in switching performance. However, all the switching improvement was observed during the fall times (T_f). The reason could be the higher series resistance in the switching test circuit masking any reduction in the rise times (T_r). Faster switching is achieved due to a lower gate resistance (R_g) offered by the poly-SiGe gate electrode as compared to poly-silicon (pSi) material. The pSi gate resistance was found to be 6.25 Ω compared to 3.75 Ω on the poly-SiGe gate measured on the same device. Lower gate resistance (R_g) also means less power is lost during switching thereby less heat is generated in the device. A very uniform boron doping profile was achieved with-in the pSiGe gate electrode, which is critical for uniform die turn on and better thermal response for the power trench MOSFET. pSiGe thin film optimization, properties and device characteristics are discussed in details in the following sections.     

Energy band alignment and interface states in AlGaN/4H–SiC vertical heterojunction diodes

The effects of Al_xGa_1−xN aluminum fraction x and SiC surface pre-treatment on AlGaN/4H–SiC heterojunction interfaces are experimentally investigated. From capacitance vs. voltage measurements, the conduction band offsets are found to be ΔE_C ≈ 0.30 for x ≈ 0.3 and ΔE_C ≈ 0.56 for x ≈ 0.5. Forward bias ideality factors are reasonable at 3.3 for Al_0.3Ga_0.7N diodes, but >9 for Al_0.5Ga_0.5N diodes, suggesting a higher level of interface charge related to the higher aluminum fraction. Reverse bias leakage is acceptably low, with breakdown occurring at V_A > 200 V reverse bias for all tested devices. The effect of 1500 °C hydrogen etching of the SiC substrate prior to Al_xGa_1−xN growth is also investigated, and found to have little effect for x = 0.3 but a beneficial effect for x = 0.5.     

Investigation of TiO2 on AlGaAs prepared by liquid phase deposition and its application

The study explored titanium dioxide (TiO₂) on aluminum gallium arsenide (AlGaAs) prepared by liquid phase deposition (LPD) at 40 °C. The leakage current density was about 8.4 × 10^?6 A/cm² at 1 MV/cm. The interface trap density (D_it) and the flat-band voltage shift (ΔV_FB) were 2.3 × 10¹² cm^?2 eV^?1 and 1.2 V, respectively. After rapid thermal annealing (RTA) in the ambient N₂ at 350 °C for 1 min, the leakage current density, D_it, and ΔV_FB were improved to 2.4 × 10^?6 A/cm² at 1 MV/cm, 7.3 × 10¹¹ cm^?2 eV^?1, and 1.0 V, respectively. Finally, the study demonstrates the application to the AlGaAs/InGaAs metal–oxide–semiconductor pseudomorphic high-electron-mobility transistor (MOS-PHEMT). The results indicate the potential of the proposed device with a LPD-TiO₂ gate oxide for power application.