X-ray microdiffraction investigation of crystallinity and strain relaxation in Ge thin lines selectively grown on Si(0 0 1) substrates

We used X-ray microdiffraction (XRMD) to investigate the crystallinity and strain relaxation of Ge thin lines with widths of 100, 200, 500 and 1000 nm selectively grown on Si(0 0 1) substrates using a patterned SiO₂ mask by chemical vapor deposition. The variations of the strain relaxation in the line and width directions were also investigated in Ge thin lines with a width of 100 nm. After growth, crystal domains with very small tilt angles were detected in Ge lines with all four line widths. The tilt angle range was larger in thinner Ge lines. After annealing at 700 °C, the formation of a single, large domain with a specific tilt angle was detected by XRMD for Ge thin lines with widths of 100 and 200 nm. These experimental results reflect the effects of SiO₂ side walls around the Ge thin lines on crystallinity and strain relaxation of Ge.     

Praseodymium oxide growth on Si(1 0 0) by pulsed-laser deposition

We report on the pulsed-laser deposition of high-K praseodymium oxide films onto Si(1 0 0) surfaces by laser-ablating a sintered Pr₆O₁₁ target. Optical microscope, SEM, and AFM investigations reveal two kinds of Pr_xO_y-surface structures, which are identified as: (a) large-scaled particles, and (b) ordered structures (rods) of different size with different orientations. The size of the particles increases with laser wavelength. The size of the ordered surface structures strongly depends on the substrate temperature. For the first time, we show characteristic Pr-Raman signals which confirm the crystalline quality of the grown layer. They also indicate that the silicon layer at the Si–Pr_xO_y interface is under compressive stress.     

Temperature-controlled self-organized InP nanostructures grown on GaAs(1 0 0) substrate by MOCVD

The self-organized InP nanostructures grown on GaAs(0 0 1) substrates by metalorganic vapor deposition were examined in detail using atomic force microscopy. By properly selecting growth temperature, three kinds of nanostructure, islands, pits and ripples were formed. For growth temperature of 400–450 °C, the surface morphologies were governed by islands; but, for the growth temperature of 500 °C, the formation of surface ripples instead of islands was presumably due to the combination effect of temperature-controlled surface kinetics and strain effect. On the other hand, the observation of enhanced growth of pits upon a high-temperature annealing (at 685 °C for 90 s) indicated that the strained InP epitaxial film would be morphologically stabilized by taking the form of pits formation.     

Low threading dislocation density Ge deposited on Si (1 0 0) using RPCVD

Epitaxial Ge layer growth of low threading dislocation density (TDD) and low surface roughness on Si (1 0 0) surface is investigated using a single wafer reduced pressure chemical vapor deposition (RPCVD) system. Thin seed Ge layer is deposited at 300 °C at first to form two-dimensional Ge surface followed by thick Ge growth at 550 °C. Root mean square of roughness (RMS) of ∼0.45 nm is achieved. As-deposited Ge layers show high TDD of e.g. ∼4 × 10⁸ cm⁻² for a 4.7 μm thick Ge layer thickness. The TDD is decreasing with increasing Ge thickness. By applying a postannealing process at 800 °C, the TDD is decreased by one order of magnitude. By introducing several cycle of annealing during the Ge growth interrupting the Ge deposition, TDD as low as ∼7 × 10⁵ cm⁻² is achieved for 4.7 μm Ge thick layer. Surface roughness of the Ge sample with the cyclic annealing process is in the same level as without annealing process (RMS of ∼0.44 nm). The Ge layers are tensile strained as a result of a higher thermal expansion coefficient of Ge compared to Si in the cooling process down to room temperature. Enhanced Si diffusion was observed for annealed Ge samples. Direct band-to-band luminescence of the Ge layer grown on Si is demonstrated.     

Wetting layer formation in superlattices with Ge quantum dots on Si(1 0 0)

The influence of parameters of germanium deposition on wetting layer thickness was studied during the growth on the Si(1 0 0) surface. A non-monotone dependence of the thickness on growth temperature was discovered and accounted for by changing the mechanism of the layer-by-layer growth. The conclusion was supported by changing the mode of oscillations of the reflection high-energy electron diffraction (RHEED) specular beam. In addition, wetting layer thickness is strongly affected by the replication number and thickness of the silicon spacer due to accumulation of elastic strains throughout the structure.     

Structural characterization of ultra-thin (0 0 1) silicon films bonded onto (0 0 1) silicon wafers:: a transmission electron microscopy study

Ultra-thin (0 0 1) silicon films (thickness less than 25 nm) directly bonded onto (0 0 1) silicon wafers have been investigated by transmission electron microscopy. Twist interfacial dislocations accommodate the twist between the two crystals, whereas tilt interfacial dislocations accommodate the tilt resulting from the residual vicinality of the initial surfaces. In low-twist angle grain boundaries, twist interfacial dislocations are dissociated and no precipitates are detected. In high-twist angle grain boundaries, there is no dissociation and a high density of silicon oxide precipitates is observed at the interface. Tilt interfacial dislocations are pinned by these precipitates, they are more mobile than precipitates. Without precipitates, their lines are straighter than those with precipitates, and this is especially when the bonded wafers are annealed at a high temperature. When no precipitates are present, tilt interfacial dislocations are associated by pairs, and we demonstrate that each tilt interfacial dislocations introduce a diatomic interfacial step at the interface.     

Growth temperature dependence of epitaxial Gd2O3 films on Si(1 1 1)

This article reports on the epitaxy of crystalline high κ oxide Gd₂O₃ layers on Si(1 1 1) for CMOS gate application. Epitaxial Gd₂O₃ thin films have been grown by Molecular Beam Epitaxy (MBE) on Si(1 1 1) substrates between 650 and 750 °C. The structural and electrical properties were investigated depending on the growth temperature. The C–V measurements reveal that equivalent oxide thickness (EOT) equals 0.7 nm for the sample deposited at the optimal temperature of 700 °C with a relatively low leakage current of 3.6 × 10^?2 A/cm² at |V_g ? V_FB| = 1 V.     

Optical and microstructural characterization of the effects of rapid thermal annealing of CdTe thin films grown on Si (100) substrates

The effects of rapid thermal annealing (RTA) on CdTe/Si (100) heterostructures have been studied in order to improve the structural quality of CdTe epilayers. Samples of CdTe (111) polycrystalline thin films grown by vapor phase epitaxy (VPE) on Si (100) substrates have been investigated. The strained structures were rapidly thermally annealed at 400°C, 450°C, 500°C, 550°C, and 600°C for 10 sec. The microstructural properties of the CdTe films were characterized by carrying out scanning electron microscopy (SEM), x-ray diffraction (XRD), and atomic force microscopy (AFM). We have shown that the structural quality of the CdTe epilayers improves significantly with increasing annealing temperature. The optimum annealing temperature resulting in the highest film quality has been found to be 500°C. Additionally, we have shown that the surface nucleation characterized by the island size distribution can be correlated with the crystalline quality of the film.     

Morphological evolution and lateral ordering of uniform SiGe/Si(0 0 1) islands

By investigating the morphological evolution during epitaxial growth of Ge on Si(0 0 1) substrates, we find that highly uniform distributions of islands can be obtained. The islands are no longer domes but they consist of barns, which are bounded by steeper facets. A detailed morphological analysis indicates the presence of facets at their base, which are not stable for Ge but for Si. Finally, we show that long-range ordering of highly uniform SiGe barns can be obtained when the growth is performed on patterned Si(0 0 1) substrates.     

Epitaxial growth of LaAlO3 on Si(0 0 1) using interface engineering

In this work, the potentiality of molecular beam epitaxy techniques to prepare epitaxial lanthanum aluminate (LaAlO₃) films on Si(0 0 1) is explored. We first demonstrate that the direct growth of LaAlO₃ on Si(0 0 1) is impossible : amorphous layers are obtained at temperatures below 600 °C whereas crystalline layers can be grown at higher temperatures but interfacial reactions leading to silicate formation occur. An interface engineering strategy is then developed to avoid these reactions. SrO and SrTiO₃ have been studied as buffer for the subsequent growth of LaAlO₃. Only partial LaAlO₃ epitaxy is obtained on SrO whereas high quality layers are achieved on SrTiO₃. However both SrO and SrTiO₃ appear to be unstable with respect of Si at the growth temperature of LaAlO₃ (700 °C). This leads to the formation of relatively thick amorphous interfacial layers. Despite their instability at high temperature, these processes could be used for the fabrication of twins-free LaAlO₃ templates on Si, and for the fabrication of complex oxide/Si heterostructures for various applications.     

A high Schottky barrier between Ni and S-passivated n-type Si(1 0 0) surface

By minimizing surface states with sulfur passivation, a record-high Schottky barrier is achieved with nickel on n-type Si(1 0 0) surface. Capacitance–voltage measurements yield a flat-band barrier height of 0.97 eV. Activation-energy and current–voltage measurements indicate ～0.2-eV lower barriers for the Ni/Si(1 0 0) junction. These results accompany a previously-reported record-high Schottky barrier of 1.1 eV between aluminum and S-passivated p-type Si(1 0 0) surface. The operation of these metal/Si(1 0 0) junctions changes from majority-carrier conduction, i.e., a Schottky junction, to minority-carrier conduction, i.e., a p–n junction, with the increase in barrier height from 0.97 eV to 1.1 eV. Temperature-dependent current–voltage measurements reveal that the Ni/S-passivated n-type Si(1 0 0) junction is stable up to 110 °C.     

Interplay of geometric and electronic structure in thin films of diindenoperylene on Ag(1 1 1)

Using the example of Diindenoperylene (DIP) a strong dependence of ionization potential, electron affinity and transport gap on the growth conditions of an organic molecular thin film is demonstrated. DIP single crystals show a remarkable polymorphism as single crystals as well as crystalline films on weakly interacting substrates like Au or SiO₂ surfaces. We have investigated DIP thin films on Ag(1 1 1) substrates and found a strong dependence of the photoemission and inverse photoemission spectra as well as of the low energy electron diffraction (LEED) patterns on the substrate temperature. Three different temperature regions could be identified with distinct reproducible signatures in the structural data as well as in the valence level spectra. Peak positions, line widths, and relative intensities directly correlate with the degree of order and with the molecular orientation. Moreover, we identified a systematic change of the structural quality ranging from high mosaicity at low temperature (<150 K) via small ordered domains (150–250 K) to a high degree of order at elevated temperature (>350 K).     

High quality relaxed Ge layers grown directly on a Si(0 0 1) substrate

After a long period of developing integrated circuit technology through simple scaling of silicon devices, the semiconductor industry is now embracing technology boosters such as strain for higher mobility channel material. Germanium is the logical supplement to enhance existing technologies, as its material behaviour is very close to silicon, and to create new functional devices that cannot be fabricated from silicon alone (Hartmann et al. (2004) [1]). Germanium wafers are, however, both expensive and less durable than their silicon counterparts. Hence it is highly desirable to create a relaxed high quality Ge layer on a Si substrate, with the provision that this does not unduly compromise the planarity of the system. The two temperature method, proposed by Colace et al. (1997) [2], can give smooth (RMS surface roughness below 1 nm) and low threading dislocation density (TDD <10⁸ cm⁻²) Ge layers directly on a Si(0 0 1) wafer (Halbwax et al. (2005) [3]), but these are currently of the order of 1-2 μm thick (Hartmann et al. (2009) [4]).We present an in depth study of two temperature Ge layers, grown by reduced pressure chemical vapour deposition (RP-CVD), in an effort to reduce the thickness. We report the effect of changing the thickness, of both the low temperature (LT) and the high temperature (HT) layers, emphasising the variation of TDD, surface morphology and relaxation.Within this study, the LT Ge layer is deposited directly on a Si(0 0 1) substrate at a low temperature of 400 °C. This low temperature is known to generate monolayer islands (Park et al. (2006) [5]), but is sufficiently high to maintain crystallinity whilst keeping the epitaxial surface as smooth as possible by suppressing further island growth and proceeding in a Frank-van der Merwe growth mode. This LT growth also generates a vast number of dislocations, of the order of 10⁸-10⁹ cm⁻², that enable the next HT step to relax the maximum amount of strain possible. The effect of varying the HT layer thickness is studied by depositing on a LT layer of fixed thickness (100 nm) at a higher growth temperature of 670 °C. We find that the HT layer allows Ge-on-Ge adatom transport to minimise the surface energy and smooth the layer. The final step to the technique is annealing at a high temperature that allows the dislocations generated to glide, increasing the degree of relaxation, and annihilate. We find that annealing can reduce the TDD to the order of 10⁷ cm⁻², but at a cost of a significantly roughened surface.     

Effect of high-temperature annealing on GaInP/GaAs HBT structures grown by LP-MOVPE

We have investigated the effect of high-temperature annealing on device performance of GaInP/GaAs HBTs using a wide range of MOVPE growth parameters for the C-doped base layer. Carbon doping was achieved either via TMG and AsH₃ only or by using an extrinsic carbon source. High-temperature annealing causes degradation of carbon-doped GaAs in terms of minority carrier properties even at doping levels of p=1 × 10¹⁹ cm⁻³. The measured reduction in electron lifetime and luminescence intensity correlates with HBT device results. It is shown that the critical temperature where material degradation starts is both a function of doping method and carbon concentration.     

Effect of deposition rate and thickness on the structural and electrical properties of evaporated Ni/glass and Ni/Si(1 0 0) thin films

We have studied the effect of substrates [glass and Si(1 0 0)], of Ni thickness (t_Ni) and of the deposition rate [v₁=13 nm/min and v₂=22 nm/min] on the structural and electrical properties of evaporated Ni thin films. The Ni thickness, measured by the Rutherford backscattering (RBS) technique, ranges from 28 to 200 nm. From X-ray diffraction, it was found that all samples are polycrystalline and grow with the 〈1 1 1〉 texture. From the measure of the lattice constant, we inferred that Ni/Si samples are under a higher tensile stress than the Ni/glass ones. Moreover, in Ni/glass deposited at v₁, stress is relived as t_Ni increases while those deposited at v₂ are almost stress-free. The grain size (D) in Ni/glass with low deposition rate monotonously increases (from 54 to 140 Å) as t_Ni increases and are lower than those corresponding to Ni/Si. On the other hand, samples grown at v₂ have a constant D, for small t_Ni with D in Ni/glass larger than D in Ni/Si. Ni/glass deposited at low v₁ are characterized by a higher electrical resistivity (ρ) than those deposited at v₂. For the latter series, ρ is practically constant with t_Ni but decreases with increasing grain size, indicating that diffusion at the grain boundaries rather than surface effect is responsible for the variation of ρ in this thickness range. For the Ni/glass deposed at v₁ and the Ni/Si series, ρ has a more complex variation with thickness and deposition rate. These results will be discussed and correlated.     

Synthesis of GaN nanowires by ammoniation of Ga2O3 films on Nb layer deposited on Si(1 1 1) substrates

Single-crystalline GaN nanowires have been successfully synthesized on Si(1 1 1) substrates by magnetron sputtering through ammoniation of Ga₂O₃/Nb films at 900 °C in a quartz tube. The as-synthesized GaN nanowires are confirmed to be single-crystalline GaN with wurtzite structure by X-ray diffraction (XRD), selected-area electron diffraction (SAED) and field-emission transmission electron microscopy (FETEM); scanning electron microscopy (SEM) shows that the GaN nanowires are smooth, with diameters of about 50 nm and lengths typically up to several microns, which could provide an attractive potential for incorporation in future GaN electronic devices into Si-based large-scale integrated circuits. Finally, the growth mechanism of GaN nanowires is also briefly discussed.     

Influence of substrate temperature to prepare (1 0 3) oriented AlN films

(1 0 3) Oriented AlN films is an attractive piezoelectric material for the applications on surface acoustic wave (SAW) and film bulk acoustic wave (FBAR) devices. As regards the SAW properties of the (1 0 3) oriented AlN films, the electromechanical coupling constant (K²) is larger than the (0 0 2) oriented AlN films. As regards the bulk acoustic wave (BAW) properties of (1 0 3) oriented AlN films, it can excite a quasi-shear mode (velocity = 5957 m/s, K² = 3.8%) that can be used for FBAR liquid sensor. In this research, the (1 0 3) oriented AlN films were successfully prepared on the silicon substrate by rf magnetron sputtering. Different temperatures (100 °C, 200 °C, 300 °C, and 400 °C) were used in this experiment process. The crystalline structure of films was determined by X-ray diffraction (XRD) and the surface microstructure was investigated by the atomic force microscope (AFM). The result exhibited the optimal substrate temperature is 300 °C. The optimal (1 0 3) oriented AlN films have the strongest XRD intensity, the smallest full width at half maximum (FWHM) value (0.6°), the largest grain size (15.8 nm) and the smoothest surface (Ra = 3.259 nm).     

多片垂直HWLPCVD系统生长的3C-SiC异质外延膜的研究

文章报道了利用我们自主研发的垂直多片HWLPCVD系统,在Si(100)衬底上获得的3C-SiC异质外延膜的最新结果。多片HWLPCVD系统最多可容纳3个直径为50mm的晶片,托盘可旋转。实验系统研究了3C-SiC外延膜的片内和片间均匀性,包括结晶质量,厚度和电学特性。片内厚度和方块电阻均匀性（标准差/平均值）最好可达3.40%和5.37%,片间厚度和方块电阻均匀性最好可达4.00%和4.24%。     

Photoelectron spectroscopy (XPS) and photoelectron diffraction (XPD) studies on the system hafnium silicide and hafnium oxide on Si(1 0 0)

Continuous down-scaling of silicon based transistors results in device lengths of less than 100 nm. This requires a reduction of the gate dielectric thickness to less than 15Å which is not possible for SiO₂ due to an increasing leakage current. One of the most promising candidates for a replacement material for the gate dielectric is HfO₂ [Wilk GD, Wallace RM, Anthony JM. J Appl Phys 2001; 89:5243].In this work we applied X-ray photoelectron spectroscopy (XPS) and photoelectron diffraction measurements in order to study the interface of hafnium oxide to Si(1 0 0). The high resolution measurements were performed with synchrotron radiation at beamlines 5 and 11 at DELTA (Dortmund). For the first time, photoelectron diffraction patterns for this system were recorded. The spectral resolution allowed to separate different spectral components.The preparation of hafnium oxide films on Si(1 0 0) was performed by evaporation of hafnium at a partial oxygen background pressure of . Three different spectral components were observed in the hafnium 4f photoemission signal by high resolution XPS. The photoelectron signals with binding energies shift of 3.1 and 1.2 eV with respect to signal of hafnium silicide were assigned to hafnium dioxide and hafnium silicate, respectively. The corresponding high-resolution diffraction patterns result from different local environments for each component. The experimental patterns are compared with simulations for a model structure of hafnium silicide.     

Multi-wafer 3C-SiC thin films grown on Si(100) in a vertical HWLPCVD reactor

We report the latest results of the 3C-SiC layer growth on Si(100)substrates by employing a novel home-made horizontal hot wall low pressure chemical vapour deposition(HWLPCVD)system with a rotating susceptor that was designed to support up to three 50 mm-diameter wafers.3C-SiC film properties of the intrawafer and the wafer-to-wafer,including crystalline morphologies and electronics,are characterized systematically. Intra-wafer layer thickness and sheet resistance uniformity(σ/mean)of～3.40%and～5.37%have been achieved in the 3×50 mm configuration.Within a run,the deviations of wafer-to-wafer thickness and sheet resistance are less than 4%and 4.24%,respectively.