Design and analysis of a highly secure stream cipher based on linear feedback shift register

Linear feedback shift register (LFSR) based stream ciphers are popular because of their low hardware implementation costs. The nonlinear combination generators and clock-controlled generators are two very commonly used schemes in LFSR based stream ciphers. FPGA implementation of these two schemes has been done to obtain an idea about the hardware complexity of the two schemes. The fast correlation attack and edit distance attack, which are the fastest of the reported attacks on the nonlinear combination generators and clock-controlled generators respectively, have been implemented. A new model for LFSR based keystream generation has been proposed by combining the two existing schemes. The proposed model is based on the detailed comparative study and cryptanalysis of the two existing schemes mentioned.     

基于多输入特征寄存器的哈希方法

无源器件的能量和计算资源有限。针对这种器件的安全认证需求,提出了一种新的哈希方法M—hash。该方法基于低复杂性的并行输入LFSR,即多输入特征分析寄存器（MISR）,采用并行压缩方法,具有硬件复杂性低、速度快等特点。理论分析和具体硬件实现表明,M-hash在硬件复杂性、压缩速度和安全性等方面均优于另外一种基于LFSR的Toeplitz希方法。     

广义自缩序列的FBDD攻击*

流密码是加密体制中的一种重要体制,一直是军事、政府等敏感部门加密的主要手段,近年来在新一代移动通信中占有主流地位。其安全性主要依赖于密钥流序列的安全。基于LFSR的构造是密钥流构造中最为常见的一种。针对基于单个LFSR的广义自缩序列,提出了一种FBDD攻击。该攻击基于BDD攻击,充分利用了BDDs对布尔函数操作上的优良特性。算法分析表明,其时间复杂度是理想的,但是其所需的内存空间较大,有待于进一步的改进。     

基于FCSR和LSFR相结合的密钥流生成器

分析了由Schneier提出的FCSR和线性反馈移位寄存器（LFSR）相结合的密钥流生成器的结构特性,给出了其可生成密钥流的周期和线性复杂度的理论上界,讨论如何选择LFSR和FCSR的参数以使产生的密钥流具有较好的伪随机特性,并使其周期和线性复杂度尽可能接近理论上界。利用美国技术与标准局（NIST）提供的STS软件包进行生成器选定参数下输出的密钥流的8项随机性测试,结果表明,在该文论述的参数选择方法下,生成器产生的序列具有良好的伪随机特性。利用FPGA实现了该密钥流生成器,并通过与5种现有流密码方案实现结果的性能比较发现,该方案具有较高的密钥流吞吐量和性价比,可在移动终端实施。     

基于多配置LFSR的测试生成结构设计

针对内建自测试技术中传统的测试生成故障覆盖率过低、硬件开销过大等缺点,提出了一种多配置LFSR的混合测试矢量生成结构,结构利用矩阵理论先后对随机性矢量和确定性矢量进行反馈网络的配置;针对确定性矢量的生成,提出了一种反馈配置解的寻优算法,在一定程度上减少了硬件开销,因结构生成的混合测试矢量可以同时检测出被测电路中的随机矢量可测性故障和抗随机性故障,进而保证了测试故障覆盖率。最后,通过实例和对几种综合基准电路的测试,验证了该方案的可行性。     

Automata Over Abstract Finite Quasigroups

This paper analyzes the structure of families of automata without output that are defined by recurrence relations on abstract finite quasigroups. The expediency of their use to design iterated hash functions with sufficiently high security is justified. It is shown how some families of reversible Mealy and Moore automata can be constructed based on such families of automata without output. The expediency of using the proposed families of Mealy and Moore automata as the basis to construct mathematical models for stream ciphers is substantiated.     

基于多扫描链的内建自测试技术中的测试向量生成

针对基于多扫描链的内建自测试技术,提出了一种测试向量生存方法。该方法用一个线性反馈移位寄存器（LFSR）作为伪随机测试向量生成器,同时给所有扫描链输入测试向量,并通过构造具有最小相关度的多扫描链克服扫描链间的相关性对故障覆盖率的影响。此外该方法经过模拟确定难测故障集,并针对这外难测故障集利用ATPG生成最小确定性测试向量集。最后丙依据得到的最小测试向量集来设计位改变逻辑电路,利用们改变逻辑电路控制改变扫描链上特定的值来实现对难测故障的检测,从而实现被测电路和故障完全检测。     

Pseudo-Random Test Generation for Large Combinational Circuits

In this paper,a simulation system of pseudo-random testing is described first to investigate thecharacteristics of pseudo-random testing.Several interesting experimental results are obtained.It isfound out that initial states of pseudo-random sequences have little effect on fault coverage.Fixedconnection between LFSR outputs and circuit inputs in which the number of LFSR stages m is less thanthe number of circuit inputs n leads to low fault coverage,and the fault coverage is reduced as mdecreases.The local unrandomness of pseudo-random sequences is exposed clearly.Generally,when anLFSR is employed as a pseudo-random generator,there are at least as many LFSR stages as circuitinputs.However,for large circuits under test with hundreds of inputs,there are drawbacks of using anLFSR with hundreds of stages.In the paper,a new design for a pseudo-random pattern generator isproposed in which m相似文献   

部分向量奇偶位切分的LFSR重新播种方法

提出一种基于部分测试向量奇偶位切分的LFSR重新播种测试方法.针对确定测试集中各个测试向量包含确定位的位数有较大差异以及测试向量所含的确定位大多连续成块的特点,通过奇偶切分部分确定位较多的向量,使得编码压缩的LFSR度数得到有效降低,从而提高了测试数据压缩率.其解压缩电路仍然采用单个LFSR进行解码与切分向量的合并.与目前国际同类编码压缩方法相比,具有测试数据压缩率高、解压硬件开销低、测试数据传输协议简单等特点.     

一类p元d型序列的线性复杂度

伪随机序列在保密通信、扩频通信和码分多址通信系统中具有广泛的应用,常用来作为保密通信中的密钥流序列、扩频通信中的扩展频谱序列和码分多址通信系统中地址序列。在流密码的设计理论中,需要在严格的数学框架内使用复杂性度量方法来判断密钥流的不可预测性,也就是由特定加密系统所能提供的安全级别,最重要的度量标准是线性复杂度,线性复杂度是指生成作为密钥流序列的最短的LFSR的长度。本文研究了一类使用迹函数构造的p元d型序列的线性复杂度,给出了在特定条件下这类序列的线性复杂度的上界,并构造了线性复杂度达到上界的d型序列,从而表明这个上界是紧的。     

Modified dynamic current mode logic based LFSR for low power applications

Shift Register, which is a cascade of flip flops shares the same clock and the outputs are connected to the data input of the next one in the chain. Linear-feedback shift register or shortly LFSR is one such shift register whose input is a linear function of its previous state. Exclusive-OR (XOR) is the most commonly used linear function. LFSR's help in generating pseudo-random numbers, fast digital counters, pseudo-noise sequences and whitening sequences. LFSR's can be realised both using hardware and software. When it comes to hardware implementation, MOS current mode logic (MCML) method can be used for designing the LFSR. There are lots of drawbacks with the traditional MCML method including the static power dissipation, more power consumption at low frequencies as compared with CMOS circuits, inappropriate for large systems involving power-down modes and it's not a cost effective solution either. To overcome these issues and to achieve the high speed characteristics of MCML, we present the modified dynamic current mode logic and is a good solution for battery powered systems and portable solutions. Our simulation results also confirm the same where a 16 bit adder circuit fabricated using CMOS technology has only a delay of 1.22 ns and dissipates 19.0 mW at 400 MHz.     

一种基于分组密码的hash函数的安全性分析及构造

利用已有的分组密码构造hash函数是一种非常方便的构造方法.早在1993 年Preneel 等人就对使用分组密码构造的64种hash 函数进行了安全分类,这些hash函数统称为PGV体制,它们都是单倍分组长度的,即输出长度和分组长度相同.2002 年Black在他的论文中对这64 种hash函数的安全性进行了严格的证明,证明其中的20种是安全的,其他是不安全的.随着计算技术的发展,人们感到单倍分组长度的hash函数的安全性不足,于是一些双倍分组长度的基于分组密码的hash函数被提了出来.但是其中的很多是不安全的.在AsiaCrypt2006上,一种使用了5个分组密码的双倍分组长度的hash函数被提了出来.作者声明这种构造方式是安全的,但没有给出安全性证明.本文对该体制进行了分析,发现其安全性并不理想,并针对本文的攻击提出了一种新的基于分组密码的hash函数,同时和SHA-256等hash函数的性能进行了对比.     

多重周期序列联合线性复杂度及其快速算法

周期序列的线性复杂度是衡量流密码系统安全性能的一个重要指标。近几年人们注重对多重周期序列的联合线性复杂度的研究。该文给出了Fp上周期为Pn的多重周期序列联合线性复杂度的一个新的表达式，介绍了周期为Pn的随机多重周期序列联合线性复杂度分布的计算方法，提出了一种周期为Pn的多重周期序列联合线性复杂度的快速算法。     

第四类广义自缩序列的分析

广义自缩序列是基于LFSR的一类非常规钟控的序列,具有良好的伪随机性,可以用作加密时的密钥流。该文对其中的一类序列—第四类广义自缩序列,提出了一种攻击方法,其目的是恢复LFSR的初始状态,主要思路是首先利用统计分析方法构造出一个拟合序列,然后利用快速相关攻击恢复对应序列的初态,最后利用解线性方程组的方法恢复出目标序列的初始状态。分析表明该攻击是有效的。     

Dynamic partial reconfiguration enchanced with security system for reduced area and low power consumption

Field-programmable gate arrays (FPGAs) have travelled far from just being utilized as glue logic to an entire system solution. This is mostly due to their generalized re-configurable nature, lower non-recurring engineering (NRE) expense, and also fast time to market. Owing to the reconfigurable nature of FPGA, a new field called reconfigurable computing that can change the circuit configuration after hardware production came into existence. Application of re-configurable computing for self-adaptive hardware allows hardware to get adapt to various environmental conditions and different needs by swapping or loading disparate computational modules. This work proposes an effectual design methodology (enhanced DPR security system (EDPRSS)) utilized to execute high performance FPGA device in respect of low power consumption along with security for the area reduction. In the proposed technique, hash code generation (HCG) and encryption hardware accelerators can well be dynamically produced on FPGA utilizing partial re-configuration as stated by the application requisites. The system is competent to swap in or swap out the equivalent hardware accelerator during run time, which in turn diminishes the power and area. Here, 2 re-configurable partitions are produced for encryption and also HCG algorithm. Experiential outcomes proved that the proposed technique proffers better performance when contrasted to the other conventional systems.     

基于流密码的可重构处理结构及其专用指令集研究

在对多种流密码算法生成结构进行分析的基础上,提出一种基于流密码的可重构处理结构,并在总结重构流密码算法使用频率较高的基本操作类型的基础上,为该流密码可重构处理结构设计了一种专用指令集。描述了指令的具体格式,并对指令性能进行了评估。结果表明,该指令集作用在该流密码可重构结构上可灵活高效地实现多种流密码算法。     

An approach for stream ciphers design based on joint computing over random and secret data

This paper proposes and analyzes an approach for design of stream ciphers based on joint computing over random and secret data. Feasibility of encryption/ decryption computation when the ciphertext involve pure random data is shown. The core element of the proposed approach for stream ciphering is a pseudo-random embedding of the random bits into the ciphertext and this embedding plays role of a homophonic encoding. The initial ciphertext with the embedded random bits is further on intentionally degraded by its exposure to a moderate noise which can be modelled as the binary symmetric channel effect. A security evaluation of the proposed approach implies that its security appears as a consequence of hardness of the LPN problem, as well. The developed design has potential of providing that complexity of recovering the secret key in the known plaintext attack scenario is close to the complexity of recovering the secret key via the exhaustive search, i.e. close to the maximal possible one for the given size of the secret key. The proposed approach can be considered as a trade-off between the increased security and decreased communications efficiency which in a number of scenarios appears as a suitable one.     

Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security

Communication protocols for wireless networks have specified security layers, with high-level encryption strength. The dedicated to security layer of Wireless Application Protocol (WAP), is the Wireless Transport Layer Security (WTLS). In this paper, an efficient architecture for the hardware implementation of WTLS is proposed. The introduced system supports bulk encryption, authentication and data integrity. The proposed architecture operates alternatively for a set of ciphers, IDEA, DES, RSA, D.H., SHA-1 and MD5. It is based on two reconfigurable design units: the Reconfigurable Authentication Unit and the Reconfigurable Integrity Unit. These units operate alternatively for different ciphers and achieve to allocate minimized resources, at the same time. The introduced security system has been implemented in an FPGA device. The supported ciphers performance is compared with previously published works, and it has been proven superior to them, in most of the cases. The system’s synthesis results prove that the proposed architecture is a flexible and powerful solution for WTLS integration of today’s and future wireless networks. The system can be applied to wireless communications servers and mobile devices also. Finally, the proposed architecture can be used as a powerful security engine, in WAP communication networks, with special security demands.     

CRC校验码并行计算的FPGA实现

用软件实现CRC校验码计算很难满足高速数据通信的要求,基于硬件的实现方法中,有串行经典算法LFSR电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR电路为基础,研究了按字节并行计算CRC校验码的原理,并以常见的CRC-16和CRC-CCITT为例,用VHDL语言进行了可综合设计。结果表明这种实现方法在速度和占用资源方面优于常见的设计,适合在FPGA中实现CRC校验码的计算。     

基于FPGA的Leighton-Micali签名方案密钥生成的高速可配置实现

由于量子计算机的飞速发展,现代密码学面临着巨大的挑战。为了实现抗量子计算机攻击的加密,人们提出了许多新的加密方案,并对后量子密码学(Post-Quantum Cryptography,PQC)开展了标准化进程。Leighton-Micali签名(Leighton-Micali signature,LMS)是一种基于哈希的后量子签名方案,其私钥和公钥尺寸都较小,且安全性已被充分研究。LMS被互联网工程小组(Internet Engineering Task Force,IETF)选为PQC签名协议的标准方案,同时被美国国家标准技术局(National Institute of Standardsand Technology,NIST)选为一种PQC过渡方案。然而,密钥生成过程中的效率低下,成为了LMS实际应用中的瓶颈。在本文中,我们首次对LMS进行基于FPGA的硬件实现与加速。首先,在不损失安全性的基础上,我们将LMS中的主要哈希函数由SHA2替换为SHA3函数。其次,我们设计了一个软硬件协同系统,将核心的哈希运算用硬件进行实现,该系统在消耗较少资源的前提下,可完成LMS协议的所有过程:密钥生成、签名与验证。该系统为物联网(Internet of things,IoT)场景下资源受限的LMS应用提供了参考。接着,我们提出了一个高速的密钥生成架构来加速LMS。该架构中具有可配置性,支持LMS的所有参数集,内部的哈希模块根据使用场景进行设计与部署,且并行度经过精心设计,以使得架构同时达到低延迟和高硬件利用率。此外,设计中的控制逻辑被设计为在适应不同参数集的情况下保持一定程度的恒定功率,以抵御功率分析攻击。该架构使用Verilog实现,并在Xilinx Zynq UltraScale+MPSoC ZCU104 FPGA平台上实验。实验结果表明,与在Intel (R) Core (TM) i7-6850K 3.60GHz CPU上启用多线程的目前较优软件实现相比,本文中的设计在不同参数配置下可实现55x~2091x的加速;与最新的各平台LMS工作相比,本文中设计可实现超过17x的加速;与相近方案的FPGA工作相比,本文中设计可实现约70x的加速。