Effect of trapped charge accumulation on the retention of charge trapping memory

The accumulation process of trapped charges in a TANOS cell during P/E cycling is investigated via numerical simulation.The recombination process between trapped charges is an important issue on the retention of charge trapping memory.Our results show that accumulated trapped holes during P/E cycling can have an influence on retention,and the recombination mechanism between trapped charges should be taken into account when evaluating the retention capability of TANOS.     

陷阱俘获存储器中电荷积累过程对保持特性的影响

本文通过数值模拟的方法对陷阱俘获存储器单元在多次擦写过程中的电荷积累过程进行了分析。由于多次擦写后陷阱电荷的积累,电荷之间的复合过程成为一个重要的问题。分析结果显示擦写过程中积累的空穴会对存储器的保持特性产生影响,同时在分析器件保持特性的时候电荷之间的复合机制必须加以考虑。     

BE-TANOS: Feasibility and technology limitations

The aim of this work is to investigate the physical mechanisms behind the write/erase and retention performances of band gap engineering (BE) layers used as tunnel oxide in charge trap memory stack. The investigation of the BE layers alone will be completed with the analyses of its integration within a TANOS (TaN/Alumina/Nitride/Oxide/Silicon) stack, pointing out the correlation between electrical performance and reliability limits.Good write/erase/retention performances can be achieved with BE tunnel oxide by using silicon nitride layer integrated in SiO₂-Si₃N₄-SiO₂ stack, as long as all different mechanisms are taken into account in optimizing stack composition: hole injection which improves erase efficiency, charge trapping and de-trapping from the thin silicon nitride which causes program instabilities and initial charge loss which does not significantly impact long term retention. All these phenomena make very crucial the BE tunnel process control and difficult its use for multi-level application.     

Influence of metal gate and capping film stress on TANOS cell performance

In this work it is shown that film stress in the gate stack of TANOS NAND memories plays an important role for cell device performance and reliability. Tensile stress induced by a TiN metal gate deteriorates TANOS cell retention compared to TaN gate material. However, the erase saturation level as well as cell endurance is improved by the use of a TiN gate. This trade-off between retention and erase saturation for TANOS cells is elaborated in detail.     

Cycling copper flip chip interconnects

Use of flip chip assembly on compound semiconductor circuits is relatively new. Although solder bumping has been around for a while, use of copper bumps is also new. This discussion is intended to provide some initial data on the melding of copper flip chip bumps and compound semiconductor technologies, with respect to thermal excursion testing––cycling. For comparison, it is known that attempts to accelerate degradation caused by thermal excursions on solder bumps can result in irregular failure mechanisms. This work shows that on-chip power cycling can be used to cause identical failure mechanisms to those caused by normal temperature cycling.     

GaAs FET Failure Mechanisms Due to High Humidity and Ionic Contamination

Failure mechanisms resulting from the concurrent exposure to high relative humidity, ion contamination, and temperature cycling were studied in commercially available, low noise GaAs fieldeffect transistors (FETs). This type of device will be applied in such adverse environmental conditions. Devices with Al and Au/refractory gates from four different suppliers were studied. Au/refractory gate devices were less susceptible to degradation as a result of the hostile environment. Failure mechanisms were determined and correlated with the electrical degradation of the devices.     

Evidence of two distinct degradation mechanisms from temperature dependence of negative bias stressing of the ultrathin gate p-MOSFET

A detailed investigation of the negative-bias temperature instability (NBTI) of the ultrathin nitrided gate p-MOSFET over a wide temperature range reveals two different activation energies, indicating the coexistence of two distinct degradation mechanisms. One mechanism is linked to the incorporation of nitrogen while the other is the classical mechanism responsible for the degradation of conventional SiO/sub 2/ gate devices. Eliminating the contribution of the former consistently yields an Arrhenius plot that matches excellently with that obtained through direct measurement of SiO/sub 2/ gate devices. This finding shows that heavy nitridation or, in the extreme case, the adoption of Si/sub 3/N/sub 4//SiO/sub x/ gate stack does not change the nature of the classical NBTI mechanism but introduces a new degradation mechanism of an order-of-magnitude lower activation energy, which dominates over typical operating temperature range. This new mechanism is related to the spontaneous trapping of positive charges at nitrogen-related precursor sites near the Si-SiO/sub 2/ interface.     

Device reliability study of AlGaN/GaN high electron mobility transistors under high gate and channel electric fields via low frequency noise spectroscopy

A set of different short term stress conditions are applied to AlGaN/GaN high electron mobility transistors and changes in the electronic behaviour of the gate stack and channel region are investigated by simultaneous gate and drain current low frequency noise measurements. Permanent degradation of gate current noise is observed during high gate reverse bias stress which is linked to defect creation in the gate edges. In the channel region a permanent degradation of drain noise is observed after a relatively high drain voltage stress in the ON-state. This is attributed to an increase in the trap density at the AlGaN/GaN interface under the gated part of the channel. It was found that self-heating alone does not cause any permanent degradation to the channel or gate stack. OFF-state stress also does not affect the gate stack or the channel.     

Effect of high temperature annealing on tunnel oxide properties in TANOS devices

We investigate the effect of high temperature Post-Deposition Annealing of Al₂O₃ on the tunnel oxide of TANOS-like non-volatile memories. We found that, when temperature steps above 850 °C are applied after the stack deposition, a transition layer is forming by the intermixing of the Si₃N₄ with the upper part of the underneath SiO₂. We found that this transition layer has worse dielectric properties as compared to SiO₂, altering in a not-negligible way the performance of TANOS memories, and in particular severely penalizing retention.     

The impacts of control gate voltage on the cycling endurance ofsplit gate flash memory

In this paper, the “erase” degradation in program/erase (P/E) cycling endurance of split-gate flash memory has been investigated. It is found that increasing the control-gate (CG) voltage (V_CG) during erasing can slow down the “window closure” of cycling endurance since a higher V_CG can “push” the FG potential into gradual part of I_Read-out -V_FG curve and in turn reduce the read-out current degradation. Moreover, the experimental results show that scaling down the gate oxide thickness under FG can effectively reduce the I_Read-out degradation in the cycling endurance test     

A novel high performance adhesion enhancing Zn-Cr leadframe coatingfor popcorn prevention

A novel adhesion enhancing Zn-Cr (A2) leadframe coating has been reported to be a highly effective solution for popcorn prevention in plastic surface mount packages. In this paper, we report our recent understanding of the adhesion and degradation mechanisms of such a coating system. TEM and TOF-SIMS were employed to study the structure of A2-coating and the molding compound/leadframe (MC/LF) interface. The A2-coating was found to be a partially thin, crystalline layer comprised of a continuous interfacial layer and a network of whiskers. Zn silicate compound, ZnO and Cr oxide(s) were identified as possible phases present in the A2-coating. The adhesion enhancing and degradation mechanisms of the A2-coating were investigated by lead pull test to study the influence of temperature cycling, pressure cooker testing, moisture preconditioning, and leadframe oxidation. The adhesion data showed that the A2-enhanced MC/Cu LF interface is not susceptible to thermomechanical stress and moisture degradation. The wetting of the molding compound coupled with mechanical interlocking mechanism offered by the whiskers are believed to be key contributing factors of adhesion enhancement. Degradation of the A2-enhanced MC/Cu LF adhesion was observed after 100 min exposure at 300°C by Cu oxide formation from Cu outward diffusion through the A2-layer and was validated by AES analysis operated in the depth profiling mode. Lead pull test specimens were cleaved to have access to the MC/Cu LF interface for RBS analysis to identify the locus of failure     

Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics

P/sup +/-poly-Si gate MOS transistors with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics (EOT=2.50 nm) have been fabricated. Similar to the reference samples with SiO/sub 2/ gate dielectrics (T/sub ox/=2.45 nm), clear saturation characteristics of drain current are obtained for the samples with stack gate dielectrics. Identical hole-effective mobility is obtained for the samples with the SiO/sub 2/ and the stack gate dielectrics. The maximum value of hole-effective mobility is the same (54 cm/sup 2//Vs) both for the stack and the SiO/sub 2/ samples. Hot carrier-induced mobility degradation in transistors with the stack gate dielectrics was found to be identical to that in transistors with the SiO/sub 2/ gate dielectrics. In addition to the suppression of boron penetration, better TDDB characteristics, and soft breakdown free phenomena for the stack dielectrics (reported previously), the almost equal effective mobility (with respect to that of SiO/sub 2/ dielectrics) has ensured the proposed stack gate dielectrics to be very promising for sub-100-nm technology generations.     

Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance

The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.     

Failure mechanism of anisotropic conductive adhesive interconnections in flip chip ICs on flexible substrates

In this work we study how the endurance performance of electrically conductive adhesive interconnections of flip chip integrated circuits with a pitch of 200 and 150/spl mu/m on flexible substrates is affected by varying environmental conditions. This is accomplished by comparison of offline and online control measurements that are carried out to monitor the electrical resistance in temperature-humidity and temperature cycling stress tests. From the gradual degradation of the resistance with time and the failure analysis, it is conjectured that periodic absorption and desorption of moisture forms one of the more important failure mechanisms in this type of assembly.     

Quantification of cracked area in thermal path of high-power multi-chip modules using transient thermal impedance measurement

Transient thermal impedance measurement is commonly used to characterize the dynamic behaviour of the heat flow path in power semiconductor packages. This can be used to derive a “structure function” which is a graphical representation of the internal structure of the thermal stack. Changes in the structure function can thus be used as a non-destructive testing tool for detecting and locating defects in the thermal path. This paper evaluates the use of the structure function for testing the integrity of the thermal path in high power multi-chip modules. A 1.2 kV/200 A IGBT module is subjected to power cycling with a constant current. The structure function is used to estimate the level of disruption at the interface between the substrate and the baseplate/case. Comparison with estimations of cracked area obtained by scanning acoustic microscopy (SAM) imaging shows excellent agreement, demonstrating that the structure function can be used as a quantitative tool for estimating the level of degradation. Metallurgical cross-sectioning confirms that the degradation is due to fatigue cracking of the substrate mount-down solder.     

Application of coupled electro-thermal and physics-of-failure-based analysis to the design of accelerated life tests for power modules

In the reliability theme a central activity is to investigate, characterize and understand the contributory wear-out and overstress mechanisms to meet through-life reliability targets. For power modules, it is critical to understand the response of typical wear-out mechanisms, for example wire-bond lifting and solder degradation, to in-service environmental and load-induced thermal cycling. This paper presents the use of a reduced-order thermal model coupled with physics-of-failure-based life models to quantify the wear-out rates and life consumption for the dominant failure mechanisms under prospective in-service and qualification test conditions. When applied in the design of accelerated life and qualification tests it can be used to design tests that separate the failure mechanisms (e.g. wire-bond and substrate-solder) and provide predictions of conditions that yield a minimum elapsed test time. The combined approach provides a useful tool for reliability assessment and estimation of remaining useful life which can be used at the design stage or in-service. An example case study shows that it is possible to determine the actual power cycling frequency for which failure occurs in the shortest elapsed time. The results demonstrate that bond-wire degradation is the dominant failure mechanism for all power cycling conditions whereas substrate-solder failure dominates for externally applied (ambient or passive) thermal cycling.     

Mechanisms of metallization degradation in high power diodes

Under operation the topside metallization of power electronic chips is commonly observed to degrade and thereby affecta device's electrical characteristics. However, the mechanisms of the degradation process and the role of environmental factors are not yet fully understood. In this work, we investigate the metallization degradation by passive thermal cycling of unpackaged high-power diode chips in different controlled atmospheres. The electrical degradation of the metallization is characterized by sheet resistance measurements, while the microstructural damage is investigated by scanning electron microscopy (SEM) and X-ray diffraction (XRD). To study the evolution of the chemical composition of the metallization, energy dispersive X-ray spectroscopy (EDX) is also applied. Since the degradation depends on the initial microstructure of the metallization, the film texture and grain size distribution is determined using electron backscatter diffraction (EBSD). The obtained data show that the type of atmosphere plays a minor role in the degradation process, with a slight tendency that cycling in dry nitrogen atmosphere accelerates the degradation compared to the experiments in ambient atmosphere with a controlled relative humidity of 50 and 95%.     

Charge transport in high-κ stacks for charge-trapping memory applications: A modeling perspective (invited)

Charge trapping (CT) memories could be a promising technology option for further NAND Flash scaling. The assessment of the scalability limits and ultimate performances of this technology demands for the comprehensive understanding of the physical mechanisms governing device operation and reliability, which requires accurate physics-based models reproducing the electrical device characteristics. The basic features of the models presented in the literature for CT memory devices are reviewed, underlining their similarities and differences, and highlighting their importance in order to achieve a comprehensive understanding of the physical mechanisms responsible for CT device operation and reliability. A physical model describing the charge transport in nitride and high-κ stacks is also presented, which allows gaining further insights into reliability issues related to charge localization and high-κ tunnel and blocking dielectrics, like the effects of the blocking alumina layer and the band-gap engineered tunnel dielectrics on the TANOS device retention.     

CHC degradation of strained devices based on SiON and high-k gate dielectric materials

A comparison between the Channel Hot-Carrier (CHC) degradation on strained pMOSFETs with SiGe source/drain (S/D) based on different gate dielectric materials, as SiON or HfSiON, has been done. The influence of the device channel orientation, channel length and temperature on the CHC damage has been studied.     

1/f Noise in conductive adhesive bonds under mechanical stress as a sensitive and fast diagnostic tool for reliability assessment

Classical lifetime predictions of conductive adhesive bonds require time consuming thermal cycling measurements. Therefore, faster lifetime test are needed with more detailed information about degradation mechanisms. This paper reports on the low frequency noise of such contacts. Our results show that the evolution of 1/f noise in contacts is a fast and non-destructive diagnostic tool for reliability testing. The 1/f noise of the contact resistance can be interpreted within an existing contact noise model in terms of a multispot contact behaviour. In comparison to classical reliability tests, 1/f noise measurements reveal more detailed information about reduction in the real electrical contact area and are much faster and are non-destructive.