Improved device variability in scaled MOSFETs with deeply retrograde channel profile

Continued scaling of transistor has resulted in severe short channel effects and transport degradation. In addition, variability in deeply scaled transistor such as threshold voltage (V_TH) variability has emerged as a major challenge for circuit and device design. Although various techniques have been suggested to alleviate these problems, such as CMOS on FDSOI or 3D transistors, they are expensive and complicated to manufacture. Recently, MOSFETs with deeply retrograde channel profile have been suggested as a mean to obtain good device characteristics on bulk substrate. In this work, V_TH variability impact of RDF on 65 nm-node deeply retrograde MOSFETs and conventional planar bulk MOSFETs were studied by using TCAD simulation. The simulated results showed that the deeply retrograde MOSFETs have 5 mV lower σ-V_TH (ΔA_VT between two devices is 1.06  mV·μm) than conventional planar bulk MOSFETs at the same I_off level (0.2 nA/μm). The ideal BOX profile structure simulated results showed that the thinner the low doping surface layer for deeply retrograde MOSFETs, the higher the V_TH variability. Our finding suggest that deeply retrograde MOSFETs are inherently less sensitive to V_TH variability due to RDF and channel length than conventional planar bulk MOSFETs and can be feasible for post-CMOS technology.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

Soft UV-NIL at 20 nm scale using flexible bi-layer stamp casted on HSQ master mold

In this paper we present a comparative study of two e-Beam Lithography (EBL) processes for Nanoimprinting Lithography (NIL) master mold, i.e. the standard PMMA based EBL Si patterning process and the HSQ process. 20 nm features with minimal sidewall roughness and high uniformity are demonstrated on large surface by using HSQ process. Moreover, to validate this ultra-high resolution HSQ EBL process and to check NIL resolution performances, soft UV-NIL replications were performed using soft hard-PDMS/PDMS bi-layer stamps casted on the HSQ master mold. We demonstrate the replication of sub-20 nm nanodots of high density (pitch 60 nm) with a good uniformity on the whole field area.     

Study of the behaviour of monomers in thermal nanoimprint lithography

Thermoplastics are commonly used in thermal nanoimprint lithography (NIL) but their high viscosity leads to inhomogeneities of residual thickness in patterns with various densities. Monomers exhibit low viscosity and are imprinted easily and polymerized with UV–NIL processes. These monomers can be also used for thermal NIL. We have imprinted A-POSS material which is spontaneously polymerized at 170 °C. The inorganic part of this monomer is interesting for pattern transfer and for permanent applications. Thermal properties of this molecule are presented in this paper. It is shown that polymerization occurs at 170 °C, and that the viscosity is 1330 mPa s at ambient temperature. Imprint experiments have demonstrated that A-POSS flows over larger surfaces during imprint step, compared to thermoplastics. Patterns with different densities have been studied and different filling regimes have been observed depending on material viscosity. They are induced by a competition between material flow and mold deformation. Finally, we imprinted some nanoelectrodes simultaneously with millimetric large connection pads, and it was demonstrated that complete filling was obtained with monomers whereas this was not possible with thermoplastics.     

A 2D compact model for lightly doped DG MOSFETs (P-DGFETs) including negative bias temperature instability (NBTI) and short channel effects (SCEs)

In this paper, a 2D compact model for potential and threshold voltage for lightly doped symmetrical double gate (DG) p-channel MOSFETs (PMOS) including negative bias temperature instability (NBTI) and short channel effects (SCEs) is presented. The model is dedicated to nano scale MOSFETs below 30 nm. In this model, both effects of interface state generation and hole-trapping are considered. Moreover, the effects of scaling down the oxide thickness and the channel thickness on NBTI are discussed. Our model is matched very well with numerical simulations obtained from COMSOL multi-physics at different drain voltages (V_d). A 4% shift in threshold voltage roll-off and 47% shift in drain induced barrier lowering (DIBL) is achieved at a gate length of 10 nm after 10 years of operation at a frequency of 1 GHz.     

Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications

The outstanding electron transport properties of InGaAs and InAs semiconductor materials, makes them attractive candidates for future nano-scale CMOS. In this paper, the ON state and OFF state performance of 30 nm gate length InGaAs/InAs/InGaAs buried composite channel MOSFETs using various high-K dielectric materials is analyzed using Synopsys TCAD tool. The device features a composite channel to enhance the mobility, an InP spacer layer to minimize the defect density and a heavily doped multilayer cap. The simulation results show that MOSFETs with Al₂O₃/ZrO₂ bilayer gate oxide exhibits higher gm/I_D ratio and lower sub threshold swing than with the other dielectric materials. The measured values of threshold voltage (V_T), on resistance (R_ON) and DIBL for Lg = 30 nm In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As composite channel MOSFET having Al₂O₃/ZrO₂ (EOT = 1.2 nm) bilayer dielectric as gate oxide are 0.17 V, 290 Ω-µm, and 65 mV/V respectively. The device displays a transconductance of 2 mS/µm.     

Isotropic wet chemical etching of deep channels with optical surface quality in silicon with HNA based etching solutions

Online trace analysis based on UV/Vis spectroscopy requires long detection paths. Therefore an isotropic wet etch process in silicon is developed to fabricate a 300 µm deep channel with low channel wall roughness for desired light guidance application. Four etchant compositions were compared in terms of etching rate, surface roughness and selectivity in a beaker process. The best fitting mixture was selected. To further increase the surface quality (bubble issue) a spin etcher tool is used for producing the channels. The dependence of homogeneity and defect density on media flux, and rotation velocity was investigated. Results show that high rotation velocity and high media flux lead to great defects in the channel wall. Through rotation of the wafer during etching, the etching rate of silicon rises compared to the beaker process due to the rapid removal of etch products and simultaneous supply of fresh etchant. After 38 min of etching, 300 µm deep semi-circular channels with high optical quality (Rq=10 nm±2 nm) over 3 m were produced.     

Comprehensive effects of strained Ge1−xSnx and device layout arrangement on a nano-scale Ge-based PMOSFET with a short channel

Layout patterns, including salient gate width and dummy active diffusion region (dummy OD), significantly influence the carrier mobility gain of nano scale devices. Germanium (Ge)-based devices with Ge–tin (GeSn) alloy embedded in the source/drain (S/D) regions have been regarded a promising candidate for higher channel mobility. Second-order piezoresistance coefficients were used to estimate the carrier mobility gain within the desired Ge-based device channel. A 20 nm Ge-based p-type metal oxide semiconductor field effect transistor with 100 nm gate width and 100 nm dummy OD width was selected to explore the layout effect of the short channel device. The device consisted of S/D region Ge_1−xSn_x alloy, compressive-stressed contact etch stop layer, and deposited shallow trench isolation with different process-induced stress magnitudes. Maximum carrier mobility gain of 93.65% was obtained when a 10 nm narrow distance between OD and dummy OD was achieved.     

Reduced contact resistance and highly stable operation in polymer thin-film transistor with aqueous MoOx solution contact treatment

We report on a newly developed solution process using MoO₃ for reducing source and drain (S/D) electrodes in organic thin-film transistor (TFT). By taking advantage of the difference in surface wettability between the gate dielectric layer and the S/D electrodes, the electrode treatment using the MoO_x solution was applied to polymer TFT with short channel lengths less than 10 μm. The contact resistance was noticeably reduced at the interface of the S/D electrodes in a polymer TFT using a pBTTT-C16. Furthermore, the field effect mobility for this TFT was enhanced from 0.03 to 0.1 cm²/V s. Most notably, the threshold voltage (V_th) shift under gated bias stress was less than 0.2 V after 10⁵ s, which is comparable to that of conventional poly crystalline Si TFT.     

Characterization of P-channel power trench MOSFETs with polycrystalline silicon germanium gate electrode for faster switching

Electrical switching characteristics using polycrystalline silicon–germanium (poly-Si_l?xGe_x) gate for P-channel power trench MOSFETs was investigated. Switching time reduction of over 22% was observed when the boron-doped poly-Si gate was replaced with a similarly boron-doped poly-SiGe gate on the P-channel power MOSFETs. The fall time (T_f) on MOSFETs with poly-SiGe gate, was found to be ～11 ns lesser than the poly-Si gate MOSFET which is ～60% improvement in switching performance. However, all the switching improvement was observed during the fall times (T_f). The reason could be the higher series resistance in the switching test circuit masking any reduction in the rise times (T_r). Faster switching is achieved due to a lower gate resistance (R_g) offered by the poly-SiGe gate electrode as compared to poly-silicon (pSi) material. The pSi gate resistance was found to be 6.25 Ω compared to 3.75 Ω on the poly-SiGe gate measured on the same device. Lower gate resistance (R_g) also means less power is lost during switching thereby less heat is generated in the device. A very uniform boron doping profile was achieved with-in the pSiGe gate electrode, which is critical for uniform die turn on and better thermal response for the power trench MOSFET. pSiGe thin film optimization, properties and device characteristics are discussed in details in the following sections.     

Growth of a Ge layer on 8 in. Si (100) substrates by rapid thermal chemical vapor deposition

We have made the successful growth of Ge layer on 8 in. Si (100) substrates by rapid thermal chemical vapor deposition (RTCVD). In order to overcome the large lattice mismatch between Ge and Si, we used a two-step growth method. Our method shows the uniformity of the thickness and good quality Ge layer with a homogeneous distribution of tensile strain and a lower etch pit density (EPD) in order of 10⁵ cm⁻². The surface morphology is very smooth and the root mean square (RMS) of the surface roughness was 0.27 nm. The photocurrent spectra were dominated by the Ge layer related transition that corresponding to the transitions of the Si and Ge. The roll-off in photocurrent spectra beyond 1600 nm is expected due to the decreased absorption of Ge.     

Nanoimprint with thin and uniform residual layer for various pattern densities

Pattern density variation is uncomfortable for nanoimprint lithography which uses a moldable material supplied as a thin film, because the variation of pattern density causes variations of residual layer thickness reflecting on the local pattern density. To solve the problem, a new type of mold “capacity-equalized mold”, which has constant averaged depth regardless of pattern density, was fabricated and the structure of the mold was inspected. UV nanoimprint was then carried out using the mold and thickness and uniformity of the residual layer were investigated. An average thickness of 33.2 nm with a standard deviation of 3.4 nm was obtained for the mold pattern layout with a pattern density of from 0.25 to 0.75. It was found that a standard deviation of 1.2 nm was achieved for pattern density variation of from 0.33 to 0.67 by excluding artifacts.     

Effects of the post nitridation anneal temperature on performances of the nano MOSFET with ultra-thin (<2.5 nm) plasma nitrided gate dielectric

A post nitridation annealing (PNA) is used to improve performances of the metal oxide semiconductor field effect transistor (MOSFETs) with nano scale channel and pulsed radio frequency decoupled plasma nitrided ultra-thin (<50 Å) gate dielectric. Effects of the PNA temperature on the gate leakage and the device performances are investigated in details. For a n-type MOSFET, as the PNA temperature rises from 1000 to 1050 °C, the saturation current and gate leakage are increased and reduced 7.9% and 3.81%, respectively. For a p-type MOSFET, the improvement is more significant i.e., 16.7% and 4.31% in saturation current increase and gate leakage reduction, respectively. The significant improvements in performance are attributed to the higher PNA temperature caused Si/SiON interface improvement and increase of EOT. Most of all, the high temperature PNA does not degrade the gate oxide integrity.     

mr-NIL 6000LT – Epoxy-based curing resist for combined thermal and UV nanoimprint lithography below 50 °C

The aim of the work presented here was to develop curing polymers for nanoimprint lithography (NIL) enabling short cycle time, low imprint temperature, and an isothermal imprint process. The result is mr-NIL 6000LT: A photochemically curing polymer system for isothermal imprinting by combined thermal and UV nanoimprint lithography. It allows a lower imprint temperature than materials presented previously [C. Schuster, M. Kubenz, F. Reuther, M. Fink, G. Grützner, mr-NIL 6000 – New epoxy-based curing resist for efficient processing in combined thermal and UV nanoimprint lithography, in: Proceedings of SPIE 6517 2007, 65172B.; D.W. Johnson, H. Miller, M. Kubenz, F. Reuther, G. Grützner, Nanoimprinting with SU-8 Epoxy Resists, in: Proceedings of SPIE 6517 2007, 65172A.].The material system chosen is based on a blend of epoxy resins and a photo acid generator. Such epoxy resists cure during the imprint step in combined thermal and UV nanoimprint lithography. Initiated by UV exposure the cationic polymerisation occurs at elevated temperature forming a polymer pattern with significantly increased thermal stability compared to the uncured system.Apart from the material development leading to mr-NIL 6000LT the correlations between the parameters imprint temperature, exposure time and post exposure hold time are investigated in this work. With the applied resin combination a T_g of ?15 °C is obtained. This enables the formation of solid films at room temperature after spin-coating and prebake and nevertheless imprint temperatures in the range of 45–50 °C, which is a distinct decrease compared to the 100–110 °C needed for the previously introduced mr-NIL 6000 [C. Schuster, M. Kubenz, F. Reuther, M. Fink, G. Grützner, mr-NIL 6000 – New epoxy-based curing resist for efficient processing in combined thermal and UV nanoimprint lithography, in: Proceedings of SPIE 6517 2007, 65172B.] or the 65–70 °C necessary for defect-free imprinting of the epoxy-based polymer described in [D.W. Johnson, H. Miller, M. Kubenz, F. Reuther, G. Grützner, Nanoimprinting with SU-8 Epoxy Resists, in: Proceedings of SPIE 6517 2007, 65172A.]. mr-NIL 6000LT exhibits good dimensional stability at 120 °C after curing during the imprint process. This is sufficient for an isothermal imprint process as well as subsequent processes, e.g. metallization or etching.     

The influence of junction depth on short channel effects in vertical sidewall MOSFETs

This work addresses a fundamental problem of vertical MOSFETs, that is, inherently deep junctions that exacerbate short channel effects (SCEs). Due to the unconventional asymmetric junction depths in vertical MOSFETs, it is necessary to look separately at the electrostatic influence of each junction. In order to suppress short channel effects better, we explore the formation of a shallow drain junction. This is realized by a self-aligned oxide region, or junction stop (JS) which is formed at the pillar top and acts as a diffusion barrier for shallow junction formation. The benefits of using a JS structure in vertical MOSFETs are demonstrated by simulations which show clearly the effect of asymmetric junctions on SCEs and bulk punch-through. A critical point is identified, where control of SCEs by junction depth is lost and this leads to appropriate junction design in JS vertical sidewall MOSFETs. For a 70 nm channel length the JS structure improves charge sharing by 54 mV and DIBL by 46 mV. For body dopings of 5.0 × 10¹⁷ cm^?3 and 6.0 × 10¹⁷ cm^?3 the JS gives improvements in I_off of 58.7% and 37.8%, respectively, for a given I_on. The inclusion of a retrograde channel gives a further increase in I_on of 586 μA/μm for a body doping of 4.0 × 10¹⁸ cm^?3.     

Simulation and fabrication of HF microelectromechanical bandpass filter

A high-frequency (HF) micromechanical bandpass filter fabricated using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and the post-process has been investigated in this study. The area of the filter is about 150×200 μm². The filter is composed of two resonators, which are joined by a coupling beam. Each resonator contains a membrane, four supported beams and two fixed electrodes, and the membrane is supported by four supported beams. The filter requires a post-process to etch the sacrificial layer, and to release the suspended structures. The post-process needs only one wet etching to etch silicon dioxide layer. The filter contains a sensing part and a driving part. When applying a driving voltage to the driving part, the sensing part generates a change in capacitance. The capacitance variation of the sensing part is converted into the output voltage by a sensing circuitry. Experiments show that the filter has a center frequency of about 39.6 MHz and a bandwidth of 330 kHz.     

High dielectric constant TiO2 film grown on polysilicon by liquid phase deposition

In this study, titanium dioxide (TiO₂) films were grown on polycrystalline silicon by liquid phase deposition (LPD) with ammonium hexafluoro-titanate and boric acid as sources. The film structure is amorphous as examined by X-ray diffraction (XRD). A uniform composition of LPD-TiO₂ was observed by SIMS examination. The leakage current density of an Al/LPD-TiO₂/poly-Si/p-type Si metal–oxide–semiconductor (MOS) structure is 1.9 A/cm² at the negative electric field of 0.7 MV/cm. The dielectric constant is 29.5 after O₂ annealing at 450 °C. The leakage current densities can be improved effectively with a thermal oxidized SiO₂ added at the interface of LPD-TiO₂/poly-Si. The leakage current density can reach 3.1×10⁻⁴ A/cm² at the negative electric field of 0.7 MV/cm and the dielectric constant is 9.8.     

Fabrication of a conductive nanoscale electrode for functional devices using nanoimprint lithography with printable metallic nanoink

This paper proposes two metal patterning processes. In each process, nanoimprint lithography (NIL) is used with commercialized particle-based silver nanoink which has appropriate properties for NIL. One process is a direct NIL process with a polydimethylsiloxane (PDMS) stamp; the other is a combined NIL and lift-off process. The direct NIL process is executed by using a xylene-absorbed PDMS stamp to decrease the curing time and minimize the residuals. A flexible PDMS stamp can also be wrapped around a quartz cylinder and used as a roll stamp to enlarge the patterned area. The direct NIL process successfully produced silver line patterns in the range of 200–300 nm, and the combined NIL and lift-off process successfully produced silver line patterns in the range of 15–60 nm.     

Effects of post-lift-off annealing conditions on contact oxidation of Ti–Au top-contacts in In-Sn–Zn–O TFT

Thin film transistors (TFT) with an indium based mixed oxide semiconductor are investigated for titanium–gold top-contacts. It is noticed that upon post annealing, in order to remove chemical residuals from top-contact lift-off steps, oxidation of titanium occurs depending on the annealing conditions. Mobility of the TFT is strongly affected by contact oxidation arising from this post lift-off annealing process. Oxidation of the top-contact is facilitated by adsorbed surface oxygen or out-diffusing oxygen from the semiconductor depending on the post lift-off annealing conditions. A passivation layer that binds effectively to surface vacancies and removes adsorbed oxygen species from the semiconductor surface is demonstrated. The combinations of this passivation layer with relatively low temperature and short post lift-off annealing in an oxygen deficient environment result in significantly reduced contact oxidation and subsequently better transistor performance. Contact resistance as low as 90 Ω cm and mobility as high as 5.3 cm²/V s are obtained for solution processed mixed metal oxide semiconductor in top-contact geometry.     

Interaction influence of S/D GeSi lattice mismatch and stress gradient of CESL on nano-scaled strained nMOSFETs

The intrinsic stress of thin films has become an important resource as advanced strain engineering is introduced into nanoscaled semiconductor devices. The performance of preferred device infrastructure can be studied by estimating stress-induced mobility gain. However, traditional simulation approaches for device stress typically do not consider the eventual consequence of the stress gradient of strained thin films on nanoscaled transistor stress prediction. Thus, the actual operating characteristic of concerned devices can be easily misunderstood. To resolve this issue, this research presents a fabrication-oriented simulation methodology for device stress and combines it with a multi-layered deposition model for thin film. This study aims to explore stress-induced effects on the performance of a Ge-based testing vehicle for 20 nm n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) with Ge_1−xSi_x alloys embedded into the source/drain regions of the device. Intrinsic stress is introduced via a 1.0 GPa tensile contact etch stop layer (CESL). Analysis results indicate that stress contours adjacent to the top of the device gate are different from those obtained using the conventional simulation method. Moreover, greater CESL stress passes through the spacer and reaches the device channel. Furthermore, a relationship between the stress components and piezoresistivity coefficients of the Ge material is adopted to estimate the width dependence of the Ge-based nMOSFET on its mobility gain. A maximum mobility gain of up to 60.87% is acquired from the estimated results, and a channel width of 200 nm is preserved.