A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

A multiplying delay-locked loop (MDLL) for high-speed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described. The MDLL design removes such drawbacks while maintaining the advantages of a PLL for multirate frequency multiplication. This design also uses a supply regulator and filter to further reduce on-chip jitter generation. The MDLL, implemented in 0.18-/spl mu/m CMOS technology, occupies a total active area of 0.05 mm/sup 2/ and has a speed range of 200 MHz to 2 GHz with selectable multiplication ratios of M=4, 5, 8, 10. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8-V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier integrated on a single chip for a 72/spl times/72 STS-1 grooming switch and has a jitter of 1.73 ps (rms) and 13.1 ps (pk-pk).     

Baseband and audio mixed-signal front-end IC for GSM/EDGE applications

A complete mixed-signal front-end CMOS chip is presented, supporting GSM/EDGE as well as enhanced audio applications. The chosen solution for the transmit section is based on Laurent's approximation of the nonlinear GMSK modulator. This enables burst shaping in the I/Q domain thereby solving the problem of power ramping. Also, up to GPRS class 12 is supported. The receive section on the other hand consists of a low power dual mode continuous-time /spl Sigma//spl Delta/ ADC for I and Q, supporting ZIF and LIF modes of operation and achieving typically 12.5 bit of resolution under production conditions. An on-chip PLL, which supplies all blocks with various clock frequencies, additionally supports clock jitter suppression. The audio section comprises a codec supporting standard formats such as IIS and PCM. It features mono/stereo signaling from various sources in 16bit quality as well as high-drive buffers for 4 /spl Omega/ single-ended loads (capacitively coupled). The whole chip is powered from a 1.5/2.65 V supply voltage and consumes 22 mW in paging mode.     

A 4160-bit C4D serial memory

A 4160-bit serial memory chip has been designed, fabricated, and tested using as the basic memory cell the conductively connected charge-coupled device (CCD) or C4D. The chip includes an inverting regenerator every 65 bits and a reading tap every 130 bits. Also on-chip is a recirculating amplifier which senses the charge packet as it reaches the end of the register and feeds it back to the input. This means that once data has been written onto the chip, it will be retained as long as the regenerator supply and the two clocks are on. The chip has two multiplexed halves to obtain a data rate of twice the clock frequency. The active area of the chip is 12 mm/SUP 2/ or 2900 /spl mu/m/SUP 2/ per bit. Operation was obtained for arbitrary data streams at clock rates of 1 kHz to 1.6 MHz (3.2 MHz data rate). Power dissipation varies linearly with frequency and is 16 /spl mu/W per bit at the highest frequency. Maximum read latency is 80 /spl mu/s at this frequency. This performance demonstrates the feasibility of the C4D as a component for a medium speed large-scale memory.     

A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology

The design of a low-voltage 40-GHz complementary voltage-controlled oscillator (VCO) with 15% frequency tuning range fabricated in 0.13-/spl mu/m partially depleted silicon-on-insulator (SOI) CMOS technology is reported. Technological advantages of SOI over bulk CMOS are demonstrated, and the accumulation MOS (AMOS) varactor limitations on frequency tuning range are addressed. At 1.5-V supply, the VCO core and each output buffer consumes 11.25 mW and 3 mW of power, respectively. The measured phase noise at 40-GHz is -109.73 dBc/Hz at 4-MHz offset from the carrier, and the output power is -8 dBm. VCO performance using high resistivity substrate (/spl sim/300-/spl Omega//spl middot/cm) has the same frequency tuning range but 2 dB better phase noise compared with using low resistivity substrate (10 /spl Omega//spl middot/cm). The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m (excluding pads).     

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.     

A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN

A single-chip dual-band 5.15-5.35-GHz and 2.4-2.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. It utilizes an innovative architecture including feedback paths that enable digital calibration to help eliminate analog circuit imperfections such as transmit and receive I/Q mismatch. The dual-band receive paths feature a 4.8-dB (3.5-dB) noise figure at 5.25 GHz (2.45 GHz). The corresponding sensitivity at 54 Mb/s operation is -76 dBm for 802.11a and -77 dBm for 802.11g, both referred at the input of the chip. The transmit chain achieves output 1-dB compression at 6 dBm (9 dBm) at 5 GHz (2.4 GHz) operation. Digital calibration helps achieve an error vector magnitude (EVM) of -33 dB (-31 dB) at 5 GHz (2.4 GHz) while transmitting -4 dBm at 54Mb/s. The die size is 19.3 mm/sup 2/ and the power consumption is 260 mW for the receiver and 320 mW (270 mW) for the transmitter at 5 GHz (2.4 GHz) operation.     

A single-chip programmable platform based on a multithreaded processor and configurable logic clusters

This paper presents a single-chip programmable platform that integrates most of hardware blocks required in the design of embedded system chips. The platform includes a 32-bit multithreaded RISC processor (MT-RISC), configurable logic clusters (CLCs), programmable first-in-first-out (FIFO) memories, control circuitry, and on-chip memories. For rapid thread switch, a multithreaded processor equipped with a hardware thread scheduling unit is adopted, and configurable logics are grouped into clusters for IP-based design. By integrating both the multithreaded processor and the configurable logic on a single chip, high-level language-based designs can be easily accommodated by performing the complex and concurrent functions of a target chip on the multithreaded processor and implementing the external interface functions into the configurable logic clusters. A 64-mm/sup 2/ prototype chip integrating a four-threaded MT-RISC, three CLCs, programmable FIFOs, and 8-kB on-chip memories is fabricated in a 0.35-/spl mu/m CMOS technology with four metal layers, which operates at 100-MHz clock frequency and consumes 370 mW at 3.3-V power supply.     

Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits

This paper introduces floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies. The shield minimizes losses without requiring an explicit on-chip ground connection. Experimental measurements demonstrate Q-factor ranging from 25 to 35 between 15 and 40 GHz for shielded coplanar waveguide fabricated on 10 /spl Omega//spl middot/cm silicon. This is more than a factor of 2 improvement over conventional on-chip transmission lines (e.g., microstrip, CPW). A floating-shielded, differentially driven 7.4-nH inductor demonstrates a peak Q of 32, which is 35% higher than an unshielded example. Similar results are realizable for on-chip transformers. Floating-shielded bond-pads with 15% less parasitic capacitance and over 60% higher shunt equivalent resistance compared to conventional shielded bondpads are also described. Implementation of floating shields is compatible with current and projected design constraints for production deep-submicron silicon technologies without process modifications. Application examples of floating-shielded passives implemented in a 0.18-/spl mu/m SiGe-BiCMOS are presented, including a 21-26-GHz power amplifier with 23-dBm output at 20% PAE (at 22 GHz), and a 17-GHz WLAN image-reject receiver MMIC which dissipates less than 65 mW from a 2-V supply.     

A low-power 2.4-GHz transmitter/receiver CMOS IC

A 2.4-GHz CMOS receiver/transmitter incorporates circuit stacking and noninvasive baseband filtering to achieve a high sensitivity with low power dissipation. Using a single 1.6-GHz local oscillator, the transceiver employs two upconversion and downconversion stages while providing on-chip image rejection filtering. Realized in a 0.25-/spl mu/m digital CMOS technology, the receiver exhibits a noise figure of 6 dB and consumes 17.5 mW from a 2.5-V supply, and the transmitter delivers an output power of 0 dBm with a power consumption of 16 mW.     

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.     

Packet-switched on-chip interconnection network for system-on-chip applications

Increasing complexity of a system-on-chip design demands efficient on-chip interconnection architecture such as on-chip network to overcome limitations of bus architecture. In this brief, we propose a packet-switched on-chip interconnection network architecture, through which multiple processing units of different clock frequencies can communicate with each other without global synchronization. The architecture is analyzed in terms of area and energy consumption, and implementation issues on building blocks are addressed for cost-effective design. A test chip is implemented using 0.38-/spl mu/m CMOS technology, and measured its operation at 800 MHz to demonstrate its feasibility.     

A high-speed, 240-frames/s, 4.1-Mpixel CMOS sensor

This paper describes a large-format 4-Mpixel (2352/spl times/1728) sensor with on-chip parallel 10-b analog-to-digital converters (ADCs). The chip size is 20/spl times/20 mm with a 7-/spl mu/m pixel pitch. At a 66-MHz master clock rate and 3.3-V operating voltage, it achieves a high frame rate of 240 frames/s delivering 9.75 Gb/s of data with power dissipation of less than 700 mW. The principal architectural features of the sensor are discussed along with the results of sensor characterization.     

CMOS/SOS frequency synthesizer LSI circuit for spread spectrum communications

Using a 3.5-/spl mu/m gate length complementary metal-oxide-semiconductor/silicon-on-sapphire technology, a single-chip, radiation-hardened, direct digital frequency synthesizer has been developed. The circuit is a critical component of a fast-tuning wideband frequency synthesizer for spread spectrum satellite communications. During each clock period the chip generates a new digitized sample of a sine wave, whose frequency is variable in 2/SUP 20/ steps from DC to one-half the clock frequency. Operation at up to 7.5 MHz is possible in a worst-case environment, including ionizing radiation levels up to 3/spl times/10/SUP 5/ rads(Si). A computationally efficient algorithm was chosen, resulting in 12-bit output precision with only 1084 logic gates and 3840 bits of on-chip read-only memory. The accuracy of the algorithm is sufficient to maintain in-band spurious frequency components below -65 dBc. At 300 mW, the chip replaces an MSI implementation which uses 25 integrated circuits and consumes 3.5 W.     

A single-path pulsewidth control loop with a built-in delay-locked loop

A 1-1.27-GHz single-path pulse width control loop with a built-in delay-locked loop is presented. Based on the proposed circuit, not only can the 50% duty cycle of the output clock be assured but the phase alignment between the reference and output clocks can also be achieved. Moreover, the requirement of the reference clock with 50% duty cycle can be eliminated. By the single-to-complementary circuit and the switched charge pump, the duty cycle error can be reduced. Moreover, the duty cycle of the output clock can be adjusted for applications such as time-interleaved analog-to-digital converters, switched-capacitor circuits, and dc-dc converters. The proposed circuit has been fabricated in a 0.35-/spl mu/m CMOS process. The power consumption is 150 mW and the die area of the core circuit is 0.47/spl times/0.3 mm/sup 2/. The duty cycle of the output clock can be adjusted from 35% to 70% in steps of 5%.     

A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration

The design of a 600-MS/s 5-bit analog-to-digital (A/D) converter for serial-link receivers has been investigated. The A/D converter uses a closed-loop pipeline architecture. The input capacitance is only 170 fF, making it suitable for interleaving. To maintain low power consumption and increase the sampling rate beyond the amplifier settling limit, the paper proposes a calibration technique that digitally adjusts the reference voltage of each pipeline stage. Differential input swing is 400 mV/sub p-p/ at 1.8-V supply. Measured performance includes 25.6 dB and 19 dB of SNDR for 0.3-GHz and 2.4-GHz input frequencies at 600 MS/s for the calibrated A/D converter. The suggested calibration method improves SNDR by 4.4 dB at 600 MS/s with /spl plusmn/0.35 LSB of DNL and /spl plusmn/0.15 LSB of INL. The 180 /spl times/ 1500 /spl mu/m/sup 2/ chip is fabricated in a 0.18-/spl mu/m standard CMOS technology and consumes 70 mW of power at 600 MS/s.     

A 1.6-GHz CMOS PLL with on-chip loop filter

A 1.6-GHz phase locked loop (PLL) has been fabricated in a 0.6-μm CMOS technology. The PLL consists of an LC-tank circuit, divider, phase detector with charge pump, and an on-chip passive loop filter. When the oscillator is open loop, it exhibits -115 dBc/Hz phase noise at a 600-kHz offset from the carrier. The PLL occupies an active area of 1.6 mm² and dissipates 90 mW from a single 3-V supply     

A pipelined 5-Msample/s 9-bit analog-to-digital converter

A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology. It requires 8500 mil/SUP 2/, consumes 180 mW, and has an input capacitance of 3 pF. A fully differential architecture is used; only a two-phase nonoverlapping clock is required, and an on-chip sample-and-hold amplifier is included.     

A 20-Gb/s 0.13-/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer

A 20-Gb/s transmitter is implemented in 0.13-/spl mu/m CMOS technology. An on-die 10-GHz LC oscillator phase-locked loop (PLL) creates two sinusoidal 10-GHz complementary clock phases as well as eight 2.5-GHz interleaved feedback divider clock phases. After a 2/sup 20/-1 pseudorandom bit sequence generator (PRBS) creates eight 2.5-Gb/s data streams, the eight 2.5-GHz interleaved clocks 4:1 multiplex the eight 2.5-Gb/s data streams to two 10-Gb/s data streams. 10-GHz analog sample-and-hold circuits retime the two 10-Gb/s data streams to be in phase with the 10-GHz complementary clocks. Two-tap equalization of the 10-Gb/s data streams compensate for bandwidth rolloff of the 10-Gb/s data outputs at the 10-GHz analog latches. A final 20-Gb/s 2:1 output multiplexer, clocked by the complementary 10-GHz clock phases, creates 20-Gb/s data from the two retimed 10-Gb/s data streams. The LC-VCO is integrated with the output multiplexer and analog latches, resonating the load and eliminating the need for clock buffers, reducing power supply induced jitter and static phase mismatch. Power, active die area, and jitter (rms/pk-pk) are 165 mW, 650 /spl mu/m/spl times/350 /spl mu/m, and 2.37 ps/15 ps, respectively.     

A 2.4-GHz RF sampling receiver front-end in 0.18-/spl mu/m CMOS

This paper presents an integrable RF sampling receiver front-end architecture, based on a switched-capacitor (SC) RF sampling downconversion (RFSD) filter, for WLAN applications in a 2.4-GHz band. The RFSD filter test chip is fabricated in a 0.18-/spl mu/m CMOS technology and the measurement results show a successful realization of RF sampling, quadrature downconversion, tunable anti-alias filtering, downconversion to baseband, and decimation of the sampling rate. By changing the input sampling rate, the RFSD filter can be tuned to different RF channels. A maximum input sampling rate of 1072 MS/s has been achieved. A single-phase clock is used for the quadrature downconversion and the bandpass operation is realized by a 23-tap FIR filter. The RFSD filter has an IIP/sub 3/ of +5.5 dBm, a gain of -1 dB, and more than 17 dB rejection of alias bands. The measured image rejection is 59 dB and the sampling clock jitter is 0.64 ps. The test chip consumes 47 mW in the analog part and 40 mW in the digital part. It occupies an area of 1 mm/sup 2/.     

MSI High-Speed Low-Power GaAs Integrated Circuits Using Schottky Diode FET Logic

A new planar high-density (10/sup -3/ mm/sup 2//gate) GaAs IC technology has been used for fabricating MSI digital circuits containing up to 75 gates/chip. These digital circuits have potential application for gigabit microwave data transmission and processor systems. The circuits consist of Schottky diode FET logic NOR gates, which have provided propagation delays in the 75-200-ps range with dynamic switching energies as low as 27 fJ/gate on ring oscillator structures. Power dissipation levels are compatible with future LSI/VLSI extensions. Operation of D flip-flops (DFF) as binary ripple dividers (/spl divide/2-/spl divide/8) was achieved at 1.9-GHz clock rates, and an 8:1 full-data multiplexer and 1:8 data demultiplexer were demonstrated at 1.1-GHz clock rates. This corresponds to equivalent propagation delays in the 100-175-ps range for these MSI circuits. Finally, a 3x3 parallel multiplier containing 75 gates functioned with a propagation delay of 172 ps/gate and with average gate power dissipations of as low as 0.42 mW/gate.