Frequency Tolerances and Spurious Emission Limitations

Appendices 7 and 8 of the WARC-79 Final Acts contain, respectively, the Table of Transmitter Frequency Tolerances and the Table of Maximum Permitted Spurious Emission Power Levels. Decisions taken at that Conference on these two new Tables will eventually touch transmitter manufacturers and users everywhere. Frequency tolerances in most bands are tightened for new equipment effective January 2, 1985. TV broadcast for system M (NTSC) from 29.7 to 2450 MHz and broadcasting in the 535 to 1606.5-kHz bands remain the same. Earth and space services were introduced in the Table for the first time with impact from 4 MHz on up to 40 GHz after 1985. Relatively tight frequency tolerances are those for HF broadcasting, single sideband (SSB), and pulse modulation above 10 GHz. Peak envelope power rather than mean power is shown generally for SSB transmitters limits. The frequency tolerance limits, again, did not reach beyond 40 GHz. New spurious emission limits come into effect on that same date for new transmitters operating between 235 MHz and 17.7 GHz, although radiodetermination and emergencytype transmitters are excluded. There is also a special exception for spurious emissions of transmitters operating above 235 MHz where transmitters feed a common antenna or where an antenna farm exists [see Note 10 of Appendix 8]. Spurious emissions have been significantly redefined. It is suggested those concerned with such limits be familiar with the new definition contained in RR 139 of Article 1 of the Final Acts.     

A 2.2 W, 80 MHz superscalar RISC microprocessor

A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described. This 32-b implementation of the PowerPC architecture is fabricated in a 3.3 V, 0.5 μm, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, loadstore, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software-programmable, static, low-power operation-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to bus clock ratios of 1×, 2×, 3×, and 4× are implemented to allow control of system power while maintaining processor performance. As a result, workstation level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers     

Testing microprocessors

The testability of microprocessors has become a very important question, especially for device manufacturers. Defining a set of worst case input vectors to exhaustively test still presents one of the major testing problems. This paper discusses a test strategy for microprocessors where the internal logic is separated into two types: data logic and control logic. This approach can be used to ease the definition of the test vectors A practical example is presented in the form of a test program for the SAB 8080 A microprocessor. The worst case functional pattern that was created lasts only 130 ms when run at 2.5 MHz.     

An experimental single-chip data flow CPU

HPSm (high-performance substrate) is a single-chip data flow CPU. It enhances throughput by using three function units to exploit parallelism, while executing RISC instructions in a data-driven manner to keep the function units busy. HPSm is data driven in the sense that instructions whose operands are not ready are not permitted to stall the machine by blocking subsequent ones. It uses branch prediction to exploit concurrency between blocks of code, and is capable of operating at a peak performance of 30 MIPS while running at only 10 MHz. It employs four on-chip smart memories to control the data-driven execution on the three function units, and to support branch prediction and exception handling. Simulations indicate that HPSm achieves significant speedup over a single-chip RISC microarchitecture implemented with the same fabrication technology and clock cycle. The HPSm chip is designed for a 1.6-μm double-metal scalable CMOS process. It contains 87279 transistors, occupies an area of 13.83 mm×13.04 mm, and is estimated to dissipate 2 W at 10 MHz     

2.44-GFLOPS 300-MHz floating-point vector-processing unit forhigh-performance 3D graphics computing

A vector unit for high-performance three-dimensional graphics computing has been developed. We implement four floating-point multiply-accumulate units, which execute multiply-add operations with one throughput; one floating-point divide/square root unit, which executes division and square-root operations with six cycles at 300 MHz; and one vector general-purpose register file, which has 128 bits×32 words. The parallel execution of all units delivers a peak performance of 2.44 GFLOPS at 300 MHz     

A 400-MHz S/390 microprocessor

A microprocessor implementing IBM S/390 architecture operates in a 10+2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2-μm L_eff CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm×17.30 mm with about 7.8 million transistors. The power supply is 2.5 V and measured power dissipation at 300 MHz is 37 W. The microprocessor features two instruction units (IUs), two fixed point units (FXUs), two floating point units (FPUs), a buffer control element (BCE) with a unified 64-KB L1 cache, and a register unit (RU). The microprocessor dispatches one instruction per cycle. The dual-instruction, fixed, and floating point units are used to check each other to increase reliability and not for improved performance. A phase-locked-loop (PLL) provides a processor clock that runs at 2× the system bus frequency. High-frequency operation was achieved through careful static circuit design and timing optimization, along with limited use of dynamic circuits for highly critical functions, and several different clocking/latching strategies for cycle time reduction. Timing-driven synthesis and placement of the control logic provided the maximum flexibility with minimum turnaround time. Extensive use of self-resetting CMOS (SRCMOS) circuits in the on-chip L1 cache provides a 2.0-ns access time and up to 500 MHz operation     

Specific absorption rates (SARs) induced in head tissues by microwave radiation from cell phones

The cellular/mobile phone industry has been reluctant to disclose SAR values to the public in the past. The decision by the Cellular Telecommunication Industry Association (CTIA) to require manufacturers to disclose SARs emerged after it became clear that SAR information was going to appear on the FCC Web site in a user-friendly form. It was also prompted by a British government panel's call, on May 11, 2000, for the SAR of each mobile phone to be printed on the box in which the phone is sold. The wireless telephone industry is concerned about how the public may use the SARs, because, according to one industry source, "SARs by themselves may be misleading and variations in SARs do not represent a variation in safety." Indeed, SAR values can vary as a function of the carrier frequency-for example, 850 or 1900 MHz, used to transmit the telephone message-or how the handset is held. The article presents some insights into SAR, what it is, how is it determined, and what it means.     

基于物联网的城市消防远程监控系统

根据物联网的概念和体系结构,结合视频监控系统,建立了基于物联网的城市消防远程监控系统结构,从监控指挥中心、公安消防管理部门和联网单位等系统用户的角度,分析了远程监控系统的功能,并主要论述了远程监控系统在感知层实现所需要的关键技术,包括不同厂家的消防主机联网及报警数据通信协议制定,以及不同厂家视频监控系统的联网及视频控制协议制定。     

Blades have the edge [blade servers]

An increasing number of computer rooms all over the world are switching from conventional servers to blade servers because they offer huge improvements over conventional, rack-mounted units. The greatest benefit of blades is their flexibility, which allows them to be easily installed, managed and repaired compared to conventional servers. The promise of blades lies not so much in their hardware as in the software used to manage them. Blades' management programs let system administrators automate and simplify what are otherwise tedious, time-consuming tasks. Another useful feature manufacturers are adding to blades is the ability to split a single physical blade server into many smaller, virtual ones. This allows an administrator to create logical shells that each run a different operating system and its respective applications simultaneously on a single server.     

CW three-terminal GaAs oscillator

Three-terminal GaAs devices have oscillated coherently at frequencies between 60 MHz and 2500 MHz. Continuous power outputs at room temperature are generally less than 1 mW. Typical units are fabricated from GaAs p-n diodes by sawing into the n side with an 0.0005- or 0.001-inch tungsten wire to a depth close to the depletion region. The resultant device has an n contact on either side of the cut and one control contact on the p region. At a threshold bias field of approximately 4 kV/cm in the narrow neck between the sawcut and the depletion region, coherent microwave or submicrowave oscillations commence. The frequency of oscillation is primarily a function of external circuitry and device size, but can also be controlled by a bias applied to the p electrode.     

Ultralow-power adiabatic circuit semi-custom design

This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiabatic systems (e.g., arithmetic units) in a short time and easy way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom PFAL carry lookahead adders and parallel multipliers were designed in a 0.6-/spl mu/m CMOS technology and verified. Post-layout simulations show that semi-custom adiabatic arithmetic units can save energy a factor 17 at 10 MHz and about 7 at 100 MHz, as compared to a logically equivalent static CMOS implementation. The energy saving obtained is also better if compared to other custom adiabatic circuit realizations and maintains high values (3/spl divide/6) even when the losses in power-clock generation are considered.     

Solid state

Competition among semiconductor manufacturers has intensified, quickening the pace of technological development. In the drive to capture market share, companies are turning out new generations of products with dizzying speed. Subhalf-micrometer lithographic feature sizes in commercial products have pegged new lows, while 275 MHz processing speeds have reached new highs. With feature sizes progressing toward 0.25 μm, scientists are optimizing everything from process-monitoring software to circuit boards and modules. Some are already looking at the next step-linewidths of 0.18 μm and below-that will be needed to make 1-gigabit memories. To keep up with product demand and rapidly advancing technology, new factories are going up all over the world, and marketing strategies have changed. The latest developments are discussed including microprocessors that can save power when machines are idle, and the new Alpha 275 MHz chip and Si-Ge technology     

Broad-Band Coaxial Boosted Media Employing Negative-Impedance Junctions and Amplifiers

As an approach to the broad-band, multi-port, multilateral media with idealized transmitting ability for various communications, a "Flat Loss Boosted Coaxial Line" (FLB Line) with many ports, such a centipede, has been proposed. It has been built from Negativeresistance BridgedTtypesqrt{f}shape Boosters (FBA) with about 10 dB gain at 300 MHz and Negative-resistance Boosting Junctions (NBJ) with an effective gain of 4.8 dB and no directivity nor phase distortion. In this line, signal powers at all branching ports axe principally equal and are transmitted bilaterally over all frequency range, while maintaining not only sufficient stability margin but also allowable transmission performance. A trial 2 km line composed of 8 FLB sections and 3 NBJ units has demonstrated engineering feasibility that bidirectional transmission of 5 color TV signals. It operated with almost no ghosts and without any adjacent channel interferences over a frequency range from 5 MHz up to about 400 MHz.     

小型化多频基站天线的设计

文中设计了一种工作频段为698~960MHz的新型低频辐射单元,该辐射单元上方可嵌套4个工作频段为1700~2700MHz的高频辐射单元,实现一列低频两列高频的多频天线,底板宽度只有280mm,与常规三频天线的宽度380mm相比,宽度减小约26%,减小了天线尺寸,实现了天线的小型化设计。仿真结果表明,该方案在698~960MHz及1700~2700MHz的水平面方向上,能满足常规基站天线的需求。     

Telemetry System for Stimulation and Monitoring of Freely Moving Patients

A telemetry system is described in which the patient carries small stimulator and monitor units. Typically, the wrist is stimulated with 0.5 ms alternating pulses whose frequency and current (up to 10 mA peak) are remotely controlled by the neurophysiologist via a 20 MHz carrier. At the same time, the synchronized EEG-somatosensory evoked potential is transmitted from C2 via a 100 MHz carrier. The stimulus unit transmits a 100 MHz " flag" signal to the neurophysiologist to indicate that the patient is actually receiving a stimulus signal. Several examples are given in which latencies and amplitudes of the EEG-SEP are recorded.     

一种高速LVDS接口的存储器设计

此存储器设计是基于已有SRAM基础上增加外围LVDS接口和一些数据处理电路而改进的一种新型存储器。它应用一些有LVDS接口的高速AD上,可直接接收AD过来的数据,写入到存储器中,然后通过LVDS接口进行读操作。此存储器的时钟为500MHz,存储容量为4Mbits,支持数据单沿采样和双沿采样,采用QFN88封装,面积2.5mm*3mm。     

A wide-range and fast-locking all-digital cycle-controlled delay-locked loop

An all-digital cycle-controlled delay-locked loop (DLL) is presented to achieve wide range operation, fast lock and process immunity. Utilizing the cycle-controlled delay unit, the proposed DLL reuses the delay units to enlarge the operating frequency range rather than cascade a huge number of delay units. Adopting binary search scheme, the two-step successive-approximation-register (SAR) controller ensures the proposed DLL to lock the input clock within 32 clock cycles regardless of input frequencies. The DLL operates in open-loop fashion once lock occurs in order to achieve low jitter operation with small area and low power dissipation. Since the DLL will not track temperature or supply variations once it is in lock, it is best suited for burst mode operation. Given a supplied reference input with 50% duty cycle, the DLL generates an output clock with the duty cycle of nearly 50% over the entire operating frequency range. Fabricated in a 0.18-/spl mu/m CMOS one-poly six-metal (1P6M) technology, the experimental prototype exhibits a wide locking range from 2 to 700 MHz while consuming a maximum power of 23 mW. When the operating frequency is 700 MHz, the measured peak-to-peak jitter and rms jitter is 17.6 ps and 2.0 ps, respectively.     

5G站点建设动力配套解决方案探讨

当前5G使用3.5 GHz频率,频段带宽100 MHz,为了保证一定的网络覆盖以及网络质量,5G设备的功耗远大于LTE设备。基于当前主流基站设备厂家的试验网产品的功耗,结合现网基站的动力情况,分析5G基站设备对动力需求,给出相应的解决方案,提前进行站点的动力配套储备,为未来5G网络大规模快速部署建设提供必要的参考。     

International intercomparison of specific absorption rates in a flat absorbing phantom in the near-field of dipole antennas

This paper reports the results of an international intercomparison of the specific absorption rates (SARs) measured in a flat-bottomed container (flat phantom), filled with human head tissue simulant fluid, placed in the near-field of custom-built dipole antennas operating at 900 and 1800 MHz, respectively. These tests of the reliability of experimental SAR measurements have been conducted as part of a verification of the ways in which wireless phones are tested and certified for compliance with safety standards. The measurements are made using small electric-field probes scanned in the simulant fluid in the phantom to record the spatial SAR distribution. The intercomparison involved a standard flat phantom, antennas, power meters, and RF components being circulated among 15 different governmental and industrial laboratories. At the conclusion of each laboratory's measurements, the following results were communicated to the coordinators: Spatial SAR scans at 900 and 1800 MHz and 1 and 10 g maximum spatial SAR averages for cubic volumes at 900 and 1800 MHz. The overall results, given as mean standard deviation, are the following: at 900 MHz, 1 g average 7.850.76; 10 g average 5.160.45; at 1800 MHz, 1 g average 18.44/spl plusmn/1.65; 10 g average 10.14/spl plusmn/0.85, all measured in units of watt per kilogram, per watt of radiated power.     

Minimum Cost Systems with Specified Reliability

A method is presented for allocating reliability to each unit of a system with a view to minimizing the system cost. The practical utility of this method, as well as other methods, depends heavily on the availability of cost-reliability data for the 1 constituent units. Unfortunately, for most components such data are not readily available. There is a need for manufacturers and users to make these data available to reliability theoreticians so that the derived results are usefully applied to practical systems. So far, very little seems to have been done in this direction.