Transient thermal analysis of sapphire wafers subjected to thermal shocks

Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer was developed to analyze the transient heat conduction in conjunction with the heat radiation and heat convection on the wafer surfaces. A silicon wafer was also investigated, for comparison. It was found that the rapid thermal loading leads to a parabolic radial temperature distribution, which induces thermal stresses even if the wafer is not mechanically restrained. The study predicted that for sapphire wafers the maximum furnace temperature of 800 /spl deg/C should be held for two hours in order to get a uniform temperature throughout the wafer.     

Rapid thermal processing of silicon wafers with emissivity patterns

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.     

Thermal uniformity of 12-in silicon wafer during rapid thermalprocessing by inverse heat transfer method

Through an inverse heat transfer method, this paper presents a finite difference formulation for determination of incident heat fluxes to achieve thermal uniformity in a 12-in silicon wafer during rapid thermal processing. A one-dimensional thermal model and temperature-dependent thermal properties of a silicon wafer are adopted in this study. Our results show that the thermal nonuniformity can he reduced considerably if the incident heat fluxes on the wafer are dynamically controlled according to the inverse-method results. An effect of successive temperature measurement errors on thermal uniformity is discussed. The resulting maximum temperature differences are only 0.618, 0.776, 0.981, and 0.326°C for 4-, 6-, 8- and 12-in wafers, respectively. The required edge heating compensation ratio for thermal uniformity in 4-, 6-, 8and 12-in silicon wafers is also evaluated     

Mechanical strength of 300 mm diameter silicon wafers at high temperatures: modeling and simulation

Under gravitational and thermal constraints of IC process technology, 300 mm diameter silicon wafers can partly relax via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the criterion for yielding under a plane stress state. The material attributes, e.g. oxygen and its state of aggregation, are taken into account. While the plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design, the control of plastic deformation due to gravitational forces may be accomplished by equipment design. This system approach allows calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulations for use in ‘what if’ experiments or initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes.     

Influence of dry and wet cleaning on the properties of rapid thermal grown and deposited gate dielectrics

Various silicon surface cleaning processes for rapid thermal in-situ polysilicon/ oxide/silicon stacked gate structures have been evaluated. Metal-oxide-semiconductor capacitors were fabricated to assess the effects of cleaning on the quality of gate oxide structures produced by both rapid thermal oxidation (RTO) and rapid thermal chemical vapor deposition (RTCVD). Excellent electrical properties have been achieved for both RTO and RTCVD gate oxides formed on silicon wafers using either an ultraviole/zone (UV/O₃) treatment or a modified RCA clean. On the contrary, poor electrical properties have been observed for RTO and RTCVD gate oxides formed on silicon wafers using a high temperature bake in Ar, H₂, or high vacuum ambient. It has also been found that the electrical properties of the RTCVD gate oxides exhibit less dependence upon cleaning conditions than those of RTO gate oxides. This work demonstrates that initial surface condition prior to gate oxide formation plays an important role in determining the quality of RTO and RTCVD gate oxides.     

Analyses of thermal stresses and control schemes for fasttemperature ramps of batch furnaces [IC manufacture]

This work studies fast temperature ramps of batch furnaces under different control schemes based on thermal and stress analyses. A thermal model is first developed to predict temperature distributions on silicon wafers during ramping processes. Thermoelastic model of stresses is then used to predict the onset of slip-line generation under dynamic conditions. Three control schemes, one based on a maximum allowable within-wafer temperature difference, one with a constant cooling rate, and the third based on the condition for onset of slip generation, are then analyzed. The results show that in order to achieve the highest ramp rates while maintaining defect-free wafer processing, the ultimate criterion for temperature control of the furnaces should be the condition for the onset of defect generation instead of the conventional scheme based on constant ramp rates     

Features of defect formation under the thermal treatment of dislocation-free single-crystal large-diameter silicon wafers with the specified distribution of oxygen-containing gettering centers in the bulk

Possibilities of obtaining a defect-free layer in wafers of dislocation-free single-crystal silicon subjected to rapid thermal annealing (RTA) are analyzed. The application of RTA is based on the possibility of effectively affecting the distribution profile of the density of oxygen precipitates over the wafer thickness by means of controlling the distribution profiles of the vacancies and interstitial atoms. However, the solution of this important task encounters the problem of the appearance of large local stresses in the vicinity of the fastening supports of a large-diameter silicon wafer and its bending in the course of RTA, which are caused by its own weight. Using mathematical modeling of the three-dimensional stress-strain state and defect formation in large-diameter silicon wafers in the course of RTA, various methods of fastening the wafers are considered and the possibilities of lowering the stress-strain state of the silicon wafer are determined. A mathematical model taking into account the diffusion-recombination processes of vacancies and interstitial silicon atoms, as well as the formation of vacancy clusters is proposed to describe the defect formation in the course of RTA. Based on this model, temperature-temporal parameters of RTA, which correspond to the required (depleted near the surface) concentration profile of the vacancies and the density and size of the vacancy clusters over the wafer thickness, are determined (heating time, holding time at the highest temperature, the cooling rate of the wafer). The results of the calculations are verified for test samples using optical microscopy and transmission electron microscopy (OM and TEM).     

Temperature distribution in semiconductor wafers heated in avertical diffusion furnace

The transient temperature distribution in a row of wafers in a vertical diffusion furnace was calculated as the heating power of the furnace was PID (proportional-integral-derivative)-controlled. Radiative heat transfer was combined with axisymmetric unsteady conduction in wafers and the furnace. With feedforward control of the heating power (which means that when wafers are inserted into the furnace, heater temperature is set higher than the desired heating temperature), the temperature of the wafers reached the heating temperature rapidly. The radiative properties of silicon wafers changed from semitransparent to opaque at 500°C, and the effect of this change on the temperature distribution in the wafers was calculated. It was found that thermoplastic deformation of the wafers is more likely to occur during withdrawal than during insertion     

Prediction of defect onset conditions in heat cycling based on athermoelastic wafer model

A thermoelastic wafer model is proposed for predicting defect onset conditions during heat cycling in a furnace. This model is formulated for application to the plane stress state under thermal loading. The wafer temperature is calculated by a wafer temperature model proposed in a previous work. Predictions are tested by comparison with the thermal stresses resolved on the slip systems of the silicon crystal under the process conditions (i.e. furnace temperature, insertion velocity, and wafer spacing). When the proposed model is applied to 125-mm diameter and 150-mm-diameter wafers, it is shown that the thermal stress level is reduced to about a half by increasing the wafer spacing by a factor of two or three. Accordingly, the predicted defect onset results based on this model are in reasonable agreement with experiments     

Thermal uniformity and stress minimization during rapid thermalprocesses

The practical development and implementation of rapid thermal processes will significantly influence the semiconductor fabrication industry. With the capability to perform heat cycles quickly and with low thermal budgets, rapid thermal processors have the potential to supplant conventional thermal systems in the years to come. Currently, rapid thermal processors are unable to match the thermal process uniformity produced in conventional convective-based systems. Using a thermal model to approximate the heating characteristics of silicon wafers, it is possible to determine the effects of time-varying intensity profiles on a wafer during a rapid thermal process. Interpretation of this model shows idealized intensity profiles can maintain thermal uniformity at steady-state temperatures. During thermal transients a dynamic continuously changing profile is required to maintain thermal uniformity. As a predictive tool, this analysis can be used to determine and evaluate dynamic uniformity producing intensity profiles before thermal transients occur within a process. This approach can reduce the accumulation of error during high temperature steps not only by providing thermal uniformity at steady states, but by reducing the initial nonuniformities produced by transitions. This paper will review the wafer model, show the results of an idealized profile for steady-state and transient temperatures, and explain the dynamic profiles required for continuous uniformity     

Full Field Temperature Measurement of Specular Wafers During Rapid Thermal Processing

Many of the processes involved in the creation of semiconductor devices involve high-temperature processing of silicon wafers. The benefits of reduced thermal budget and faster cycle time make rapid thermal processing (RTP) a possible key technology for semiconductor manufacturing. However, the problem of nonuniform wafer temperature has prevented it from further spread among the industry. The first step in developing controls to maintain a uniform wafer temperature is accurate temperature measurement during processing. In this paper, a system was developed to exploit the specular reflectivity of silicon wafers and obtain a measurement of the wafer temperature profile. The spectral reflectivity is determined by measuring the intensity of an incident beam and the beam reflected from the wafer surface. With this measured reflectivity value the spectral-directional wafer emissivity was determined using Kirchhoff's law. The obtained emissivity then was used to calculate the wafer temperature profile from an image obtained with an infrared camera. An experimental study of the transmittance of an undoped silicon calibration wafer at an elevated temperature is also discussed     

Infrared spectroscopy of bonded silicon wafers

Infrared spectra of multiple frustrated total internal reflection and transmission for silicon wafers obtained by direct bonding in a wide temperature range (200–1100°C) are studied. Properties of the silicon oxide layer buried at the interface are investigated in relation to the annealing temperature. It is shown that the thickness of the SiO₂ layer increases from 4.5 to 6.0 nm as the annealing temperature is increased. An analysis of the optical-phonon frequencies showed that stresses in the SiO₂ relax as the annealing temperature is increased. A variation in the character of chemical bonds at the interface between silicon wafers bonded at a relatively low temperature (20–400°C) is studied in relation to the chemical treatment of the wafers’ surface prior to bonding. Models of the process of low-temperature bonding after various treatments for chemical activation of the surface are suggested.     

Multilayer diamond heat spreaders for electronic power devices

Single layer diamond and multilayer diamond heat spreader substrates are prepared and bonded to device wafers of silicon and gallium arsenide. Metallization schemes for the diamond surface and the backside of the device wafers are described. Bonding of the device wafers to the diamond substrates using the high thermal conductivity gold–tin eutectic solder is carried out. Characterization of the bond for the distribution of different elements in the metallization layers and the solder, for the presence of microscopic defects such as voids and cracks, for the adhesion strength and for the stability of the bond under thermal cycling is performed. The heat spreader characteristics of the substrates with single and multlayer diamond are determined using infrared imaging of the bonded device wafers and compared with that of wafers bonded to metal substrates. Modeling and analysis of the effectivethermal conductivity showed that the multilayer diamond substrates are better heat spreaders and reduce the device temperature so that the life of the electronic devices is prolonged.     

直拉单晶硅中氧沉淀的高温消融和再生长

重点研究了直拉(CZ)硅中氧沉淀在快速热处理(RTP)和常规炉退火过程中的高温消融以及再生长行为.实验发现,RTP是一种快速消融氧沉淀的有效方式,比常规炉退火消融氧沉淀更加显著.硅片经RTP消融处理后,在氧沉淀再生长退火过程中,硅中体微缺陷(BMD)的密度显著增加,BMD的平均尺寸略有增加;而经过常规炉退火消融处理后,在后续退火过程中,BMD的密度变化不大,但BMD的尺寸明显增大.氧沉淀消融处理后,后续退火的温度越高,氧沉淀的再生长越快.     

Temperature distribution in semiconductor wafers heated in ahot-wall-type rapid diffusion furnace

Transient temperature distribution was calculated for wafers heated in a new hot-wall-type rapid diffusion furnace. Two-dimensional radiative heat transfer was combined with unsteady conduction in wafers and the furnace. The furnace is composed of parallel plate heaters, and heats wafers to a temperature of about 1000°C. The heaters are divided into four zones and their heating powers are PID-controlled. Two wafers on a holder are inserted vertically from the bottom of the furnace, and heated for three minutes. The calculated results show the wafer temperature approached the desired heating temperature about one minute after insertion, agreeing with experimental results. The average temperature distribution in the wafers during heating is found to be within ±1°C at 1000°C, when the heating power (temperature) of the four zones is properly controlled. The effects of heater temperature, insertion speed, and holder thickness on the temperature distribution in wafers were calculated. The new hot-wall-type rapid diffusion furnace can be used to manufacture future VLSI     

A global model for rapid thermal processors

A simple model for the components that make up a rapid thermal processing system is given. These components are the furnace, the pyrometer used to measure temperature, and the control system that utilizes the pyrometer measurement to control the power to the lamps. The models for each of the components are integrated in a numerical code to give a computer simulation of the complete furnace operation. The simulation can be used to investigate the interaction of the furnace, temperature-sensing technique, and the control system. Therefore, the interplay of heat transfer (furnace) properties, optical (pyrometer) parameters, and control gains can be studied. The objective is to define variability in wafer temperature as process parameters change. The following three applications of the model are included: (1) a simulation of open-loop operation; (2) a simulation of the ramp up and subsequent operation with a step change in wafer optical properties; and (3) a simulation of the rapid thermal chemical vapor deposition of polysilicon on silicon oxide which demonstrates the applicability model for actual processes. A technique for correction of pyrometer output to improve temperature control is also presented     

New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity

We propose in this letter a new passivation method to get rid of parasitic surface conduction in oxidized high resistivity (HR) silicon and HR silicon-on-insulator (SOI) wafers. The method consists in passivating the HR substrate with a rapid thermal anneal (RTA)-crystallized layer of silicon. The electrical efficiency of this new passivation technique is analyzed and shown to be superior over previously published methods. The surface roughness as well as the stability over temperature of this layer are also investigated. It is shown that this new passivation method is the only one simultaneously combining a low surface roughness and a high stability over long thermal anneals. In the context of SOI technology, it therefore appears as the most suitable technique for the substrate passivation of HR SOI wafers, for which a bonding between an oxidized silicon wafer and a passivated HR substrate is required.     

Wafer temperature measurement in a rapid thermal processor with modulated lamp power

Pyrometry methods utilizing modulated lamp power (“ripple”) were used to improve wafer temperature measurement and control in rapid thermal processing (RTP) for silicon integrated circuit production. Data from a manufacturing line where ripple pyrometers have been tested show significantly reduced wafer to wafer and lot to lot variations in final test electrical measurements and increased yields of good chips per wafer. The pyrometers, an outgrowth of Accufiber’s ripple technique, are used to compensate for ordinary production variations in the emissivities of the backsides of wafers, which face the pyrometers. Power to the heating lamps is modulated with oscillatory functions of time at either the power line frequency or under software control. Fluctuating and quasi-steady components in detected radiation are analyzed to suppress background reflections from the lamps and to correct for effective wafer emissivity. Sheet resistances of annealed wafers with high dose shallow As implants were used to infer temperature measurement capability over a range in backside emissivity. Emissivities are varied when depositing or growing one or more layers of silicon dioxide, silicon nitride, or polycrystalline silicon on the backsides of the wafers.     

A model for rapid thermal processing: achieving uniformity throughlamp control

A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures     

Recent developments in rapid thermal processing

Rapid thermal annealing (RTA) with a short dwell time at maximum temperature is used with ion implantation to form shallow junctions and polycrystalline-Si gate electrodes in complementary, metal-oxide semiconductor (CMOS) Si processing. Wafers are heated by electric lamps or steady heat sources with rapid wafer transfer. Advanced methods use “spike anneals,” wherein high-temperature ramp rates are used for both heating and cooling while also minimizing the dwell time at peak temperature to nominally zero. The fast thermal cycles are required to reduce the undesirable effects of transient-enhanced diffusion (TED) and thermal deactivation of the dopants. Because junction profiles are sensitive to annealing temperature, the challenge in spike annealing is to maintain temperature uniformity across the wafer and repeatability from wafer to wafer. Multiple lamp systems use arrayed temperature sensors for individual control zones. Other methods rely on process chambers that are designed for uniform wafer heating. Generally, sophisticated techniques for accurate temperature measurement and control by emissivity-compensated infrared pyrometry are required because processed Si wafers exhibit appreciable variation in emissivity.