一种全差分电荷泵设计

本文设计一种新型的全差分电荷泵,采用差分输入和差分输出。采用差分输出不但能够降低电荷泄漏所带来的电压噪声,而且能够提高电荷泵的上升和下降速度。上拉泵电路和下拉泵电路完全对称,能够消除电流失配所带来的噪声,并采用正反馈电路结构,以提高开启和关断速度,并降低功耗。电路在0.18μm工艺,BSIM 3V 3模型下,采用Cadence中的Spectre仿真工具进行仿真,当电源电压VDD=1.8V,f=100MH z时,电路输出的电压范围是0V~1.8V,功耗为0.01mW。     

基于常数跨导轨到轨运算放大器的新型电荷泵

针对传统电荷泵电荷共享引起的输出电压波动、充放电电流失配引起的电路杂波问题,设计了一种新型电荷泵。该电荷泵电路采用常数跨导轨到轨运算放大器,降低了电荷共享引起的输出电压波动;采用基于全差分放大器的负反馈结构,解决了充放电电流失配的问题。基于SMIC 0.18 μm CMOS工艺,利用Cadence软件完成了电路的设计与仿真。结果表明,在0.5～1.5 V输出电压范围内,该电荷泵充放电电流失配小于2%;与传统电荷泵相比,该电荷泵输出电压的波动减小了1.5 mV,并且采用该电荷泵的锁相环输出频谱噪声减小了10 dB。     

用于相变存储器的超低输出纹波2X/1.5X电荷泵

本文针对相变存储器编程驱动电路,提出了一种超低输出电压纹波的开关电容型电荷泵。该电荷泵可根据输入电压的不同,自适应工作在2X/1.5X升压模式之间,以获得更高的电源转换效率。相比于传统开关电容型电荷泵,在充电阶段泵电容被充电至预先设定的电压值Vo-VDD(Vo为预期的输出电压);放电阶段,泵电容串联在输入电压VDD与输出端,通过此方法将电荷泵输出端电压稳定在Vo,并有效的降低了由于电荷分享所造成的输出纹波。在中芯国际40nm标准CMOS工艺模型下,对电路进行了仿真验证,结果表明在输入电压为1.6-2.1V,输出2.5V电压,最大负载电流为10mA,输出电压纹波低于4mV,电源效率最高可达91%。     

锁相环中高性能电荷泵的设计

设计了一种结构新颖的动态充放电电流匹配的电荷泵电路，该电路利用一种放电电流对充电电流的跟随技术，使充放电电流达到较好匹配，同时，在电荷泵中增加差分反相器，提高电荷泵的速度。采用Istsilicon 0．25μmCMOS工艺进行仿真，结果显示：输出电压在0．3—2．2V之间变化时，电荷泵的充放电电流处处相等。     

一种用于白光LED驱动的电荷泵的设计

提出了一种可用于白光LED驱动芯片的电路设计,主要从低噪声、高效率两方面进行设计。采用线性模式控制方法,最大限度减小电荷泵电源电流纹波,从而降低噪声,同时应用多增益工作模式提高不同输入电源电压下的效率。详细讨论了其中带隙电压基准、振荡器及跨导放大器三大模块的电路结构、工作原理和性能特点。采用此电荷泵电路的芯片已在CSMC0.6μm CMOS工艺线投片,测试结果表明,该电荷泵电路工作良好,有效减小了PCB面积和降低了噪声,并且在不同输入电源电压下均能保持较高效率,输出在200 mA时,效率可达92%。     

一款基于电荷泵高压内电源的恒定跨导轨到轨运算放大器

设计了一款基于电荷泵高压内电源的恒定跨导轨到轨运算放大器.输入级采用PMOS差分对结构,通过电荷泵产生高于电源电压的输入级内电源,使运放在轨到轨输入范围能正常工作并保持输入跨导恒定.电荷泵电路所需的时钟信号通过内部振荡器电路产生,再通过电压自举电路和时序电路产生所需电平的非交叠开关控制信号,最后利用时间交织结构输出连续稳定的高压内电源.在电荷泵实现中还采用了辅助开关结合跟随运放的结构降低了主开关在切换时的毛刺.该运放在折叠式共源共栅结构中使用增益自举结构提高了总体增益,输出级采用class AB类输出结构实现轨到轨输出.该运算放大器基于0.5μm CMOS工艺完成电路与版图设计,仿真结果表明,在5 V电源电压下,直流增益为150.76 dB,单位增益带宽为53.407 MHz,相位裕度为96.1°,输入级跨导在轨到轨输入共模范围内的变化率为0.001 25%.     

一种用于H桥功率驱动电路的电荷泵设计

提出了一种可驱动H桥功率电路的电荷泵.为了简化电路设计和确保电路稳定性,本电荷泵采用两倍压电荷泵电路拓扑结构,通过加入两路反馈控制电路来提高电荷泵充电电流和输出电压值的控制精度以及电源转换效率.设计采用0.35μm BCD工艺,通过Cadence Spectre仿真器表明,在负载电流为5mA条件下,电荷泵正常工作时输出电压范围广(10~40V),电源转换效率最高达到91%,输出电压建立所需时间为579μs.样片实测结果显示,在不同输入电压条件下,输出电压纹波控制在385mV以下.     

锁相环中基于电流控制技术的电荷泵的设计

锁相环能够跟踪输入信号的相位和频率,并输出相位锁定、低抖动的其他频率信号,广泛应用于通信系统中。高性能的锁相环芯片的设计,是当今通信领域研究的一个重点。文中对锁相环电路中的电荷泵电路模块进行改进,设计出一种带有电流控制技术的差分型电荷泵,实现了低功耗、高充放电速度的目的,并很好抑制电荷共享效应。同时通过电流模滤波器电路的设计,减小了整体电路的噪声,降低了功耗。     

用于电机驱动芯片的高压电荷泵电路设计

基于开关电容系统理论,提出了一种用于步进电机芯片中H桥驱动电路的电荷泵电路。电路设计了零温度系数的高压压差检测电路、线形调制的反馈控制电路和泵电容充电电流控制电路。基于HHNEC 0.35μm BCD工艺平台进行电路设计,并完成流片。测试结果显示,电荷泵电路输出电压跟随输入电压线性变化,输出电压范围为13 V~41 V,纹波电压大小约为560 mV。所获结果与设计目标保持一致,证明了设计思想的正确性。     

一种高性能CMOS电荷泵的设计

设计了一种用于电荷泵锁相环的CMOS电荷泵电路。电路中采用3对自偏置高摆幅共源共栅电流镜进行泵电流镜像,增大了低电压下电荷泵的输出电阻,实现了上下两个电荷泵的匹配。为消除单端电荷泵存在的电荷共享问题,引入了带宽幅电压跟随的半差分电流开关结构,使电荷泵性能得以提高。设计采用0.18μm标准CMOS工艺。电路仿真结果显示,在0.35～1.3V范围内泵电流匹配精度达0.9%,电路工作频率达250MHz。     

Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching

An ultrahigh-speed fully differential charge pump with minimum current mismatch and variation is proposed in this brief. A mismatch suppression circuit is employed to minimize the mismatch between the charging and discharging currents, which minimizes the steady-state phase error in a phase-locked loop (PLL). A variation suppression circuit is proposed to minimize output current variation with the change of output voltage, which reduces the variation of the bandwidth in a PLL. Techniques are proposed to suppress both low-speed glitches and high-speed glitches in the output current to allow glitch-free operation of the charge pump with ultrafast input pulses. The differential charge pump is designed and simulated under the power supply of 3.3 V in TSMC 0.35-$mu$m CMOS technology to verify the effectiveness of the proposed techniques.     

Design of a high performance CMOS charge pump for phase-locked loop synthesizers

A new high performance charge pump circuit is designed and realized in 0.18μm CMOS process. A wide input ranged rail-to-rail operational amplifier and self-biasing cascode current mirror are used to enable the charge pump current to be well matched in a wide output voltage range.Furthermore,a method of adding a precharging current source is proposed to increase the initial charge current,which will speed up the settling time of CPPLLs.Test results show that the current mismatching can be less than 0.4%in the output voltage range of 0.4 to 1.7 V,with a charge pump current of 100μA and a precharging current of 70μA.The average power consumption of the charge pump in the locked condition is around 0.9 mW under a 1.8 V supply voltage.     

一种用于视频信号处理的高速宽带运算放大器

基于高速亚微米互补双极工艺,设计了一种用于视频信号处理的高速宽带运算放大器。电路内部采用高速输入差分对、电流型放大单元、Rail-to-Rail输出单元等结构进行信号传输和放大。对开环增益提升、高速电压-电流信号转换、满摆幅输出设计以及频率稳定性补偿等关键技术进行分析,利用Spectre软件进行仿真。流片后的测试结果表明,在±5 V工作电压下,该放大器的－3 dB带宽≥200 MHz,失调电压≤5 mV,电源电流≤6 mA,满足高速通信、高速ADC前端信号采集、视频信号处理等各种场合的应用需求。     

A self-calibrating Hall sensor IC with direction detection

A monolithic wheel speed sensor integrated circuit based on Hall effect is presented. Speed and motion direction of magnetic encoder wheels or ferromagnetic target wheels are detected. Two specific amplitudes of the magnetic input signal are detected as well. A two-wire current output directly linked to the input signal frequency indicates speed. Direction information and detection of specific amplitudes of the magnetic input signal are encoded in its output pulsewidth. It features a strictly differential sensing principle, a new direction detection algorithm, and a dynamic self-calibrated offset compensation. The integrated circuit is manufactured in a 0.6-/spl mu/m BiCMOS process, enhanced by bipolar transistors with increased breakthrough voltage.     

一种适用于恒定导通时间控制的高性能定时器电路

本文提出一种适用于恒定导通时间控制的开启时间定时器电路。电路中采用与输入电源电压成正比的电流对电容充电,从而实现定时器的定时时间与输入电源电压成反比,解决了传统恒定导通时间控制中系统工作频率随输入电源电压变化的问题。为了获得高的定时精度,开启时间定时器中的比较器采用了自适应偏置技术,根据输入电源电压的情况动态地设置定时器中比较器的偏置电流。基于0.6μmCD工艺,对所设计开启时间定时器电路进行仿真验证。结果表明,本文所设计的开启时间定时器电路,能够始终保证高的定时精度。同时由于定时时间与输入电源电压成反比,在系统中引入了前馈,极大地提高了系统的线性响应速度。     

Research and design of a novel current mode charge pump

To meet the demands for a number of LEDs, a novel charge pump circuit with current mode control is proposed. Regulation is achieved by operating the current mirrors and the output current of the operational transcon ductance amplifier. In the steady state, the input current from power voltage retains constant, so reducing the noise induced on the input voltage source and improving the output voltage ripple. The charge pump small-signal model is used to describe the device's dynamic behavior and stability. Analytical predictions were verified by Hspice sim ulation and testing. Load driving is up to 800 mA with a power voltage of 3.6 V, and the output voltage ripple is less than 45 mV. The output response time is less than 8 μs, and the load current jumps from 400 to 800 mA.     

二极管型非制冷红外探测器的前端电路设计

设计了一种二极管型非制冷红外探测器的前端电路,该电路采用Gm-C-OP积分放大器的结构,将探测器输出的微弱电压信号经跨导放大器(OTA)转化为电流信号,再经电容反馈跨阻放大器(CTIA)积分转化为电压信号输出。该OTA采用电流反馈型结构,可以获得比传统OTA更高的线性度和跨导值。输入采用差分结构,可以有效地消除环境温度及制造工艺对探测器输出信号的影响。电路采用0.35 m CMOS工艺进行设计并流片,5 V电源电压供电。Gm-C-OP积分放大器总面积0.012 6 mm2,当输入差分电压为0~5 mV时,测试结果表明:OTA跨导值与仿真结果保持一致,Gm-C-OP积分放大器可实现对动态输入差分信号到输出电压的线性转化,线性度达97%,输出范围大于2 V。     

Design and application of CMOS bulk input scheme

This work presents CMOS bulk input differential logic (BIDL) circuits. The bulk input scheme is applied to enable bulk terminals to receive signals. A boost circuit is employed to the bulk terminal of an input device. A multiple-input boost circuit is also developed to improve the flexibility of logic design. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential logic network are connected in parallel, leading to a low parasitic resistive and capacitive load. The BIDL has better speed and power performance than conventional differential logic circuits. The flexibility of the logic design is greatly improved. The BIDL is applied to a divide-by-128/129 frequency synthesizer using a 0.25-/spl mu/m CMOS process. Measurement results of the test chip indicate that the operating frequency is 2 GHz at a supply voltage of 2.5 V.     

宽范围 CMOS差分式双端输入-输出电流传输器

基于宽线性跨导及共模检测电路,设计了一种改进型差分式双端输入-输出电流控制电流传输器电路(DIDOCC)。该全差分式电路具有电流控制功能,并能抑制偶次谐波和共模干扰。仿真结果表明,在-1.5～+1.5V供电电压下,总静态电流约为300μA,X1、X2端差分电压输入动态范围为-0.9～0.9V。基于DIDOCC电路,设计了一种全差分二阶滤波器,仿真结果与理论值较为吻合。文中所有电路均基于0.25μmCMOS工艺。