High field effect mobility deuterated amorphous silicon thin-filmtransistors based on the substitution of hydrogen with deuterium

The characteristics of amorphous silicon hydrogen and deuterium thin-film transistors (a-Si:H/a-Si:D TFT) were studied. The deuterated and hydrogenated amorphous silicon channels were prepared by first annealing the as-deposited a-Si:H layer at 550°C in N₂ environment to expel all the hydrogen atoms out of the films, then the D ₂ or H₂ plasma were applied to treat the amorphous silicon layers. The field effect mobility of the conventional hydrogen TFT is usually smaller than 1 cm²/V-s. It was found that substitution of hydrogen with deuterium improved the field effect mobility of the TFT. The maximum field effect mobility of a-Si:D TFT obtained from the saturation region was 1.77 cm²/V-s     

Amorphous-silicon thin-film transistor with liquid phase depositionof silicon dioxide gate insulator

The liquid phase deposition of silicon dioxide (LPD-SiO₂) at 50°C has been successfully applied as the gate insulator for inverted, staggered amorphous silicon thin-film transistors (TFTs). The maximum field-effect mobility of the TFTs, estimated from the saturation region, was 0.53 cm²/V-s, comparable to that obtained for conventional, silicon nitride (SiN_x ) gate transistors. The threshold voltage and subthreshold swing were 6.2 V and 0.76 V/decade, respectively. Interface and bulk characteristics are as good as those obtained for silicon nitride (SiN _x) films deposited by plasma enhanced chemical vapor deposition     

Fully self-aligned tri-layer a-Si:H thin-film transistors withdeposited doped contact layer

We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFTs with deposited n⁺ contacts. Since no critical data alignment is required, this simple process is well suited to fabrication of short channel TFTs. We have fabricated fully self-aligned tri-layer a-Si:H TFTs with excellent device performance, and contact overlaps <1 μm. For a 20-μm channel length TFT with an a-Si:H thickness of 13 nm, the linear region (V_DS=0.1 V) and saturation region (V_DS=25 V) extrinsic mobility values are both 1.2 cm²/V-s, the off currents are <1 pA, and the on/off current ratio is >10⁷     

Low-temperature polysilicon TFT with two-layer gate insulator usingphoto-CVD and APCVD SiO2

The performance of polysilicon thin-film transistors (TFTs) formed by a 600°C process was improved using a two-layer gate insulator of photochemical-assisted vapor deposition (photo-CVD) SiO₂ and atmospheric-pressure chemical vapor deposition (APCVD) SiO₂. The photo-CVD SiO₂, 100 Å thick, was deposited on polysilicon and followed by APCVD SiO₂ of 1000 Å thickness. The TFT had a threshold voltage of 8.3 V and a field-effect mobility of 35 cm²/V-s, which were higher than those of the conventional TFT with a single-layer gate SiO₂ of APCVD. Hydrogenation by hydrogen plasma was more effective for the new TFT than for the conventional device     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Dependence of thin film transistor characteristics on thedeposition conditions of silicon nitride and amorphous silicon

The systematic relation between thin film transistors' (TFT's) characteristics and the deposition conditions of amorphous silicon nitride (a-SiN) films and hydrogenated amorphous silicon (a-Si:H) films is investigated. It is observed that field effect mobility μ_FE and threshold voltage V_th of the TFT's strongly depend on the deposition conditions of these films. The maximum μ_FE of 0.88 cm²/V·s is obtained for the TFT of which a-SiN film is deposited at a pressure of 85 Pa. This phenomenon is due to the variation of the interface states density between a-Si:H film and a-SiN film     

Integrated amorphous and polycrystalline silicon thin-filmtransistors in a single silicon layer

Using a masked hydrogen plasma treatment to spatially control the crystallization of amorphous silicon to polycrystalline silicon in desired areas, amorphous and polycrystalline silicon thin-film transistors (TFTs) with good performance have been integrated in a single film of silicon without laser processing. Both transistors are top gate and shared all process steps. The polycrystalline silicon transistors have an electron mobility in the linear regime of ~15 cm²/Vs, the amorphous silicon transistors have a linear mobility of ~0.7 cm²/Vs and both have an ON/OFF current ratios of >10⁵. Rehydrogenation of amorphous silicon after the 600°C crystallization anneal using another hydrogen plasma is the critical process step for the amorphous silicon transistor performance. The rehydrogenation power, time, and reactor history are the crucial details that are discussed in this paper     

Formation of source and drain regions for a-Si:H thin-filmtransistors by low-energy ion doping technique

A low-energy ion doping technique has been applied to form source and drain regions of hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) with an inverted staggered electrode structure. Phosphine gas diluted in hydrogen was discharged by RF power and magnetic field. Both phosphorus and hydrogen ions were accelerated to an energy of 5.5 keV and implanted into heated samples. The ON-OFF current ratio and the field-effect mobility of the fabricated TFTs were 10⁶ and 0.12 cm²/V-s, respectively     

Stable gallium arsenide MIS capacitors and MIS field effecttransistors by (NH4)2Sx treatment andhydrogenation using plasma deposited silicon nitride gate insulator

The beneficial effects of sulfur passivation of gallium arsenide (GaAs) surface by (NH₄)₂S_x chemical treatment and by hydrogenation of the insulator-GaAs interface using the plasma-enhanced chemical vapor-deposited (PECVD) silicon nitride gate dielectric film as the source of hydrogen are illustrated by fabricating Al/PECVD silicon nitride/n-GaAs MIS capacitors and metal insulator semiconductor field effect transistors (MISFET). Post metallization annealing (PMA) at temperatures in the range 450-550°C is shown to be the key process for achieving midgap interface state density below 10 ¹¹/cm²/eV and maximum incremental transconductance, which is about 75% of the theoretical maximum limit. MIS capacitors are fabricated on (NH₄)₂S_x treated GaAs substrate using gate dielectrics such as PECVD SiO ₂ and silicon oxynitride to demonstrate that the PMA is less effective with these dielectrics because of their lower hydrogen content. The small signal AC transconductance, g_ms measurements on MISFETs fabricated using silicon nitride, have shown that the low-frequency degradation of g_ms is almost absent in the devices fabricated on (NH₄)₂S_x-treated GaAs substrates and subjected to PMA. The drain current stability in these devices is demonstrated to be excellent, with an initial drift of only 2% of the starting value. The dual role of silicon nitride layer, namely, protection against loss of sulfur and an excellent source of hydrogen for additional surface passivation along with sulfur is demonstrated by comparing the transconductance of MISFETs fabricated on GaAs substrates annealed without the nitride cap after the (NH₄)₂S _x treatment     

Thin-film transistors in polycrystalline silicon by blanket andlocal source/drain hydrogen plasma-seeded crystallization

Thin film n-channel transistors have been fabricated in polycrystalline silicon films crystallized using hydrogen plasma seeding, by using several processing techniques with 600 to 625°C or 1000°C as the maximum process temperature. The TFTs from hydrogen plasma-treated films with a maximum process temperature of 600°C, have a linear field-effect mobility of ~35 cm²/Vs and an ON/OFF current ratio of ~10⁶, and TFTs with a maximum process temperature of 1000°C, have a linear field-effect mobility of ~100 cm²/Vs and an ON/OFF current ratio of ~10⁷. A hydrogen plasma has also then been applied selectively a in the source and drain regions to seed large crystal grains in the channel. Transistors made with this method with maximum temperature of 600°C showed a nearly twofold improvement in mobility (72 versus 37 cm² /Vs) over the unseeded devices at short channel lengths. The dominant factor in determining the field-effect mobility in all cases was the grain size of the polycrystalline silicon, and not the gate oxide growth/deposition conditions. Significant increases in mobility are observed when the grain size is in order of the channel length. However the gate oxide plays an important role in determining the subthreshold slope and the leakage current     

Inverse staggered poly-Si and amorphous Si double structure TFT'sfor LCD panels with peripheral driver circuits integration

Inverse staggered polycrystalline silicon (poly-Si) and hydrogenated amorphous silicon (a-Si:H) double structure thin-film transistors (TFT's) are fabricated based on the conventional a-Si:H TFT process on a single glass substrate. After depositing a thin (20 nm) a-Si:H using the plasma CVD technique at 300°C, Ar⁺ and XeCl (300 mJ/cm²) lasers are irradiated successively, and then a thick a-Si:H (200 nm) and n⁺ Si layers are deposited again. The field effect mobilities of 10 and 0.5 cm ²/V·s are obtained for the laser annealed poly-Si and the a-Si:H (without annealing) TFT's, respectively     

High temperature formed SiGe p-MOSFETs with good devicecharacteristics

We have used a simple process to fabricate Si_0.3Ge_0.7/Si p-MOSFETs. The Si_0.3Ge _0.7 is formed using deposited Ge followed by 950°C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. A hole mobility of 250 cm²/Vs is obtained from the Si_0.3Ge_0.7 p-MOSFET that is ~two times higher than Si control devices and results in a consequent substantially higher current drive. The 228 Å Si_0.3Ge_0.7 thermal oxide grown at 1000°C has a high breakdown field of 15 MV/cm, low interface trap density (D_it) of 1.5×10¹¹ eV^-1 cm^-2, and low oxide charge of 7.2×10¹⁰ cm^-2. The source-drain junction leakage after implantation and 950°C RTA is also comparable with the Si counterpart     

Hydrogenated amorphous silicon thin film transistor fabricated onplasma treated silicon nitride

We have demonstrated that the performance of the inverted staggered, hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) is improved by a He, H₂, NH₃ or N₂ plasma treatment for a short time on the surface of silicon nitride (SiN _x) before a-Si:H deposition. With increasing plasma exposure time, the field-effect mobility increase at first and then decrease, but the threshold voltage changes little. The a-Si:H TFT with a 6-min N₂ plasma treatment on SiN_x exhibited a field effect mobility of 1.37 cm²/Vs, a threshold voltage of 4.2 V and a subthreshold slope of 0.34 V/dec. It is found that surface roughness of SiN_x is decreased and N concentration in the SiN _x at the surface region decreases using the plasma treatment     

Low-temperature (⩽550°C) fabrication of poly-Si thin-filmtransistors

High performance n- and p-channel thin-film transistors (TFTs) have been fabricated in polycrystalline silicon films using a self-aligned-gate process without exceeding 550°C. This process features the use of polycrystalline Si_0.5Ge_0.5 for the gate material and high-dose H⁺ implantation for grain-boundary passivation so that shorter process times can be used. Low threshold voltages of 2.8 and -0.2 V, and high field-effect mobilities of 35 and 28 cm²/V-s, where achieved by the NMOS and PMOS devices, respectively. The performance of these devices is comparable to that of previously reported devices fabricated using process temperatures up to 600°C, and is adequate for large-area-display peripheral driver circuits. The significant reduction in maximum process temperature makes this process advantageous for the fabrication of CMOS circuits on large-area glass substrates     

Pentacene-based organic thin-film transistors

Organic thin-film transistors using the fused-ring polycyclic aromatic hydrocarbon pentacene as the active electronic material have shown mobility as large as 0.7 cm²/V-s and on/off current ratio larger than 10⁸; both values are comparable to hydrogenated amorphous silicon devices. On the other hand, these and most other organic TFT's have an undesirably large subthreshold slope. We show here that the large subthreshold slope typically observed is not an intrinsic property of the organic semiconducting material and that devices with subthreshold slope similar to amorphous silicon devices are possible     

High-temperature thin-film diamond field-effect transistorfabricated using a selective growth method

Selective growth of boron-doped homoepitaxial diamond films was achieved using sputtered SiO₂ as a masking layer. The hole mobility of selectively grown films varied between 210 and 290 cm² /V-s for hole concentration between 1.0×10¹⁴ and 6.9×10¹⁴ cm^-3. The technique was used to fabricate a thin-film diamond field-effect transistor operational at 300°C. The channel resistance of the device is an exponential function of temperature. In combination with the selective growth method, this device can be used as a starting point for the development of high-temperature diamond-based integrated circuits     

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n⁺ amorphous silicon (n⁺ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (V_TH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm²/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P⁺ ions) in the channel reduced the V_TH and increased the S value.     

High performance low-temperature poly-Si n-channel TFTs for LCD

High-performance poly-Si TFTs were fabricated by a low-temperature 600°C process utilizing hard glass substrates. To achieve low threshold voltage (V_TH) and high field-effect mobility (μ_FE), the conditions for low-pressure chemical vapor deposition of the active layer poly-Si were optimized. Effective hydrogenation was studied using a multigate (maximum ten divisions) and thin-poly-Si-gate TFTs. The crystallinity of poly-Si after thermal annealing at 600°C depended strongly on the poly-Si deposition temperature and was maximum at 550-560°C. The V_TH and μ_FE showed a minimum and a maximum, respectively, at that poly-Si deposition temperature. The TFTs with poly-Si deposited at 500°C and a 1000-Å gate had a V _TH of 6.2 V and μ_FE of 37 cm²/V-s. The high-speed operation of an enhancement-enhancement type ring oscillator showed its applicability to logic circuits. The TFTs were successfully applied to 3.3-in.-diagonal LCDs with integration of scan and data drive circuits     

High field-effect-mobility a-Si:H TFT based on high deposition-ratePECVD materials

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT's) having a field-effect mobility of 1.45 ±0.05 cm² /V·s and threshold voltage of 2.0±0.2 V have been fabricated from the high deposition-rate plasma-enhanced chemical vapor deposited (PECVD) materials. For this TFT, the deposition rates of a-Si:H and N-rich hydrogenated amorphous silicon nitride (a-SiN_1.5 :H) are about 50 and 190 nm/min, respectively. The TFT has a very high ON/OFF-current ratio (of more than 10⁷), sharp subthreshold slope (0.3±0.03 V/decade), and very low source-drain current activation energy (50±5 meV). All these parameters are consistent with a high mobility value obtained for our a-Si:H TFT structures. To our best knowledge, this is the highest field-effect mobility ever reported for an a-Si:H TFT fabricated from high deposition-rate PECVD materials     

Dependence of electron channel mobility on Si-SiO2interface microroughness

The effect of the Si-SiO₂ interface microroughness on the electron channel mobility of n-MOSFETs was investigated. The surface microroughness was controlled by changing the mixing ratio of NH₄ OH in the NH₄OH-H₂O₂-H₂O solution in the RCA cleaning procedure. The gate oxide was etched, following the evaluation of the electrical characteristics of MOS transistors, to measure the microroughness of the Si-SiO₂ interface with scanning tunneling microscopy (STM). As the interface microroughness increases, the electron channel mobility, which can be obtained from the current-voltage characteristics of the MOSFET, gets lower. The channel mobility is around 360 cm²/V-s when the average interface microroughness is 0.2 nm, where the substrate impurity concentration is 4.5×10¹⁷ cm^-3, i.e. the electron bulk mobility is 400 cm²/V-s. It goes down to 100 cm²/V-s when the interface microroughness exceeds 1 nm