电容式振动传感器谐波失真自检测接口ASIC设计

为实现电容式振动传感器的谐波失真测量,针对电容式振动传感器表头设计出一种开关电容型接口ASIC芯片,采用相同电极分时复用的方法,从而避免电容敏感与静电力反馈的馈通现象.对传感器敏感电容上下极板与中间质量块间的杂散电容导致的谐波失真进行了原理分析,可知传感器二次谐波与寄生电容成正比,三次谐波与寄生电容无关.提出采用电容阵列补偿、静电力平衡反馈式闭环电路结构进行传感器谐波失真抑制,并基于静电力原理提出一种新的电容式振动传感器谐波失真自检测方法,该方法无需精密振动台,仅需要低失真度电压信号源.实际测试结果显示,谐波失真检测精度可达到-83 dB.ASIC芯片采用2μm CMOS工艺流片,刻度因子为1.2 V/g（g为重力加速度,g=9.8 m/s2）,量程为±2g,噪声密度为3×10-6g/（Hz）～（1/2）,静态功耗为40 mW.测试结果证明,该电路达到高精度微加速度计系统设计要求,可以应用到地震监测、石油勘探等领域中.     

基于电磁激励的SOI-MEMS谐振式加速度计的闭环检测系统(英文)

介绍了一种基于电磁激励方式,采用基于绝缘体上硅的微电子机械系统(SOI-MEMS)加工方法制作谐振式加速度计及其闭环控制电路系统.传感器芯片制作采用的是SOI材料(10μm+2μm+290μm),利用MEMS加工工艺制作.当外界z轴方向加速度作用于加速度计时,加速度计的两根"H"型谐振梁因受到弯曲应力而产生谐振频率的漂移,通过检测谐振梁频率的变化标定加速度的大小.电磁激励检测方式有利于加速度计的最终闭环控制.闭环电路控制系统主要由增益放大部分、自动增益控制(AGC)电路缓冲系统和移相器组成.测试结果显示,当有1g重力加速度作用于加速度计,闭环电路可稳定输出检测正弦频率信号58.958 kHz,与开环扫频结果一致.加速度计的"H"型谐振梁空气中检测Q值约为400,灵敏度可达584 Hz/g.     

静电悬浮加速度计电容检测电路变压器桥路设计

静电悬浮加速度计用于测量非惯性力,是重力卫星的重要载荷,高精度重力场模型的获取对加速度计的分辨率要求很高。电容检测电路是加速度计的核心电路之一,其作用是通过测量差动电容的变化,反映检测质量块微小位移的变化,电容检测电路的噪声水平直接影响加速度计的分辨率。通过对电容检测电路的噪声分析,设计了变压器桥路,降低电容检测电路噪声。结果表明,变压器桥路输出阻抗越大,电容检测电路输出噪声越小,选取典型参数代入桥路输出阻抗公式进行仿真。当桥路谐振频率与电容检测信号工作频率相等时,输出阻抗达到最大。因此桥路设计所选取的参数,应满足使桥路谐振频率与电容检测信号工作频率相等,电容检测电路噪声能够大幅度降低。     

BD031 MEMS信号处理电路的研制及测试

本文报道了一个为电容式微加速度计传感器信号处理而设计的全集成化的BD031 CMOS MEM信号处理电路.电路设计采用了对信号的差分电容采样方式和过采样技术、前置采样放大器高增益和低噪声设计措施、可调节选通带宽的的低通滤波器及为提高电容噪声性能的带有虚开关结构的开关电容滤波器设计技术、可微调节增益(常规情况下恒定增益为2)的输出缓冲放大器、可调节振荡频率(正常情况下为800KHz)的本地CMOS时钟产生振荡器及为上述模拟电路提供基准电压和基准电流的基准电压源等设计技术、以及可以进行输入失调调节和对差分电容变化量△C的自测试电路.电路使用单一5伏电源,采用1.2微米、双多晶硅、双铝、N-阱CMOS工艺加工,芯片面积为2.82×3.61平方毫米.芯片性能测试表明其差分小电容变化量△C传感范围达到0.06pF-5pF、带宽为300Hz-5KHz.     

BD031 MEMS信号处理电路的研制及测试

本文报道了一个为电容式微加速度计传感器信号处理而设计的全集成化的BD031 CMOS MEM信号处理电路.电路设计采用了对信号的差分电容采样方式和过采样技术、前置采样放大器高增益和低噪声设计措施、可调节选通带宽的的低通滤波器及为提高电容噪声性能的带有虚开关结构的开关电容滤波器设计技术、可微调节增益(常规情况下恒定增益为2)的输出缓冲放大器、可调节振荡频率(正常情况下为800KHz)的本地CMOS时钟产生振荡器及为上述模拟电路提供基准电压和基准电流的基准电压源等设计技术、以及可以进行输入失调调节和对差分电容变化量△C的自测试电路.电路使用单一5伏电源,采用1.2微米、双多晶硅、双铝、N-阱CMOS工艺加工,芯片面积为2.82×3.61平方毫米.芯片性能测试表明其差分小电容变化量△C传感范围达到0.06pF-5pF、带宽为300Hz-5KHz.     

低功耗低相位噪声4.8GHz CMOS压控振荡器芯片设计

采用TSMC 0.18μm RF CMOS工艺设计并实现了一个应用于无线传感器网络射频前端频率综合器的低功耗、低相位噪声4.8GHz电感电容压控振荡器.此振荡器的核心电路采用电流源偏置的互补差分负阻结构,降低了电路对电源电压变化的灵敏度和功耗.电感电容谐振腔采用了降低相位噪声的设计方法.在不恶化相位噪声性能的前提下,核...     

扭摆式高g值微机械加速度计的设计优化与冲击校准

设计实现了一种扭摆式高g值微机械加速度计。微结构采用十字形扭梁减小横向效应,摆片两侧使用梳齿结构作为止档和阻尼器,6个敏感单元并联的方式提高基础电容量。有限元仿真得到表头谐振频率约为56kHz,前两阶模态分离比大于4,高过载能力10万g,微结构灵敏度为8.94E-6pF/g,基于SOG工艺流片后单侧基础电容约为3.6pF。分析了环形二极管电容检测电路的检测带宽问题,并设计了高g值加速度计的检测电路。搭建了霍普金森杆实验系统进行高g值的冲击校准,2万g范围内非线性度2%,5V供电下标度因数约为24.5μV/g。     

基于V/T变换的电容传感器新型电容测量电路

提出了一种基于V/T变换的用于电容传感器的电容测量电路。它将被测微小电容变化量转换成时间信号并由单片机进行处理 ,电路结构简单 ,电路中没有影响测量稳定性和产生零点漂移的元器件 ,大幅度地降低了测量过程中的噪声。     

基于跨阻放大器的动态微弱电容检测电路

基于MEMS技术的微电容超声传感器(CMUT),因具有易制造、易阵列化、噪声低、稳定性好以及批量化生产等众多优点,成为未来高频超声传感器发展的主要方向.本文介绍了微电容超声传感器的工作原理,提出了跨阻放大器检测电路,它能将电容信号转换为相应的电压信号(C/V转换),再通过放大、滤波得出电容的变化量.该电路能很好地抑制杂散电容的影响,有很好的线性和稳定性,在400kHz的超声波作用下的灵敏度为1.64mV/fF,基本满足对超声传感器电容变化量的检测.     

SOI高g值压阻式加速度传感器与工艺实现

基于SOI技术,利用电感耦合等离子体硅深加工,设计制备了一种新型平面内振动高g值压阻式加速度计.该加速度计包括X轴向与Y轴向单元,采用扇形敏感质量块平板内振动结构.对称的布局方式,有效地消除了灵敏度的交叉干扰,提高了传感器的测量精度.测试系统分析出加速度传感器的灵敏度是1.170 μV/g.研究表明该加速度传感器可实现对量程高达25×104g加速度的测量.     

基于PIC单片机的胶印机墨斗电机控制系统设计

以四色胶印机墨斗为平台,以PIC18F2580单片机为控制核心,设计了一套完整的直流电机闭环调速控制系统。详细设计了系统硬件电路,着重设计了与操作台和PC机通讯的CAN通讯接口电路、电机控制与驱动电路、电机位置闭环反馈电路和电机PWM调速电路,编写了系统的C语言驱动程序。经实验和实际环境下的运行证明,该系统具有良好的驱动性能、调速性能和抗电磁干扰性能,有利于降低成本,有利于国产胶印机的自动化、智能化进程,有良好的市场应用前景。     

A model for phase noise generation in amplifiers

In this paper, a model is presented for predicting the phase modulation (PM) and amplitude modulation (AM) noise in bipolar junction transistor (BJT) amplifiers. The model correctly predicts the dependence of phase noise on the signal frequency (at a particular carrier offset frequency), explains the noise shaping of the phase noise about the signal frequency, and shows the functional dependence on the transistor parameters and the circuit parameters. Experimental studies on common emitter (CE) amplifiers have been used to validate the PM noise model at carrier frequencies between 10 and 100 MHz     

Ultralow-noise readout circuit with an avalanche photodiode: toward a photon-number-resolving detector

The charge-integration readout circuit was fabricated to achieve an ultralow-noise preamplifier for photoelectrons generated in an avalanche photodiode with linear mode operation at 77 K. To reduce the various kinds of noise, the capacitive transimpedance amplifier was used and consisted of low-capacitance circuit elements that were cooled with liquid nitrogen. As a result, the readout noise is equal to 3.0 electrons averaged for a period of 40 ms. We discuss the requirements for avalanche photodiodes to achieve photon-number-resolving detectors below this noise level.     

基于有限元的三辊行星轧制力预测及分析

为预测三辊行星轧制力,建立了三维热力耦合有限元模型,用均匀设计法安排有限元模拟样本,采用基于LM算法的BP神经网络学习有限元轧制力结果,确定了轧制参数与轧制力的映射关系,并根据训练后的神经网络分析了摩擦系数、轧辊偏转角和轧辊转速对轧制力影响．预测结果表明：摩擦系数和轧辊偏转角对轧制力影响是多方面的,在高轧辊转速时,较大的摩擦系数有利于降低轧制力．     

Effect of clock offset on an impulse radio ultra wideband ranging system with comparators

Impulse radio ultra wideband (IR-UWB) can achieve high resolution in ranging because it uses a very short pulse with a duration of less than 1 ns. In order to reduce cost and power consumption, a ranging system with high-speed comparators has been proposed. In this system, it is necessary to reduce noise power through averaging the comparator outputs. The authors evaluate the effect of clock offset on the averaging process, and a two-stage averaging scheme for the IR-UWB ranging system is proposed. Through computer simulation, it is proved that the proposed scheme can reduce the effect of the clock offset with appropriate numbers of initial averaging.     

PSD 信号处理电路的研究

目的简化PSD信号处理电路,降低噪声信号和温漂的技术.方法用软件代替部分硬件电路的方法.结果简化了电路,提高了信噪比.结论这种方法适于多PSD计算机信号处理的智能测试系统.     

车辆驾驶室内噪声建模及分析

驾驶室内噪声是车辆乘坐舒适性的重要指标之一。以某型水泥搅拌车为例,综合考虑驾驶室外噪声源和悬置点振动源的影响,建立较全面的驾驶室声振耦合有限元分析模型。通过有限元仿真分析室内噪声响应和驾驶室结构吸声敏感特性。根据仿真结果提出改进措施,改进前后仿真计算结果与实验测得的结果较为吻合,改进后室内的降噪效果较为理想,降低3 dBA左右,并且低频噪声得到抑制。上述结果充分验证模型和降噪方法的有效性。     

Low phase noise operation of microwave oscillator circuits

In this paper, we describe a theoretical basis, leading to new results, on the general conditions to be fulfilled by oscillator circuits to achieve a very low phase noise. Three main conditions must be fulfilled by a transistor oscillator circuit to reach the minimum phase noise. The energy stored in the resonator must be maximum. Its transfer to the controlling voltage port of the transistor current source must be first maximized. A possible conversion noise at the transistor output port will be also minimized by maximizing the energy transferred to that port. The proposed method has been applied to an experimental oscillator set up with a PHEMT transistor. A state-of-the-art phase noise of -80 dBc/Hz at 100 Hz offset from carrier with a 1/f(3) slope has been measured at room temperature with a 9.2 GHz, oscillator. The application of these new results to free-running oscillator circuits with one-stage then multistage transistor amplifiers demonstrate clearly the validity of the design method. The efficiency of this design method and its ease of use represent a real breakthrough in the field of low noise transistor oscillator circuit design.     

An Electronic-Calibration Scheme for Logarithmic CMOS Pixels

Logarithmic cameras have the wide dynamic range required to image natural scenes and encode the important contrast information within the scene. However, the images from these cameras are severely degraded by a fixed pattern noise (FPN). Previous attempts to improve the quality of the images from these cameras by removing an additive FPN have led to disappointing results. Using an existing model for the response of logarithmic pixels, it is concluded that the residual FPN in these images is caused by gain variations between pixels. In order to reduce the effects of these variations, a readout circuit, which is based upon a differential amplifier, has been used. However, even with this readout circuit, high-quality images will only be obtained if each image is corrected to remove the effects of both gain and offset variations. Measurement results are presented that show that the quality of the output from the logarithmic pixels is significantly improved if an electronic-calibration procedure is used to correct for both types of variations. In fact, with this procedure, the contrast sensitivity of the logarithmic pixels becomes comparable to that of the human eye over five decades of illumination intensity.     

The maximal area of superconducting tunneling junction x-ray detectors determined by the required signal-to-noise ratio

The intrinsically high energy resolution of superconducting tunneling junctions (STJ) requires a low noise charge sensitive amplifier circuit. The noise sources of such a junction + amplifier circuit are discussed. The dominant noise sources are the series noise and the flicker noise of the FET input stage, amplified by the large input capacitance of the STJ-detector. Means to reduce this capacitance are discussed. Reducing the preamplifier noise by a factor of two and the height of the potential barrier of the insulating layer by two orders of magnitude, by keeping the large conductance of the junction constant, would allow an increase in junction area by a factor of 15.