基于gm/ID的CMOS模拟集成电路设计方法及应用

介绍一种基于gm/ID参数特性的模拟电路优化设计方法,并以CMOS两级运算放大器的设计为例具体阐述该方法的基本设计步骤和与传统设计方法相比的优势。该方法以晶体管的跨导和漏电流的比值gm/ID与反型系数IC的特性曲线作为设计参量来对电路进行设计。基于gm/ID的设计方法对晶体管工作在所有的工作区域均有效。实验仿真结果很好地验证了gm/ID设计方法的有效性。     

基于数字电路的二阶Σ-Δ调制微加速度计

为了简化模拟电路部分的设计,减少模拟电路的干扰,提出了一种基于数字电路的Σ-Δ调制微加速度计.在传统由纯模拟电路搭建的Σ-Δ接口电路基础上,将基于运算放大器的比例放大、微分、积分电路使用现场可编程门阵列(FPGA)进行实现.使用分立元件搭建了PCB板级电路,实现了采样频率为50 kHz的二阶Σ-Δ闭环调制接口电路.测试结果表明:该加速度计灵敏度为1.4 V/gn,系统基带内闭环噪声密度小于400 μgm/Hz1/2.     

宽频二阶程控低通滤波器的设计

设计了一种宽频二阶程控低通滤波器.二阶低通滤波电路由模拟乘法器、电流反馈运算放大器、可编程电阻网络及电容构成,充分利用了模拟乘法器和电流反馈运算放大器的优点,并通过主控电路调节数模转换电路的输出电压和低通滤波电路可编程电阻网络的值,实现截止频率程控.该滤波器具有截止频率高、信号处理范围宽、速度高等特点.     

一种三级CMOS运算放大器

运算放大器（OPERATIONAL AMPLIFIER）是模拟电路中最重要和最通用的单元电路之一。基于0.5 umCMOS混合工艺设计了一种三级CMOS运算放大器,它具有放大倍率高,静态功耗低,适合大规模集成等特点。     

一种用于微加速度计的低输入电容运算放大器

采用0.5μm CMOS工艺设计了一种低输入电容运算放大器。该运算放大器通过采用正反馈回路消除运算放大器输入管的密勒电容来实现低输入电容。分析了寄生电容对加速度计灵敏度的影响,并提出了一种采用低输入电容运算放大器的开环加速度计接口电路实现方法。结果表明:采用低输入电容运算放大器能够有效地提高加速度计灵敏度。     

基于 OPA820ID 的宽带低噪音放大器

本文设计制作一个5 V单电源供电的宽带低噪声放大器,输出为50Ω阻性负载.设计中采用高速运算放大器 OPA820ID 作为第一级放大电路,THS3091D 作为末级放大电路,利用 DC-DC 变换器 TPS61087DRC 为末级放大电路供电.在最大增益下,放大器的输入频率范围低至20Hz,高达5MHz.本设计放大器电压增益不小于40db,放大器最大不失真输出电压峰峰值大于等于10V,输出电压(峰峰值)测量范围为0.5~10V,测量相对误差小于5%.     

一种低压恒跨导轨对轨CMOS运算放大器设计

介绍了轨到轨恒定跨导运算放大器输入级电路设计。所提出的电路通过使用虚拟输入差分对动态地改变输入差分对的尾电流来获得恒定跨导gm。引起总跨导gm变化的因素是输入对和虚拟输入对在共模输入电压变化时不能同时生效,当输入对关闭时输入对的尾电流晶体管处于三极管区域当共模电压变化时,虚拟输入对将在输入对之前从截止区域进入亚阈值区域。在低电源电压设计中,此因素的影响更突出。为了解决这个问题,采用添加补偿电流源到每个虚拟输入差分对的尾电流晶体管,以降低跨导gm的变化。所设计的运算放大器输入级的gm变化误差约为±2%。     

ADI公司推出超低噪声超低失真的高速运算放大器

美国模拟器件公司推出一种新的高速运算放大器——AD8099,它能够将放大器设计中两个基本的误差源(电压噪声和谐波失真)都降至最低。AD8099采用一种先进电路结构专利技术,使其满足传统运算放大器差分输入级基本性能的同时又不牺牲其固有性能。这使得AD8099既能提供极低的电压噪声(0.95nV/(Hz)~(1/2))又能提供极低的失真(-90dB,在10MHz基频条件下),这种新器件在增益为10条件下具有1600V/μs转换速率和5GHz增益带宽乘积。当增益降为2时,其转换速率为600V/μs。     

ADI公司推出超低噪声超低失真高速运算放大器

全球领先的放大器供应商开创信号调理技术的新纪元美国模拟器件公司(AnalogDevices,Inc.,纽约证券交易所代码:ADI),近日在马萨诸塞州诺伍德市(Norwood,Massachusetts)推出一种新的高速运算放大器——AD8099,它能够将放大器设计中两个基本的误差源(电压噪声和谐波失真)都降至最低。AD8099采用一种先进电路结构专利技术,使其满足传统运算放大器差分输入级的基本性能的同时又不牺牲其固有性能。这使得AD8099既能提供极低的电压噪声(0.95nV/Hz)又能提供极低的失真(-90dB,在10MHz基频条件下),目前市场上还没有其它高速运算放大器能够达到…     

基于微生物传感器的恒电位仪电流积分电路的设计

为了隔离微生物传感器和读出电路,保证微电极信号的稳定,设计了一种恒电位仪电流积分电路.对电路中的CMOS差分运算放大器进行了噪声分析.在0.6 μm/Level 7 CMOS工艺条件下通过PSPICE 9.1进行模拟.仿真结果表明,采用恒电位仪电流积分电路使输入输出转换具有很好的线性关系.     

Design, fabrication, and characterization of a submicroelectromechanical resonator with monolithically integrated CMOS readout circuit

In this paper, we report on the main aspects of the design, fabrication, and performance of a microelectromechanical system constituted by a mechanical submicrometer scale resonator (cantilever) and the readout circuitry used for monitoring its oscillation through the detection of the capacitive current. The CMOS circuitry is monolithically integrated with the mechanical resonator by a technology that allows the combination of standard CMOS processes and novel nanofabrication methods. The integrated system constitutes an example of a submicroelectromechanical system to be used as a cantilever-based mass sensor with both a high sensitivity and a high spatial resolution (on the order of 10/sup -18/ g and 300 nm, respectively). Experimental results on the electrical characterization of the resonance curve of the cantilever through the integrated CMOS readout circuit are shown.     

Logic synthesis and testing techniques for switching nano-crossbar arrays

Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements logic, arithmetic, and memory elements by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of logic, arithmetic, and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of “Emerging Computing Models” or “Computational Nanoelectronics”, more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS.     

Theory and verification of operator design methodology

Non-recurring-engineering(NRE)and time-to-market play an increasingly important role in the field of IC design.Meanwhile,with the continuous development of IC manufacturing technology,it is necessary to propose a novel design methodology to shorten design cycle and enhance design efficiency.In this paper,operator design methodology(ODM)is presented and an H.264 encoder is implemented as a verification.According to the flow of ODM,the register transfer level(RTL)design of H.264 encoder has been accomplished with 15 man-months,which is lower than the average 19 man-months in the field of traditional application specific integrated circuit(ASIC)design.Moreover,with the advantage of operator design library,the design has a comparable performance with other ASIC implementations.The obtained design can support a real-time video encoding of 720p at 60 frames per second or 1080p at 30 frames per second,working at 167 MHz with SMIC 0.13 μm CMOS technology.These results provide good evidence for the practicability and efficiency of ODM.     

一种采用CDS电路的高精度温度传感器

采用相关双采(CDS)电路,设计了一种新颖的高精度温度传感器,该温度传感器可用于CMOS集成电路的过温检测。传感器的温度感应部分仅采用9个MOS管,其输出的包含温度信息的电流信号通过一个电容进行积分,随后采用CDS电路对积分信号进行消除kTC噪声和降低1/f噪声处理,并同时进行采样处理,得到与温度成正比的电压信号。该新型温度传感器与标准CMOS工艺兼容,且仿真结果表明其具有较高的性能。     

微悬臂梁传感器以及读出电路的单片集成

提出了一种基于SOI技术的微悬臂梁传感器集成化方案,并从传感器信号调理电路的设计和集成化工艺设计方面论证了该方案的可行性。微悬臂梁传感器集成化系统主要包括惠斯通电桥阵列以及微悬臂梁传感器的信号调理电路。信号调理电路部分包括温补电流源、时分多路选择器和两级仪用放大器。测量的结果证实了我们单片集成的可行性。     

Specification and implementation of a digital Hopfield-typeassociative memory with on-chip training

The definition of the requirements for the design of a neural network associative memory, with on-chip training, in standard digital CMOS technology is addressed. Various learning rules that can be integrated in silicon and the associative memory properties of the resulting networks are investigated. The relationships between the architecture of the circuit and the learning rule are studied in order to minimize the extra circuitry required for the implementation of training. A 64-neuron associative memory with on-chip training has been manufactured, and its future extensions are outlined. Beyond the application to the specific circuit described, the general methodology for determining the accuracy requirements can be applied to other circuits and to other autoassociative memory architectures.     

基于门控时钟的寄存器传输级功耗优化

随着深亚微米技术的发展,功耗已经成为现代超大规模集成电路设计中的一个主要设计约束.本文在设计多点控制协议MPCP模块中,采用插入门控时钟这一技术以降低芯片功耗.针对插入门控寄存器造成测试很难控制这个问题,采取在锁存器的前后加入控制点的方法,解决了由于插入门控时钟而对可测性造成的影响.最后,使用SMIC的0.25um CMOS工艺,并用Synopsys的power complier进行功耗优化,达到了很好的效果.     

0.2 mT Residual offset of CMOS integrated vertical Hall sensors

A residual offset lower than 0.2 mT is obtained with a CMOS integrated vertical Hall (VH)-sensor microsystem. Instead of the conventional design with five contacts in the sensor active area, we apply a layout with only four contacts. This design shows a higher effectiveness for the offset reduction by the spinning current (SC) method, because of the symmetrical current flow for the two different biasing phases. Furthermore, to obtain very low offsets, coupled sensors are integrated with the spinning current electronics in the final microsystem. A sensitivity up to S_v=0.025 V/VT is achieved for these sensors without any additional technology step. The measured output noise level of the integrated microsystem (1.9 μT/ ) is in the usual range of commercial integrated Hall-sensors. Our new developments open the way to the realization of compact, low-cost angular sensors with 10 bit resolution.     

FP──VLSI自动综合系统

ＦＰ—ＶＬＳＩ自动综合系统是一个集成化的ＶＬＳＩ自动设计工具，它能完成从并行算法到脉动算法到脉动结构再到逻辑结构最后到ＣＭＯＳ版图的自动综合过程．ＦＰ—ＶＬＳＩ系统以脉动阵列为ＶＬＳＩ的体系结构，采用具有良好代数性质的ＦＰ／Ｂ语言作为各层次的描述语言，通过程序变换进行综合和优化．该系统支持形式化的ＶＬＳＩ设计方法，能保证设计结果的正确性．     

Hierarchical design and test of integrated microsystems

This article presents emerging results of an integrated mixed-domain design methodology similar to the mixed-signal design methodologies in the VLSI community. This methodology is based on a hierarchical mixed-domain design representation and includes a Spice-like nodal simulation environment, an “on-the-fly” component layout-synthesis module, a layout extractor for design verification, and a fault model generator for test methodology development