Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors

In deep submicrometer MOSFETs the device performance is limited by the parasitic capacitance and resistance. Hence a circuit model is needed to treat these effects correctly. In this work, we have developed circuit models for the parasitic capacitances in conventional and high-K gate dielectric MOS transistors by taking into account the presence of source/drain contact plugs. The accuracy of the model is tested by comparing the modeled results with the results obtained from three-dimensional (3-D) Monte-Carlo simulations and two-dimensional (2-D) device simulations over a wide range of channel length and oxide thickness. The model is also used to study the dependence of parasitic capacitance on gate length, gate electrode thickness, gate oxide thickness, gate dielectric constant, and spacer width.     

14 nm FinFET栅围寄生电容的建模与拟合

提出了一种基于保角映射方法的14 nm鳍式场效应晶体管(FinFET)器件栅围寄生电容建模的方法。对FinFET器件按三维几何结构划分寄生电容的种类,再借助坐标变换推导出等效电容计算模型,准确表征了不同鳍宽、鳍高、栅高和层间介质材料等因素对寄生电容的依赖关系。为了验证该寄生电容模型的准确性,对不同结构参数的寄生电容进行三维TCAD仿真。结果表明,模型计算结果与仿真结果的拟合度好,准确地反映了器件结构与寄生电容之间的依赖关系。     

A floating well method for exact capacitance-voltage measurement of nano technology

Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.     

3 nm环栅场效应管射频小信号等效电路模型

针对3 nm环栅场效应晶体管,提出了一种射频小信号等效电路模型及基于有理函数拟合的解析模型参数提取方法。首先,在关态条件下提取不受偏置影响的非本征栅/源/漏极电阻、栅到源/漏电容、衬底电容和电阻。然后,在不同偏置条件下提取受偏置影响的本征模型参数。使用Sentaurus TCAD和Matlab对器件进行仿真并拟合得到相关参数,在ADS中验证等效电路模型。结果表明,在10 MHz~300 GHz频率范围内,TCAD仿真与等效电路仿真S参数的最大误差低于2.69%,证实了所建立模型及建模方法的准确性。该项研究成果对射频集成电路设计具有参考价值。     

Analysis of the channel inversion layer capacitance in the very thin-gate IGFET

As the gate insulator thickness approaches the channel thickness, the gate capacitance is speculated to be smaller than its gate insulator capacitance. The gate capacitance of the thin-gate IGFET is calculated using Maxwell-Boltzmann and Fermi-Dirac statistics and is experimentally measured. The results show that the gate capacitance approaches the gate insulator capacitance regardless of the gate thickness within the practical range (T_{ox} > 50Å). To explain why the channel thickness is not reflected in the measured gate capacitance, the channel inversion layer capacitance is analyzed numerically. Based on that, its effects on the gate capacitance are discussed quantitatively and an equivalent circuit is proposed.     

An improved two-frequency method of capacitance measurement forSrTiO3 as high-k gate dielectric

An improved two-frequency method of capacitance measurement for the high-k gate dielectrics is proposed. The equivalent circuit model of the MOS capacitor including the four parameters of intrinsic capacitance, loss tangent, parasitic series inductance, and series resistance is developed. These parameters can be extracted by independently measuring the capacitor at two different frequencies. This technique is demonstrated for high-k SrTiO₃ gate dielectrics and the results show that the calibrated capacitances are invariant over a wide range of frequency. In addition, the extracted loss tangent, inductance and resistance are independent on gate voltage and frequency. The effect of series resistance on the frequency dispersion of the capacitance can be also explained by this model. These results indicate that this modified technique can be incorporated in the routine capacitance-voltage (C-V) measurement procedure providing the physically meaningful data for the high-k gate dielectrics     

Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era

In this paper, we propose a methodology to model and optimize FinFET devices for robust and low-power SRAMs. We propose to optimize the gate sidewall offset spacer thickness to simultaneously minimize leakage current and drain capacitance to on-current ratio in FinFET. With the source/drain extension doping controlled at the outer edges of the spacer, the thickness of the spacer determines the channel length. Optimization reduces the sensitivity of the device threshold voltage to the fluctuations in silicon thickness (by 32%) and gate length (by 73%). Our analysis shows that optimization of spacer thickness results in 65% reduction in SRAM cell leakage and improves cell read-failure probability (by 200 X) compared to conventional FinFET SRAM. Access time of an SRAM cell designed with optimized devices is comparable to conventional SRAM. We also compared the optimized-spacer-thickness SRAM cell with one designed using longer gate length and minimum-spacer-thickness transistors. The long-channel-device-based SRAM cell is marginally robust than optimized SRAM; however, increased gate-edge direct-tunneling leakage and parasitic capacitances degrade the power consumption and access time.     

Modeling and optimization of fringe capacitance of nanoscale DGMOS devices

We analyze the impact of gate electrode thickness and gate underlap on the fringe capacitance of nanoscale double-gate MOS (DGMOS) transistors. We propose an analytical fringe capacitance model considering gate underlap and finite source/drain length. A comparison with the simulation results show that the model can accurately estimate the fringe capacitance of the device. We show that an optimum gate underlap can significantly reduce the fringe capacitance resulting in higher performance and lower power consumption. Also, the effects of process variation in gate underlap devices are discussed. Simulation results on a three-stage ring oscillator show that with optimum gate underlap 32% improvement in delay can be achieved.     

A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-/spl kappa/ gate-dielectric MOSFETs

A grounded lamination gate (GLG) structure for high-/spl kappa/ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.     

功率VDMOS器件的ESD瞬态模型

基于对功率VDMOS器件ESD保护及初始条件的分析,建立了VDMOS器件的ESD保护等效电路,分析了ESD响应过程,得到功率VDMOS器件的ESD瞬态模型. 分析结果表明,该模型准确地描述了功率VDMOS器件的ESD瞬态放电过程,解决了以往模型中初始条件分析不足等问题. 借助该模型,获得ESD器件的等效电阻和击穿电压、VDMOS的栅极输入电阻、栅源电容、栅氧厚度等与功率VDMOS器件抗ESD能力的关系,为功率VDMOS器件的抗ESD保护设计提供重要指导.     

The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs

This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied     

具有高掺杂表面层和阶梯栅结构SiC MESFETs双沟道器件研究

An improved dual-channel 4H-SiC MESFET with high doped n-type surface layer and step-gate structure is proposed, and the static and dynamic electrical performances are analyzed.A high doped n-type surface layer is applied to obtain a low source parasitic series resistance, while the step-gate structure is utilized to reduce the gate capacitance by the elimination of the depletion layer extension near the gate edge, thereby improving the RF characteristics and still maintaining a high breakdown voltage and a large drain current in comparison with the published SiC MESFETs with a dual-channel layer.Detailed numerical simulations demonstrate that the gate-to-drain capacitance, the gate-to-source capacitance, and the source parasitic series resistance of the proposed structure are about 4%, 7%, and 18% smaller than those of the dual-channel structure, which is responsible for 1.4 and 6 GHz improvements in the cut-off frequency and the maximum oscillation frequency.     

绝缘体上硅FinFET亚阈值摆幅研究

在新型多栅器件栅电容模型的研究中,量子电容随着沟道长度及栅氧化层厚度的不断减小而变得越发不可忽略。推导了基于绝缘体上硅(SOI)工艺技术的鳍式场效应晶体管(FinFET)的量子电容,并通过构建囊括量子电容的内部电容网络模型推导了亚阈值摆幅。采用Matlab软件,仿真验证了量子电容对亚阈值摆幅的影响。提出了亚阈值摆幅的优化方法,为如何选取合适的器件尺寸来优化某个特定设计目标的性能提供了指导。     

A new pinched-off cold-FET method to determine parasiticcapacitances of FET equivalent circuits

A new pinched-off cold FET method to extract the parasitic capacitances of FETs is proposed in this paper. The method is based on a physically meaningful depletion-layer model and the theoretical analysis of the two-port network for the pinched-off cold FETs. The parasitic gate capacitance (C_pg) and the parasitic drain capacitance (C _pd) of FETs are extracted using the linear regression technique associated with the frequency responses of Y-parameters. The extraction method can be applied to the small-signal equivalent-circuit modeling of the FETs including MESFETs, heterojunction FETs, and high-electron-mobility transistors. According to the new analytical method, the simulated S-parameters exhibit great agreement with the measured S-parameters for the equivalent-circuit models of FETs     

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

FinFET器件的集约阈电压模型

对FinFET器件(或称三栅MOSFET器件)的二维截面做了解析静电学分析以得出阈电压的计算公式.结果显示,由于三栅结构在高度方向的限制作用,需要引入一个H系数来修正栅电容,随着高度不断变大,它渐近于双栅MOSFET器件的情况.由该解析模型得出的电势分布与数值模拟结果吻合.提出了一个包含量子效应的Fin-FET器件的集约阈电压模型,结果表明,当高度或者顶栅的氧化层厚度变小时,栅电容及阈电压都会上升,这与FinFET设计时发现的趋势是相符合的.     

A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs

A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance $C_{rm of}$ dominates around 25% of the intrinsic gate capacitance $(C_{rm gint})$ in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor $C_{rm of}/C_{rm gint}$ above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design.      

An analytical approach to the capacitance-voltage characteristicsof double-heterojunction HEMTs

The two-dimensional electron gas concentration and capacitance in AlGaAs/GaAs/AlGaAs double-heterojunction high-electron-mobility transistors (DH-HEMTs) are calculated as a function of gate voltage using simple iterative solutions of analytical equations. The results show very good agreement with experimental data, as well as with characteristics predicted by complex numerical methods. The calculations are extended to predict the capacitance-voltage characteristics in the presence of parasitic conduction when the gate does not fully control the two-dimensional gas. The developed charge control and capacitance models are easy and inexpensive to run. They are therefore very useful for microwave circuit designs. Furthermore, they can be used for performance prediction and design optimization of DH-HEMTs. The influence of technological parameters, such as layer thickness and aluminum composition, on device performance are presented