SiC电力电子器件研究现状及新进展

由于硅材料本身的限制,传统硅电力电子器件性能已经接近其极限,碳化硅(SiC)器件的高功率、高效率、耐高温、抗辐照等优势逐渐突显,成为电力电子器件一个新的发展方向.综述了SiC材料、SiC电力电子器件、SiC模块及关键工艺的研究现状,重点从材料、器件结构、制备工艺等方面阐述了SiC二极管、金属氧化物半导体场效应晶体管(MOSFET)、结晶型场效应晶体管(JFET)、双极结型晶体管(BJT)、绝缘栅双极晶体管(IGBT)及模块的研究进展.概述了SiC材料、SiC电力电子器件及模块的商品化情况,最后对SiC材料及器件的发展趋势进行了展望.     

The Effects of Implant Activation Anneal on the Effective Inversion Layer Mobility of 4H-SiC MOSFETs

In this paper, we investigate the effective inversion layer mobility of lateral 4H-SiC metal oxide semiconductor field-effect transistors (MOSFETs). Initially, lateral n-channel MOSFETs were fabricated with three process splits to investigate phosphorus implant activation anneal temperatures of 1200, 1650, and 1800°C. Mobility results were similar for all three temperatures (using a graphite cap at 1650°C and 1800°C). A subsequent experiment was performed to determine the effect of p-type epi-regrowth on the highly doped p-well surface. The negative effects of the high p-well doping are still seen with 1500 ? p-type regrowth, while growing 0.5 μm or more appears to be sufficient to grow out of the damaged area. A continuing series of tests are being conducted at present.     

Comparative hall measurements on wet- and dry-oxidized 4H-SiC MOSFETs

Hall measurements have been used to compare the properties of 4H-SiC inversion-mode MOSFETs with “wet” and “dry” gate oxides. While the field-effect mobilities were approximately 3–5 cm²/Vs, the Hall mobilities in 4H-SiC MOSFETs in the wet and dry oxide samples were approximately 70–80 cm²/Vs. The dry-oxidized metal oxide semiconductor field effect transistors (MOSFETs) had a higher transconductance, improved threshold voltage, improved subthreshold slope, and a higher inversion carrier concentration compared to the wet-oxidized MOSFETs. The difference in characteristics between the wet- and the dry-oxidized MOSFETs is attributed to the larger fixed oxide charge in the dry oxide sample and a higher interface trap density in the wet oxide sample.     

A New Degradation Mechanism in High-Voltage SiC Power MOSFETs

The phenomenon of recombination-induced stacking faults in high-voltage p-n diodes in SiC has been previously shown to increase the forward voltage drop due to reduction of minority carrier lifetime. In this paper, it has been shown that, for the first time, this effect is equally important in unipolar devices such as high-voltage MOSFETs. If the internal body diode is allowed to be forward biased during the operation of these devices, then the recombination-induced SFs will reduce the majority carrier conduction current and increase the leakage current in blocking mode. The effect is more noticeable in high-voltage devices where the drift layer is thick and is not expected to impact 600-1200-V devices.     

SiC power-switching devices-the second electronics revolution?

Silicon carbide (SiC) offers significant advantages for power-switching devices because the critical field for avalanche breakdown is about ten times higher than in silicon. SiC power devices have made remarkable progress in the past five years, demonstrating currents in excess of 100 A and blocking voltages in excess of 19000 V. In this paper we describe the latest progress in three classes of SiC devices: diodes (p-i-n and Schottky), transistors (junction field-effect transistor, metal-oxide-semiconductor field-effect transistor, and bipolar junction transistor), and thyristors (gate turn-off).     

Effect of processing conditions on inversion layer mobility and interface state density in 4H−SiC MOSFETs

N-channel, inversion mode MOSFETs have been fabricated on 4H−SiC using different oxidation procedures, source/drain implant species and implant activation temperature. The fixed oxide charge and the field-effect mobility in the inversion layer have been extracted, with best values of 1.8×10¹² cm⁻² and 14 cm²/V-s, respectively. The interface state density, D_it close to the conduction band of 4H−SiC has been extracted from the subthreshold drain characteristics of the MOSFETs. A comparison of interface state density, inversion layer mobility and fixed oxide charges between the different processes indicate that pull-out in wet ambient after reoxidation of gate oxide improves the 4H−SiC/SiO₂ interface quality.     

A field-effect electron mobility model for SiC MOSFETs including high density of traps at the interface

Besides its favorable physical properties, high performant MOSFETs (metal-oxide-semiconductor field-effect transistors) fabrication in silicon carbide (SiC) remains an open issue due to their low channel mobility values. The effect of charge trapping and the scattering at interface states have been invoked as the main reasons for mobility reduction in SiC thermal oxidized MOS gated devices. In this paper, we propose a compact electron mobility model based on the well-established Lombardi mobility model to reproduce the mobility degradation commonly observed in these SiC devices. Using 2D electrical simulations along with the proposed model and taking into account interface traps Coulomb scattering, the experimental field-effect mobility of 4H-SiC MOSFET devices has been fitted with a good agreement.     

碳化硅电力电子器件及其制造工艺新进展

评述了各种碳化硅电力电子器件研究开发的最新进展及其发展前景,指出碳化硅的优势不仅仅限于能提高功率开关器件的电压承受能力、高温承受能力和兼顾频率与功率的能力,还在于能大幅度降低器件的功率损耗,使电力电子技术的节能优势得以更加充分地发挥.针对碳化硅材料的特殊性和实现碳化硅器件卓越性能的需要,分析了器件工艺当前亟待解决的问题.     

SiC JBS二极管和SiC MOSFET的空间辐照效应及机理

基于第六代650 V碳化硅结型肖特基二极管(SiC JBS Diode)和第三代900 V碳化硅场效应晶体管(SiC MOSFET),开展SiC功率器件的单粒子效应、总剂量效应和位移损伤效应研究。20～80 MeV质子单粒子效应实验中,SiC功率器件发生单粒子烧毁(SEB)时伴随着波浪形脉冲电流的产生,辐照后SEB器件的击穿特性完全丧失。SiC功率器件发生SEB时的累积质子注量随偏置电压的增大而减小。利用计算机辅助设计工具(TCAD)开展SiC MOSFET的单粒子效应仿真,结果表明,重离子从源极入射器件时,具有更短的SEB发生时间和更低的SEB阈值电压。栅-源拐角和衬底-外延层交界处为SiC MOSFET的SEB敏感区域,强电场强度和高电流密度的同时存在导致敏感区域产生过高的晶格温度。SiC MOSFET在栅压偏置(U_GS=3 V,U_DS=0 V)下开展钴源总剂量效应实验,相比于漏压偏置(U_GS=0 V,U_DS=300 V)和零压偏置(U_GS=U_DS=0...     

碳化硅器件发展概述

概要介绍了第三代半导体材料碳化硅(SiC)在高温、高频、大功率器件应用方面的优势,结合国际上SiC肖特基势垒二极管,PiN二极管和结势垒肖特基二极管的发展历史,介绍了SiC功率二极管的最新进展,同时对我国宽禁带半导体SiC器件的研究现状及发展方向做了概述及展望。     

Extraction of SiO2/SiC interface trap profile in 4H- and 6H-SiC metal-oxide semiconductor field-effect transistors from subthreshold characteristics at 25°C and 150°C

The profile of trap density at the SiO₂/SiC interface in SiC metal-oxide semiconductor field-effect transistors (MOSFETs) is critical to study the channel electron mobility and evaluate device performance under various processing and annealing conditions. In this work, we report on our results in determining the interface trap density in 4H- and 6H-SiC MOSFETs annealed in dry O₂, NO, and CO₂, respectively, based on the device transfer and currentvoltage characteristics in the subthreshold region at 25°C and 150°C. We also studied electron field-effect mobility, fixed oxide charge, and gate leakage in those devices.     

Compact models for silicon carbide power devices

Compact silicon carbide (SiC) power semiconductor device models for circuit simulation have been developed for power Schottky, merged-PiN-Schottky, PiN diodes, and MOSFETs. In these models, the static and dynamic performance of the power SiC devices requires specific attention to the low-doped, voltage blocking drift region; the channel transconductance in MOS devices; the relatively low-intrinsic carrier concentration; the incomplete ionization of dopants; and the temperature dependent material properties. The modeling techniques required to account for each of these characteristics are described.     

Fabrication of self-aligned graded junction termination extensions with applications to 4H-SiC P-N diodes

The properties of SiC make this wide band-gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices, such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc., all of which require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power-handling capabilities. In this paper, we describe a technique for fabricating a graded junction termination extension (GJTE) that is effective and self-aligned, a feature that simplifies the implantation process during fabrication and, therefore, has the potential to reduce production costs. Implanted anode p-n diodes fabricated using this technique on 10-μm thick n⁻ epitaxial layer had a maximum breakdown voltage of 1830 V. This was comparable to the ideal parallel-plane breakdown of 1900 V predicted by numerical simulation.     

A 1-MHz hard-switched silicon carbide DC-DC converter

Silicon Carbide (SiC) is a wide bandgap semiconductor material that offers performance improvements over Si for power semiconductors with accompanying benefits for power electronics applications that use these semiconductors. The wide bandgap of SiC results in higher junction forward voltage drops, so SiC is best suited for majority carrier devices such as field effect transistors (FETs) and Schottky diodes. The wide bandgap of SiC results in it having a high breakdown electric field, which in turn results in lower resistivity and narrower drift regions in power devices. This dramatically lowers the resistance of the drift region and means that SiC devices with substantially less area than their corresponding Si devices can be used. The lower device area reduces the capacitance of the devices enabling higher frequency operation. Here, the results from a 1-MHz hard-switched dc-dc converter employing SiC JFETs and Schottky diodes will be presented. This converter was designed to convert 270Vdc to 42Vdc such as may be needed in future electric cars. The results provide the performance obtained at 1MHz and demonstrate the feasibility of a hard-switched dc-dc converter operating at this frequency.     

Reliability and performance limitations in SiC power devices

Despite silicon carbide’s (SiC’s) high breakdown electric field, high thermal conductivity and wide bandgap, it faces certain reliability challenges when used to make conventional power device structures like power MOS-based devices, bipolar-mode diodes and thyristors, and Schottky contact-based devices operating at high temperatures. The performance and reliability issues unique to SiC discussed here include: (a) MOS channel conductance/gate dielectric reliability trade-off due to lower channel mobility as well as SiC–SiO₂ barrier lowering due to interface traps; (b) reduction in breakdown field and increased leakage current due to material defects; and (c) increased leakage current in SiC Schottky devices at high temperatures.Although a natural oxide is considered a significant advantage for realizing power MOSFETs and IGBTs in SiC, devices to date have suffered from poor inversion channel mobility. Furthermore, the high interface state density presently found in the SiC–SiO₂ system causes the barrier height between SiC and SiO₂ to be reduced, resulting in increased carrier injection in the oxide. A survey of alternative dielectrics shows that most suffer from an even smaller conduction band offset at the SiC–dielectric interface than the corresponding Silicon–dielectric interface and have a lower breakdown field strength than SiO₂. Thus, an attractive solution to reduce tunneling such as stacked dielectrics is required.In Schottky-based power devices, the reverse leakage currents are dominated by the Schottky barrier height, which is in the 0.7–1.2 eV range. Because the Schottky leakage current increases with temperature, the SiC Schottky devices have a reduction in performance at high temperature similar to that of Silcon PN junction-based devices, and they do not have the high temperature performance benefit associated with the wider bandgap of SiC.Defects in contemporary SiC wafers and epitaxial layers have also been shown to reduce critical breakdown electric field, result in higher leakage currents, and degrade the on-state performance of devices. These defects include micropipes, dislocations, grain boundaries and epitaxial defects. Optical observation of PN diodes undergoing on-state degradation shows a simultaneous formation of mobile and propagating crystal stacking faults. These faults nucleate at grain boundaries and permeate throughout the active area of the device, thus degrading device performance after extended operation.     

Impact of switching frequencies on the TID response of SiC power MOSFETs

Different switching frequencies are required when SiC metal-oxide-semiconductor field-effect transistors(MOSFETs)are switching in a space environment.In this study,the total ionizing dose(TID)responses of SiC power MOSFETs are investig-ated under different switching frequencies from 1 kHz to 10 MHz.A significant shift was observed in the threshold voltage as the frequency increased,which resulted in premature failure of the drain-source breakdown voltage and drain-source leakage current.The degradation is attributed to the high activation and low recovery rates of traps at high frequencies.The results of this study suggest that a targeted TID irradiation test evaluation method can be developed according to the actual switching fre-quency of SiC power MOSFETs.     

Impact of the gate driver voltage on temperature sensitive electrical parameters for condition monitoring of SiC power MOSFETs

Condition monitoring using temperature sensitive electrical parameters (TSEPs) is widely recognized as an enabler for health management of power modules. The on-state resistance/forward voltage of MOSFETs, IGBTs and diodes has already been identified as TSEPs by several researchers. However, for SiC MOSFETs, the temperature sensitivity of on-state voltage/resistance varies depending on the device and is generally not as high as in silicon devices. Recently the turn-on current switching rate has been identified as a TSEP in SiC MOSFETs, but its temperature sensitivity was shown to be significantly affected by the gate resistance. Hence, an important consideration regarding the use of TSEPs for health monitoring is how the gate driver can be used for improving the temperature sensitivity of determined electrical parameters and implementing more effective condition monitoring strategies. This paper characterizes the impact of the gate driver voltage on the temperature sensitivity of the on-state resistance and current switching rate of SiC power MOSFETs. It is shown that the temperature sensitivity of the switching rate in SiC MOSFETs increases if the devices are driven at lower gate voltages. It is also shown, that depending on the SiC MOSFET technology, reducing the gate drive voltage can increase the temperature sensitivity of the on-state resistance. Hence, using an intelligent gate driver with the capability of customizing occasional switching pulses for junction temperature sensing using TSEPs, it would be possible to implement condition monitoring more effectively for SiC power devices.     

Interfacial effects during GaN growth on 6H-SiC

GaN growth on 6H-SiC was investigated for heterojunction device applications. Dopant diffusion and surface reactions were discovered at the GaN/SiC heterojunction. A systematic study was therefore conducted focusing on: 1) SiC substrate preparation, 2) SiC nitridation; the effect of flowing ammonia (NH₃) at 1050°C on the SiC, and 3) the conductivity type and carrier concentration of the SiC substrate. Atomic force microscopy measurements revealed that the SiC substrates became smoother after the nitridation process possibly due to nitrogen chemisorption and etching. Current-voltage and capacitance-voltage measurements on Cr-Schottky diodes made on SiC revealed evidence for an increased potential barrier in the nitrided samples that can be explained by an interfacial monolayer ofSiN_x. Furthermore, we compared GaN/SiC heterojunction n-n and n-p diodes made from direct and selective GaN growth. Capacitancevoltage measurements on GaN/SiC n-p heterojunctions indicate that the effective doping in the junction increases as the growth temperature increases. Secondary ion mass spectrometry measurements exposed a tail of Al in the GaN due to acceptor out-diffusion from the p-SiC.     

Spatial Localization of Carrier Traps in 4H-SiC MOSFET Devices Using Thermally Stimulated Current

Carrier traps in 4H-SiC metal–oxide–semiconductor (MOS) capacitor and transistor devices were studied using the thermally stimulated current (TSC) method. TSC spectra from p-type MOS capacitors and n-channel MOS field-effect transistors (MOSFETs) indicated the presence of oxide traps with peak emission around 55 K. An additional peak near 80 K was observed due to acceptor activation and hole traps near the interface. The physical location of the traps in the devices was deduced using a localized electric field approach. The density of hole traps contributing to the 80-K peak was separated from the acceptor trap density using a gamma-ray irradiation method. As a result, hole trap density of N _t,hole = 2.08 × 10¹⁵ cm⁻³ at 2 MV/cm gate field and N _t,hole = 2.5 × 10¹⁶ cm⁻³ at 4.5 MV/cm gate field was extracted from the 80-K TSC spectra. Measurements of the source-body n ⁺–p junction suggested the presence of implantation damage in the space-charge region, as well as defect states near the n ⁺ SiC substrate.     

Power cycling issues and challenges of SiC-MOSFET power modules in high temperature conditions

Silicon carbide (SiC) MOSFETs power modules are very attractive devices and are already available in the market. Nevertheless, despite technological progress, reliability remains an issue and reliability tests must be conducted to introduce more widely these devices into power systems. Because of trapping/de-trapping phenomena at the SiC/SiO₂ interface that lead to the shift of threshold voltage, test protocols based on silicon components cannot be used as is, especially in high temperature conditions. Using high temperature SiC MOSFET power modules, we highlight the main experimental difficulties to perform power cycling tests. These reversible physical mechanisms preclude the use of temperature sensitive parameters (TSEP) for junction temperature measurements, so we set up fiber optic temperature sensors for this purpose. Moreover, these degradation phenomena lead to difficulties in both controlling the test conditions and seeking for reliable aging indicator parameters. Finally, a power cycling test protocol at high temperature conditions is proposed for such devices.