Performance of a digital stereo FM modulator with reduced outputresolution

A digital stereo FM modulator has been built using a direct digital synthesiser (DDS). The system incorporates a digital stereo generator to provide the modulating signal. The stereo generator was sampled at 228 kHz and interpolation by 2 was carried out to move the unwanted FM sidebands further away from the FM carrier, in order to facilitate filtering. The paper presents the effects of quantisation noise on the system output by reduction in output resolution. Demodulation has been carried out so that the signal to noise and distortion ratios (SINAD) could be measured for all spectral components ⩽53 kHz with different monotone modulation frequencies and varying output resolution. An FM simulation of this process has been developed and the FM spectra produced by it are shown to match the experimental spectra almost exactly. These spectra complied with broadcast standards even with as little as a 6 bit output. The experimental system, with a 10 bit output, gives a SINAD performance which is ⩾77 dB     

D/A转换在System View环境下的仿真及硬件实现

针对模拟信号在传输介质中优于数字信号,而设计数模转换模块。首先用System View对DAC模块进了仿真。然后设计的D/A转换的硬件电路。通过设计了一个前置的串并转换电路,不仅可以实现8位并行数字信号的D/A转换,还可实现8位串口输入数字信号的D/A转换。在输出端,接入一个有源二阶低通滤波电路,使模拟输出更为平滑。达到了在实际范围内较低波形衰减的目的。     

A 14-bit monotonic NMOS D/A converter

A new configuration of a 14-bit digital-to-analog (D/A) converter has been fabricated as an experimental monolithic NMOS chip. The concept utilizing two cascaded resistor strings delivers an inherent 14 bit monotonicity and a static voltage output signal. The small chip size of about 8.5 mm/SUP 2/ and the saving of external components make the converter applicable for low-cost high-resolution control loop systems. A modified test chip is also described which has been provided as a step into the field of accurate monolithic converters needed for digital audio systems. A voltage output settling time less than 10 /spl mu/s and a linearity at the 12 bit level have been achieved.     

Application of the CCIR Bit Error Ratio Recommendation to Real Digital Radio Paths

The CCIR (International Radio Consultative Committee) has published a recommendation on the "Allowable bit error ratios at the output of the hypothetical reference digital path for radio-relay systems for telephony" (Recommendation 594). It has been normal practice to augment such a recommendation on performance with a corresponding recommendation for so-called real digital paths, as discussed in CCIR Report 930. This correspondence proposes and justifies the form that such a recommendation could take.     

一种基于统计的流水线ADC数字后台校准方法

高精度流水线ADC的设计需要校准技术来提高其转换精度.基于统计的数字后台校准方法无需校准信号,直接通过对输出的统计得到误差值的大小,将其从数字输出中移除从而消除了ADC输出非线性.将该校准方法应用于14bit流水线ADC中,仿真结果表明校准后信噪失真比SNR为76.9dB,无杂散动态范围SFDR为73.9dB,有效精度ENOB从9bit提高到12.5bit.     

8 GHz, 10 W solid-state power amplifier for microwave digital radio

An 8 GHz, 10 W GaAs FET prototype power amplifier has been developed to replace the TWT in the Northern Telecom's digital microwave radio system. For a single bit stream of 91.04 Mbit/s, the residual bit error rate at 40 dBm output level was 1.0×10?32 compared with 1.0×10?23 for TWT; the AM/AM conversion ratio was 0.375 dB/dB and AM/PM was 0.84°/dB. The total mean time between failure of the amplifier was 350 000 h.     

一种0.18μm数字工艺的12bit 100MS/s流水线型ADC设计

描述一个基于TSMC 0.18μm数字工艺的12 bit 100 Ms/s流水线模数转换器的设计实例。该模数转换器采用1.5bit每级结构,电源电压为1.8V。包括十级1.5 bit/stage和最后一级2bit Flash模数转换器,共产生22bit数字码,数字码经过数字校正电路产生12 bit的输出。该模数转换器省去了采样保持电路,电路模块包括:各个子流水级、共模电压生成模块、带隙基准电压生成模块、开关电容动态偏置模块、系统时钟生成模块、时间延迟对齐模块和数字校正电路模块。为了实现低功耗设计,在电路设计中综合采用了输入采样保持放大器消去、按比例缩小和动态偏置电路等技术。ADC实测结果,当以100 MHz的采样率对10MHz的正弦输入信号进行采样转换时,在其输出得到了73.23dB的SFDR,62.75dB的SNR,整体功耗仅为113mW。     

集成数字转换器MAX6682的原理及时序

集成数字转换器MAX6682,具有10位分辨率,支持任意热敏电阻温度范围测量,具备SPI兼容接口,直接输出温度相对应的数字编码。文中介绍了该电路的工作原理及工作时序。     

IMPATT-Diode Power Amplifiers for Digital Communication Systems

lMPATT-diode amplifiers with a power output of 1.0 W have been developed for use in an 11-GHz digital radio. Two types of amplifiers, a multistage reflection amplifier and a hybrid amplifier containing an injection-locked oscillator stage, have been evaluated by measuring the bit error rate degradation due to the amplifier. System test data show that the stable amplifier introduces little or no errors while the injection-locked oscillator (ILO) often introduces an error-rate floor.     

基于EPC Class0协议超高频温度传感器无源电子标签

提出了实现具有温度传感功能的RFID无源标签芯片电路的设计思路,结合900MHz超高频EPC Class0协议,提出电子标签结构及参考电路,包括射频前端接收电路、数字逻辑控制部分、温度传感及量化和存储器四部分组成。采用Chartered0.35μm CMOS工艺流片、测试。温度量化采用一个低功耗8位逐次逼近模数转化器实现,输出温度量化误差在0～90℃范围内为±2℃。芯片测试工作电流20.7μA(不包含存储器)。     

Efficient VLSI digital logarithmic codecs

N bit digital words can be logarithmically encoded and compressed to a word length of (log/sub 2/n+m-1) bit maintaining a relative accuracy of m bit over (n-m) octaves of signal level. A bit-serial VLSI coder is reported, which requires little more than a log/sub 2/n counter and an output register and it has a latency of one wordlength. The bit-parallel coder can be built with less than n/sup 2/ transistors and has less than n/4 gate delays. The decoder has similar properties and it expands the logarithm to an antilogarithm with n bit of dynamic range. Using these codecs, digital multiplication, division, powers and roots are reduced to additions, subtractions and shifts, respectively.<>     

Highly configurable capacitive interface circuit for tri‐axial MEMS microaccelerometer

A highly configurable capacitive interface circuit with on‐chip calibration capability for tri‐axial microaccelerometer is presented. The capacitive interface circuit is designed to be programmable, and can reduce the output errors due to the parasitic capacitance variations and process variations. The capacitive sensing chain adopts the chopper stabilisation, and includes the front‐end charge amplifier with three 10‐bit programmable capacitor arrays, 9‐bit digital‐to‐analogue converter and 10‐bit programmable gain amplifier. The calibration coefficients are stored to the on‐chip erasable programmable read only memory. The outputs from the three‐channel capacitive sensing chain are converted to digital signal by the integrated 14‐bit algorithmic analogue‐to‐digital converter. After calibrating the 48 samples, all the samples meet the desired specification range. Before the calibration, the errors of the average values of the output offset and gain were +47.1% and ?85.9%, respectively. After the calibration, however, the errors of the average values of the output offset and gain are reduced to be 0.3% and 0.5%, respectively. The resolutions for x/y‐axis and z‐axis are measured to be 326 and 728?µg, respectively.     

An all-digital bit detector for compact disc players

A bit detector is described which is suitable for integration using digital VLSI technology. In the bit detector the signal is sampled at a fixed clock frequency which is not related to the bit rate of the input signal. The incoming bits are detected by comparing the digitized input signal with the output of an all-digital phase-locked loop (PLL), which regenerates the bit clock that is present in the input signal. The design must be sufficiently robust to handle deviations in the physical size of the pits and disturbances like dropouts. Experimental optimization of the bit detector was performed with the aid of a hardware realization     

一种数字预失真功放输出动态提升技术

数字预失真功放的输出动态提升技术在现代功率放大器设计和研究中已成为一个重要的课题。本文基于数字预失真功放自身特征以及自适应信号处理技术,提出了一种全新的输出动态提升技术。理论分析和试验结果表明：采用该新型技术的数字预失真功放不仅输出动态得到了大幅度提升,而且线性也有一定程度改善。     

A 1 GHz Digital Channel Multiplexer for Satellite Outdoor Unit

A digital channel multiplexer for satellite outdoor unit running at 1 GHz clock frequency is implemented in 65 nm CMOS mixed oxide dual voltage technology. This multiplexer, based on a 1 GS/s digital signal processor (DSP) approach with 500 MHz input and output bandwidth, embeds two 8 bit 1 GS/s analog-digital converters (ADCs) and two 8 bit 1 GS/s digital-analog converter (DACs). It consumes less that 1022 mW at ambient temperature while achieving noise rejection up to 42.5 dB on a single tone, and > 37 dB on modulated satellite channels.     

Improved performance of coded digital FM

The performance of convolutionally encoded narrow-band digital FM with Viterbi decoding was considered in some detail by Simon (1983) for a noncoherent limiter/discriminator (L/D) with integrate and dump (I&D) bit detection. Employing a new threshold receiver which averages the output of the I&D detector with the output of a sample and hold (S&H) detector, a 3-dB improvement over Simon's results for the bit error probability with FM clicks is shown to be achievable. At low error rates, the performance of this new receiver is, moreover, comparable to that obtained when the clicks are exactly removed by Simon's hypothetical “genie”     

Pulse Regeneration in the Gigabit-Per-Second Range Using a Diode Differential Regenerator

A clocked pulse regenerator circuit (diode differential regenerator (DDR)) is described which employs a modified hybrid tee, step recovery diodes, and bipolar transistors. For the first time a hybrid tee is used in ultra broad-band digital applications. Signal pulses with bit rates up into the gigabit-per-second range are regenerated, the shape of the input pulses having no direct influence on the shape of the output pulses. Only the charge of the input signals determines the amplitudes of the output pulses. At a signal bit rate of 1 Gbit/s an insertion voltage gain of 20 dB was obtained. Operating the DDR in a push-pull mode the voltage gain is doubled to 26 dB. Because the output pulses of the DDR are very narrow the circuit can be used in time-division multiplexers providing output pulse streams with bit rates up to 16 Gbit/s and amplitudes of several volts across a load of 50 Omega. The internal behavior of the DDR is analyzed, among other things by the results of computer simulations. Calculations for optimizing the employed components are given.     

Digital signal transfer in charge-transfer devices

The nonlinear properties of digital signal transfer through charge-coupled device and bucket-brigade shift registers are considered in terms of adjacent bit charge levels. A signal transfer efficiency is defined and shown to be a useful parameter for charge-transfer device shift register simulation. Approximate equations are developed for the worst case output bit levels and an approximate formula for the optimum input `fat' zero level, with respect to the worst case output signal `window', is obtained. The analysis includes only the intrinsic incomplete charge transfer properties of CTD's under square-wave clock pulsing conditions. Comparison of the theory and preliminary experimental results for CCD indicate good quantitative agreement.     

Ka-band analog front-end for software-defined direct conversion receiver

A six-port Ka-band front-end architecture based on direct conversion for a software-defined radio application is proposed in this paper. The direct conversion is accomplished using six-port technology. In order to demodulate various phase-shift-keying/quadrature-amplitude-modulation (PSK/QAM) modulated signals at a high bit rate, a new analog baseband circuit was specially designed according to the I/Q equations presented in the theoretical part. An experimental prototype has been fabricated and measured. Simulation and measurement results for binary PSK, quaternary PSK (QPSK), 8 PSK, 16 PSK, and 16 QAM modulated signals at a bit rate up to 40 Mb/s are presented to validate the proposed approach. A software-defined radio can be designed using the new front-end and only two analog-to-digital converters (ADCs) because the I/Q output signals are generated by analog means. Previous six-port receivers make use of four ADCs to read the six-port dc levels and require digital computations to generate the I/Q output signals. With the proposed approach, the load of the signal processor will therefore be reduced and the modulation speed can be significantly increased using the same digital signal processor.     

Low‐Voltage Current‐Sensing CMOS Interface Circuit for Piezo‐Resistive Pressure Sensor

A new low‐voltage CMOS interface circuit with digital output for piezo‐resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo‐resistance due to applied pressure and to allow low‐voltage circuit operation. A simple 1‐bit first‐order delta‐sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 µm CMOS technology and draws less than 200 µA from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non‐linearity error.