A versatile ECL multiplexer IC for the Gbit/s range

A new approach to digital multiplexing for communication systems operating in the Gbit/s range is presented. With a single function, monolithically integrated in the established silicon bipolar process, many operations required by the communication system's multiplex equipment are achieved at data rates of up to 3 Gbits/s. The IC is a four-channel multiplexer designed to interface readily with ECL families. Demonstrations of the ICs performance include pseudorandom pattern generation by multiplexing ECL inputs up to 2 Gbits/s, demultiplexing into ECL registers at 1 Gbits/s, clock extraction in a 560 Mbit/s coaxial cable transmission system, and a modulo-n divider technique for timing generation using ECL feedback shift registers for frequencies up to 1.6 GHz. The demonstrations highlight the multiplexer's ability to effectively extend the system speed limit of commercially available ECL from a few hundred Mbits/s to the Gbit/s range. An eight-input multiplexer using three chips in a hybrid assembly is demonstrated multiplexing a static input pattern up to 2.8 Gbits/s.     

Technology and Design Considerations for a Very-High-Speed Fiber-Optic Data Bus

The techology for very-high-speed fiber-optic data transmission is reviewed, and an assessment is made of the data rate limitations for a ring bus. Maximum data rates for single-channel transmission are estimated to he in the five-ten Gbit/s range, but bus capacity can be increased to 100 Gbits/s or higher with parallel interconnections or carrier-frequency multiplexing. A recirculating fiber loop is proposed as a buffer between the high data rate bus and terminals which operate at relatively low speeds. A bus terminal design based on this concept is suggested.     

Q-switched semiconductor diode lasers

Diode lasers with an intracavity electroabsorption modulator have been operated with full on/off modulation at rates of 3 GHz. In addition, modulation of the lasers has been shown up to a detector-limited frequency of 6 GHz. A new model of these devices, which includes amplified spontaneous emission and high gain is developed in this paper. A quasi-static gain approximation is introduced and the dynamics of the electron and photon population are modeled by three coupled nonlinear difference equations which can be numerically solved with very little computation time. The model predicts the possibility of a new mode ofQ-switched operation with the capacity for repetition rates of tens of gigahertz and binary pulse position modulation at rates of the order of 10 Gbits/s.     

Gigabit/s optical receiver sensitivity and zero-dispersion single-mode fiber transmission at 1.55 µm

High-speed pulse response and receiver sensitivity at 1.55 μm were measured at data rates ranging from 400 Mbits/s to 2 Gbits/s, in order to elucidate characteristics of a reach-through p+nn- Ge APD. The p+nn- Ge APD receiver provided a 2 Gbit/s received optical power level of -32.0 dBm at 1.55μm and a 10^-9error rate, which was 4 dB better than the receiving level with a p+n Ge APD. Detector performance at 1.3μm was also studied for comparison with performance at 1.55μm. Single-mode fibers, which have 0.54 dB/km loss and zero dispersion at 1.55μm, and an optical transmitter-receiver, whose repeater gain is 29.2 dB, have enabled 51.5 km fiber transmission at 2 Gbits/s. The transmission system used in this study has a data rate repeater-spacing product of 103 (Gbits/s) . km at 1.55μm. Optical pulse broadening and fiber dispersion were also studied, using 1.55 and 1.3μm dispersion-free fibers. Future repeater spacing prospects for PCM-IM single-mode fiber transmission systems are discussed based on these experimental results.     

光通信高速率调制系统设计及性能仿真测试

为了奠定未来光通信高效实行的基础,需要研究高速高质量的激光调制系统。本文在一般调制系统设计原则基础之上,从核心器件入手,选定了以DFB激光器、EAM为主的调制整体框架;之后进行了激光器周边辅助电路、调制器驱动电路以及调制器自身结构的精细化设计,形成了高速调制系统设计框图;利用光通信仿真平台Optisystem在临界调制速率1.12 Gbits、高速5 Gbits、超高速10 Gbits三种梯度下进行了该系统的性能测试。结果显示:1.12 Gbits到5 Gbits测试性能优异且稳步提升,表明该系统能够满足现阶段一般条件下的光通信高速调制需求;但10 Gbits下系统表现不够稳定,说明适应超高速条件下的调制系统还需进一步深入研究。该调制系统的设计和仿真对后续实测工作的开展具有重要指导意义。     

Gigabit/s Optical Receiver Sensitivity and Zero-Dispersion Single-Mode Fiber Transmission at 1.55 µm

High-speed pulse response and receiver sensitivity at 1.55 µm were measured at data rates ranging from 400 Mbits/s to 2 Gbits/s, in order to elucidate characteristics of a reach-through p/sup +/nn/sup -/ Ge APD. The p/sup +/nn/sup -/ Ge APD receiver provided a 2 Gbit/s received optical power level of -32.0 dBm at 1.55 µm and a 10/sup -9/ error rate, which was 4 dB better than the receiving level with a p/sup +/n Ge APD. Detector performance at 1.3 µm was also studied for comparison with performance at 1.55 um. Single-mode fibers, which have 0.54 dB/km loss and zero dispersion at 1.55 µm, and an optical transmitter-receiver, whose repeater gain is 29.2 dB, have enabled 51.5 km fiber transmission at 2 Gbits/s. The transmission system used in this study has a data rate repeater-spacing product of 103 (Gbits/s) /spl dot/ km at 1.55 µm. Optical pulse broadening and fiber dispersion were also studied, using 1.55 and 1.3 µm dispersion free fibers. Future repeater spacing prospects for PCM-IM single-mode fiber transmission systems are discussed based on these experimental results.     

Mode partition noise characteristics in high-speed modulated laser diodes

This paper presents the theoretical and experimental results of a study on laser diode mode partition noise. Laser diode mode partition noise is evaluated by mode partition constants which indicate the degree of variance in longitudinal mode power. The relationship between the mode partition constants and laser diode characteristic parameters is clarified using rate equations. The mode partition constants for AlGaAs/GaAs and InGaAsP/InP double heterostructure laser diodes are measured experimentally and found to be independent of the structure, wavelength (0.8-1.6 mum), and bit-rate (400 Mbits/s-l.6 Gbits/s). The experimental and theoretical results show excellent agreement.     

A Flexible DSP Architecture for MIMO Sphere Decoding

This paper presents the architecture and circuit design of a sphere decoder for agile multi-input multi-output (MIMO) communication systems. Algorithm and architecture co-design is used to reduce hardware complexity, which enables the proposed sphere decoder to support larger antenna-array sizes and higher order modulations. The proposed architecture is also capable of processing multiple frequency subcarriers for orthogonal frequency-division multiplexing (OFDM) based systems. A 20 times area reduction is achieved, even without interleaving of subcarriers compared to the direct-mapped architecture. The sphere decoder supports multiple configurations: antenna arrays from 2 times 2 to 16 times 16, constellation sizes from binary phase-shift keying (BPSK) to 64-QAM (quadrature-amplitude modulation), and 16-128 subcarriers. The peak estimated data rate exceeds 1.5 Gbits/s of ideal throughput in a 16-MHz bandwidth. The core area is estimated at 0.31 mm² in a standard 90-nm CMOS technology. The estimated power consumption is 33 mW in the 16 times 16 64-QAM mode at 256 MHz from a 1-V supply voltage.     

Fully digital jerk-based chaotic oscillators for high throughput pseudo-random number generators up to 8.77 Gbits/s

This paper introduces fully digital implementations of four different systems in the 3rd order jerk-equation based chaotic family using the Euler approximation. The digitization approach enables controllable chaotic systems that reliably provide sinusoidal or chaotic output based on a selection input. New systems are introduced, derived using logical and arithmetic operations between two system implementations of different bus widths, with up to 100× higher maximum Lyapunov exponent than the original jerk-equation based chaotic systems. The resulting chaotic output is shown to pass the NIST SP. 800-22 statistical test suite for pseudo-random number generators without post-processing by only eliminating the statistically defective bits. The systems are designed in Verilog HDL and experimentally verified on a Xilinx Virtex 4 FPGA for a maximum throughput of 15.59 Gbits/s for the native chaotic output and 8.77 Gbits/s for the resulting pseudo-random number generators.     

Characteristics of Gbit/s optical receiver sensitivity and long-span single-mode fiber transmission at 1.3 µm

Sensitivity of a 1.3 μm Ge APD receiver was measured at data rates ranging from 100 Mbits/s to 2 Gbits/s, using a high-speed GaAs FET RZ driver, low-noise Si bipolar transistor (BIT) receiver amplifier, and a highly sensitive TD comparator. The required received optical level at a 10^-9error rate was -31.9 dBm for 2 Gbits/s with a Ge APD/Si BIT front end having a 50 Ω input impedance. A Ge APD/ GaAs FET front end, with a 500 Ω input impedance, brought about 2 dB improvement at 100 Mbits/s, as compared with a Ge APD/Si BIT (50 Ω) front end. A coupling loss of 4 dB, achieved by a hemispherical microlens tipped on a single-mode fiber, and a low fiber loss of 0.57 dB/km, including splice loss, enabled 44.3 km single-mode fiber transmission at 2 Gbits/s. The 1.3 μm transmission system has a data rate repeater-spacing product of 88.6 (Gbit/s)km. Prospects of Gbit/s receiver sensitivity and the 2 Gbit/s transmission system, with more than 50 km repeater spacing, are also discussed.     

Lightwave primer

This paper presents an introduction to the principles of lightwave system engineering. The treatment is historical rather than categorical-lightwave systems are described in terms of their evolution through four generations of technology, from a first generation operating at 0.85 μm wavelength over multimode fiber to a fourth generation employing coherent techniques at 1.55 μm. Basic engineering considerations such as fiber dispersion and receiver sensitivity are introduced early, then refined as the discussion progresses toward higher-performance, more sophisticated systems. The fundamental mechanisms that limit the performance of a given technology are quantified, and a figure of merit, the product of bit rate times maximum repeater spacing, is estimated. Values of this product range from about 2 Gbits/s . km for first-generation technology to roughly 900 Gbits/s . km for coherent systems.     

Monolithic large-signal transimpedance amplifier for use in multi-gigabit, short-range optoelectronic interconnect applications

A novel large-signal transimpedance amplifier front-end, intended for monolithic integration with a Si p-i-n diode and employing HBT-CMOS technology for use in short-range optoelectronic interconnects is proposed. Simulated bandwidth and gain are >4 Gbits/s and 43 dB/spl Omega/, respectively, while driving a 100-fF load to TTL voltage levels.     

光分组交换系统的结构研究

对光分组交换系统的几种结构进行了分类和比较研究,介绍了已研制成功的2.5Gbit/s光ATM交换实验系统的结构,给出了测试波形图,说明了工作机理。     

Terahipas: a modular and expandable terabit/second hierarchicallymultiplexing photonic ATM switch architecture

A terabit/second hierarchically multiplexing photonic asynchronous transfer mode (ATM) switch network architecture, called Terahipas, is proposed. It combines the advantages of photonics (a large bandwidth for transport of cells) and electronics (advanced logical functions for controlling, processing, and routing). It uses a hierarchical photonic multiplexing structure in which several tens of channels with a relatively low bit rate, say 2.4 Gb/s, are first time-multiplexed on an optical highway by shrinking the interval between optical pulses, then a number of optical highways are wavelength-multiplexed (or space-division multiplexed). As a result, the switch capacity can be expanded from the order of 100 Gb/s to the order of 10 Tb/s in a modular fashion. A new implementation scheme for cell buffering is used for eliminating the bottleneck when receiving and storing concurrent optical cells at bit rates as high as 100 Gb/s. This new architecture can serve as the basis of a modular, expandable, high-performance ATM switching system for future broad band integrated service digital networks (B-ISDN's)     

光载无线电系统综合实验方案设计与教学实践

为了培养学生的创新能力,在光纤通信实验中安排了光载无线电的综合性设计性实验项目。该实验采用学生自主设计的模式,主要教学环节有：核心模块设计、自主系统搭建、传输信号分析、参数优化和总结汇报及考核,可以在仿真软件上对自行设计的系统进行测试及优化。教学实践证明,大部分学生能自主设计各具特色的光载无线电系统,在波分复用单通道下行链路中,速率达到1Gbits/s;通过实验学生能学到科学研究的方法,进而锻炼了创新意识与创新实践能力;该实验方案对于高校实验室教学改革具有较好的借鉴意义。     

2.5Gbit/s交叉增益型全光波长转换的实验研究

利用自行研制的半导体光放大器对交叉增益型波长转换器进行了实验研究.实现了速率为2.5Gbit/s的1549.8nm到1562.6nm波长上转换.比较了不同调制格式、不同泵浦功率条件下的转换输出功率、消光比和噪声特性,并对实验的结果作了解释.     

Terminals for a high-speed optical pulse code modulation communication system: II. Optical multiplexing and demultiplexing

Techniques are described for optically multiplexing and demultiplexing individual pulse code modulation channels in order to develop the terminal capability for a high-capacity optical communication system. It is shown that, using these techniques, an information capacity in excess of 10¹⁰bit/s can be achieved on the output beam of a single laser.     

Effect of avalanche build-up time on avalanche photodiode sensitivity

A calculation method for the receiver sensitivity of an avalanche photodiode is considered, taking into account avalanche build-up time and carrier transit time, in addition to the CR time constant. Actual receiver performance is estimated in a high data rate region of up to 10 Gbits/s for germanium avalanche photodiodes, applying the measured avalanche build-up time.     

基于V93000的SoC中端口非测试复用的ADC和DAC IP核性能测试方案

 SoC(System-on-a-Chip)芯片设计中,由于芯片测试引脚数目的限制以及基于芯片性能的考虑,通常有一些端口不能进行测试复用的IP(Intellectual Property)核将不可避免地被集成在SoC芯片当中.对于端口非测试复用IP核,由于其端口不能被直接连接到ATE(Automatic Test Equipment)设备的测试通道上,由此,对端口非测试复用IP核的测试将是对SoC芯片进行测试的一个重要挑战.在本文当中,我们分别提出了一种基于V93000测试仪对端口非测试复用ADC(Analog-to-Digital Converter)以及DAC(Digital-to-Analog Converter)IP核的性能参数测试方法.对于端口非测试复用ADC和DAC IP核,首先分别为他们开发测试程序并利用V93000通过SoC芯片的EMIF(External Memory Interface)总线对其进行配置.在对ADC和DAC IP 核进行配置以后,就可以通过V93000捕获ADC IP 核采样得到的数字代码以及通过V93000 采样DAC IP 核转换得到的模拟电压值,并由此计算ADC以及DAC IP 核的性能参数.实验结果表明,本文分别提出的针对端口非测试复用ADC以及DAC IP 核测试方案非常有效.     

A GaAs MSI Word Generator Operating at 5 Gbits/s Data Rate

This paper describes a monolithic MSI GaAs word generator that operates at data rates from a few bits/s up to 5 Gbits/s. This circuit, with 600 active devices, consists of an 8:1 parallel-to-serial converter, a timing generator, control logic, and ECL-interface networks. The circuit generates multiple 8-bit words with dynamic word-length control. The paper discusses the fabrication technology, the design of the word generator and its building blocks, and the performance of the complete chip.