A 256-element CMOS imaging receiver for free-space optical communication

This paper describes a CMOS imaging receiver for free-space optical (FSO) communication. The die contains 256 optical receive channels with -47 dBm optical sensitivity and 30 dB optical dynamic range at 500 kb/s/channel while consuming 67 mW. Received signals are amplified by digitally self-calibrated open-loop amplifiers and digitized before clock and data recovery. The sampled data also provide inputs for digital automatic gain and offset control loops closed around the analog amplifier chain to compensate for signal variations due to atmospheric turbulence and daylight interference. Gain control logic can adapt to incident signals over the 30 dB dynamic range within 28 bit periods. Low-power logic design and analog circuit techniques are used to minimize digital crosstalk to single-ended photodetectors referenced to a bulk substrate. Local arbitration circuitry at each channel forms an intrachip data passing network to multiplex received data words from the 16 /spl times/ 16 array onto a common off-chip bus. The 1.6 M transistor mixed-signal die fabricated in a 0.25 /spl mu/m CMOS process measures 6.5/spl times/6.5 mm/sup 2/. Reception at 500 kb/s through a 1.5 km atmospheric channel is demonstrated with 3 mW optical transmit power during nighttime and daylight hours.     

A vertical-cavity surface-emitting laser appliqued to a 0.8-/spl mu/m NMOS driver

An optoelectronic integrated circuit (OEIC) composed of a vertical-cavity surface-emitting laser (VCSEL) appliqued to an NMOS drive circuit was fabricated to form an optical link from the CMOS chip. A custom NMOS circuit was designed and fabricated through the MOSIS foundry service in a standard 0.8-/spl mu/m CMOS process. InGaAs quantum-well VCSELs were grown, fabricated and tested on an n-type GaAs substrate. Next, the VCSELs underwent a substrate removal technique and were appliqued to the NMOS circuitry. The OEIC was tested at the chip level and showed an electrical to optical conversion efficiency of 1.09 mW/V. Modulation results are also discussed.     

A 3-Gb/s optical detector in standard CMOS for 850-nm optical communication

This paper presents a monolithic optical detector, consisting of an integrated photodiode and a preamplifier in a standard 0.18-/spl mu/m CMOS technology. A data rate of 3 Gb/s at BER <10/sup -11/ was achieved for /spl lambda/=850 nm with 25-/spl mu/W peak-peak optical power. This data rate is more than four times than that of current state-of-the-art optical detectors in standard CMOS reported so far. High-speed operation is achieved without reducing circuit responsivity by using an inherently robust analog equalizer that compensates (in gain and phase) for the photodiode roll-off over more than three decades. The presented solution is applicable to various photodiode structures, wavelengths, and CMOS generations.     

A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology

This paper presents a 28-GHz monolithic quadrature voltage-controlled oscillator (QVCO) realized in a preproduction 0.4-/spl mu/m SiGe bipolar technology with 85-GHz transit frequency. QVCOs efficiently drive quadrature modulators and demodulators in receivers or transmitters. At 28.9 GHz, the circuit provides -14.7 dBm of output power and phase noise of -84.2 dBc/Hz at a 1-MHz offset. The two output signals are in quadrature with phase error of about 5/spl deg/. Tuning of the QVCO may be done in the frequency range from 24.8 to 28.9 GHz with nearly constant output power. The circuit consumes 25.8 mA from the 5 V voltage supply.     

A packaged high-performance decision IC up to 45-Gb/s

A packaged D-type flip-flop (DFF) decision circuit for optical OC-768 systems and testing equipment is reported. The circuit uses 1 /spl mu/m InP SHBT technology featuring f/sub T//f/sub max/=150 GHz and has been operated up to 45 Gb/s with a clock phase margin about 180/spl deg/. Measured output eye diagrams from packaged devices exhibit 9/8 ps rise/fall with only 3ps peak-peak jitter. A single-ended AC-coupled clock input makes the application of this circuit very convenient. The IC dissipates 440 mW from a -4V supply voltage.     

A 75-dB image rejection IF-input quadrature-sampling SC /spl Sigma//spl Delta/ Modulator

Quadrature sampling of intermediate frequency (IF) signals is subject to the well-known problem of gain and phase mismatches between the in-phase (I) and quadrature (Q) channels. This paper presents an IF-input quadrature-sampling switched-capacitor (SC) /spl Sigma//spl Delta/ modulator that circumvents the I/Q mismatch problem by time-sharing between the I and Q channels the critical circuit components, namely, the sampling capacitor and the capacitor of the first-stage feedback digital-to-analog converter (DAC). In addition, a clocking scheme that is insensitive to I/Q phase imbalance is used. A third-order single-loop 1-bit low-pass modulator has been designed and fabricated in a 0.35-/spl mu/m CMOS process with an active area of 0.57mm/sup 2/. The experimental results show that the modulator achieves an image-rejection ratio (IRR) of greater than 75dB throughout a 200-kHz signal bandwidth.     

Linear frequency modulation of voltage-controlled oscillator using delay-line feedback

This letter proposes a structure for a voltage-controlled oscillator (VCO) circuit which operates in a frequency range of 4.0-4.3 GHz and can achieve a highly linear frequency sweep without any additional compensation circuit. The VCO consists of an amplifier and a feedback circuit only. The feedback circuit compensates for the phase delay of a transmission line with a varactor and sets the closed-loop phase change close to 360/spl deg/. The measured maximum deviation from a linear frequency sweep is /spl sim/1.2 MHz when the varactor capacitance C/sub V/ of the VCO is related to the control voltage V/sub C/ by C/sub V//spl prop/V/sub C//sup -1.06/. The spectral distribution of the beat frequency between the VCO output and delayed VCO output shows that the proposed VCO has excellent linearity in frequency modulation.     

Broadband hitless bypass switch for integrated photonic circuits

A new microphotonic hitless switch is proposed. By enabling continuous, uninterrupted transition to a bypass path, it permits tuning of wavelength add-drop filters without disturbing intermediate channels. The scheme comprises two symmetrically actuated, 2 /spl times/ 2 /spl Delta//spl beta/-type optical switches, antisymmetrically cascaded in a balanced Mach-Zehnder configuration, and a /spl pi/ differential phase shift in the interferometer arms. By symmetry, it provides for wavelength-independent hitless operation before, during and after switch reconfiguration, permitting slow switching independent of bit rate. Compact implementations using high-index-contrast microelectromechanical-system (MEMS)-actuated switches are proposed.     

1/spl times/4 optical switch based on transversal filter configuration with constant power consumption

An optical switch based on a transversal filter configuration is demonstrated. The switch consists of cascaded 3 dB optical power splitters and a phase shifter array. By using a silica-based planar lightwave circuit, a 1/spl times/4 optical switch was realised. A characteristic of the switch is that its power consumption is constant regardless of the output selection.     

RF power transistor storage time: theory and measurements

Measurements on two types of UHF power transistors are given. The measured charge storage time constants (/spl tau//SUB s/) were 89 ns and 173 ns, effectively `infinite' for most applications. Then t/SUB s/ is essentially independent of /spl tau//SUB s/, and depends mainly on circuit properties: base drive and collector current waveforms. The measured dependence of t/SUB s/ on circuit and transistor parameters is in accordance with analytical predictions. Therefore storage time can be accounted for explicitly in a priori circuit design of RF power amplifiers.     

Novel broad-band bit-synchronization circuit module for optical interconnections

A novel broad-band and ultrafast bit-synchronization circuit module is proposed and fabricated for optical interconnections. In optical packet switch fabric or optical interconnection between electric circuit boards, instantaneous bit synchronization is crucial to properly retime incoming packets with a random phase and reduce the number of preamble overhead bits. The developed bit-synchronization circuit module has a new clock selection circuit, which is configured with a phase comparator and an amplitude comparator. Since device-dependent delay circuits, such as buffer amplifiers or RC phasors, are not adopted, the newly developed clock selection circuit can operate under broad-band frequencies. The bit-synchronization circuit module was fabricated with a Si-bipolar gate array and it can operate at broad-band bit rates of up to 10.5 Gb/s. It also exhibits a power sensitivity penalty as low as 3 dB for 10-Gb/s input signals. The synchronization acquisition time of less than 9 b over the entire 360/spl deg/ phase range was confirmed by experiment.     

Evanescently coupled photodiodes integrating a double-stage taper for 40-Gb/s applications-compared performance with side-illuminated photodiodes

The design, fabrication, and performance of double-stage taper photodiodes (DSTPs) are reported. The objective of this work is to develop devices compatible with 40-Gb/s applications. Such devices require high efficiency, ultrawide band, high optical power handling capability, and compatibility with low-cost module fabrication. The integration of mode size converters improves both the coupling efficiency and the responsivity with a large fiber mode diameter. Responsivity of 0.6 A/W and 0.45 A/W are achieved with a 6-/spl mu/m fiber mode diameter and cleaved fiber, respectively, providing relaxed alignment tolerances (/spl plusmn/1.6 /spl mu/m and /spl plusmn/2 /spl mu/m, respectively), compatible with cost-effective packaging techniques. DSTPs also offer a wide bandwidth greater than 40 GHz and transverse-electric/transverse-magnetic polarization dependence lower than 0.2 dB. Furthermore, a DSTP saturation current as high as 11 mA results in optical power handling greater than +10 dBm and a high output voltage of 0.8 V. These capabilities allow the photodiode to drive the decision circuit without the need of a broad-band electrical amplifier. The DSTP devices presented here demonstrate higher responsivities with large fiber mode diameter and better optical power handling capabilities and are compared with classical side-illuminated photodiodes.     

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-/spl mu/m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 /spl mu/A/sub rms/. The input sensitivity of the receiver front-end is 16 /spl mu/A for 2.5-Gbps operation with bit-error rate less than 10/sup -12/, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 /spl mu/m/spl times/1500 /spl mu/m.     

Phase modulation efficiency and transmission loss of silicon optical phase shifters

This paper focuses on understanding the phase efficiency and optical loss of MOS-capacitor-based silicon waveguide phase shifters. A total of nine designs have been fabricated using poly-silicon and characterized at wavelengths around 1.55 /spl mu/m. Detailed comparison of design parameters shows that scaling down the waveguide dimensions, placing the capacitor gate oxide near the center of the optical mode, and reducing the oxide thickness significantly enhance phase modulation efficiency. Our best design to date demonstrates a /spl pi/-radian phase shift with 0.8-cm device length and 3-V drive. This phase shifter has a transmission loss of 15 dB, the primary source of which is the poly-silicon regions inside the device. An improved material can reduce loss to as little as 4 dB.     

A photonic-link millimeter-wave mixer using cascaded optical modulators and harmonic carrier generation

Efficient frequency conversion into and out of the millimeter wave frequency band has been demonstrated using photonic link signal mixing with cascaded optical modulators. By adjusting the modulator bias point and RF drive power to the modulator introducing the local oscillator signal at f/sub LO/=8.8 GHz, frequency conversions from f/sub s/ to f/sub LO//spl plusmn/f/sub s/, sf/sub LO//spl plusmn/f/sub s/, and 4f/sub LO//spl plusmn/f/sub s/ with respective losses of 4.8, 6.3, and 7.5 dB have been demonstrated. The direct phase noise measurement of the optical RF signal at 2f/sub LO/=17.6 GHz with 1 kHz offset shows -89 dBc/Hz, limited by the RF drive source.     

Automatic control of excitation parameters for switched-reluctance motor drives

This paper presents a new approach to the automatic control of the turn-on angle used to excite the switched-reluctance motor (SRM). The control algorithm determines the turn-on angle that supports the most efficient operation of the motor drive system, and consists of two pieces. The first piece of the control technique monitors the position of the first peak of the phase current (/spl theta//sub p/) and seeks to align this position with the angle where the inductance begins to increase (/spl theta//sub m/). The second piece of the controller monitors the peak phase current and advances the turn-on angle if the commanded reference current cannot be produced by the controller. The first piece of the controller tends to be active below base speed of the SRM, where phase currents can be built easily by the inverter and /spl theta//sub p/ is relatively independent of /spl theta//sub m/. The second piece of the controller is active above base speed, where the peak of the phase currents tends to naturally occur at /spl theta//sub m/ regardless of the current amplitude. The two pieces of the controller naturally exchange responsibility as a result of a change in command or operating point. The motor, inverter and control system are modeled in Simulink to demonstrate the operation of the system. The control technique is then applied to an experimental SRM system. Experimental operation documents that the technique provides for efficient operation of the drive.     

MIMO linear equalization with an H/sup /spl infin// criterion

In this paper, we study the problem of linearly equalizing the multiple-input multiple-output (MIMO) communications channels from an H/sup /spl infin// point of view. H/sup /spl infin// estimation theory has been recently introduced as a method for designing filters that have acceptable performance in the face of model uncertainty and lack of statistical information on the exogenous signals. In this paper, we obtain a closed-form solution to the square MIMO linear H/sup /spl infin// equalization problem and parameterize all possible H/sup /spl infin//-optimal equalizers. In particular, we show that, for minimum phase channels, a scaled version of the zero-forcing equalizer is H/sup /spl infin//-optimal. The results also indicate an interesting dichotomy between minimum phase and nonminimum phase channels: for minimum phase channels the best causal equalizer performs as well as the best noncausal equalizer, whereas for nonminimum phase channels, causal equalizers cannot reduce the estimation error bounds from their a priori values. Our analysis also suggests certain remedies in the nonminimum phase case, namely, allowing for finite delay, oversampling, or using multiple sensors. For example, we show that H/sup /spl infin// equalization of nonminimum phase channels requires a time delay of at least l units, where l is the number of nonminimum phase zeros of the channel.     

A new concept on remote sensing of cirrus optical depth and effective ice particle size using strong water vapor absorption channels near 1.38 and 1.88 /spl mu/m

Techniques for retrieving cloud optical properties, i.e., the optical depths and particle size distributions, using atmospheric "window" channels in the visible and near-infrared spectral regions are well established. For partially transparent thin cirrus clouds, these "window" channels receive solar radiances scattered by the surface and lower level water clouds. Accurate retrieval of optical properties of thin cirrus clouds requires proper modeling of the effects from the surface and the lower level water clouds. In this paper, we describe a new concept using two strong water vapor absorption channels near 1.38 and 1.88 /spl mu/m, together with one window channel, for remote sensing of cirrus optical properties. Both the 1.38- and 1.88-/spl mu/m channels are highly sensitive in detecting the upper level cirrus clouds. Both channels receive little scattered solar radiances from the surface and lower level water clouds because of the strong water vapor absorption below cirrus. The 1.88-/spl mu/m channel is quite sensitive to changes in ice particle size distributions, while the 1.38-/spl mu/m channel is less sensitive. These properties allow for simultaneous retrievals of optical depths and particle size distributions of cirrus clouds with minimal contaminations from the surface and lower level water clouds. Preliminary tests of this new concept are made using hyperspectral imaging data collected with the Airborne Visible Infrared Imaging Spectrometer. The addition of a channel near 1.88 /spl mu/m to future multichannel meteorological satellite sensors would improve our ability in global remote sensing of cirrus optical properties.     

Simultaneous multiplexing and demultiplexing of wavelength-interleaved channels in DWDM millimeter-wave fiber-radio networks

A simultaneous multiplexing and demultiplexing (MUX/DEMUX) scheme for wavelength-interleaved millimeter-wave 37.5-GHz-band fiber-radio channels spaced at 25 GHz has been proposed. The proposed MUX/DEMUX technique potentially realizes simple, compact, and low-cost central office and remote nodes by avoiding the use of wavelength-selective pre- and postprocessing hardware. The novel scheme incorporates an arrayed-waveguide grating with multiple loop-backs between the input and the output ports, in addition to multiple optical circulators and optical isolators. The multiplexing functionality of the proposed technology enables a carrier subtraction technique and consequently reduces the carrier-to-sideband ratios of the multiplexed channels. Multiplexing of the uplink channels generated via several methods is demonstrated experimentally. These techniques include generation of the channels by using the optical carriers that correspond to wavelengths spaced at the free spectral range (FSR) or multiples of the FSR from the downlink (DL) optical carriers and reuse of the DL optical carriers that are recovered by applying a wavelength reuse technique (/spl lambda//sub UL/=/spl lambda//sub DL//spl plusmn/n/spl times/FSR, where n=0,1,2,3,...). The demultiplexing functionality of the proposed scheme that separates the 37.5-GHz-band wavelength-interleaved DL channels spaced at 25 GHz is also demonstrated. In addition, the effect of optical crosstalk on the transmission performance of the demultiplexed channels is also characterized experimentally.     

Controlling a unified chaotic system to hyperchaotic

This brief presents a simple technique using a sinusoidal parameter perturbation control input to drive a unified chaotic system to hyperchaotic. The original chaotic system is a three-dimensional autonomous system that has a broad spectrum of chaotic behaviors with the Lorenz and the Chen systems as two extremes of the spectrum. The control input is a simple sinusoidal function cos(/spl omega/t) with a constant parameter /spl omega/. The hyperchaotic system is not only demonstrated by computer simulations but also verified with bifurcation analysis and implemented via an electronic circuit.