CMOS video filters using switched capacitor 14 MHz circuits

In order to realize self-contained analog video LSI, video band switched-capacitor (C) filters, including a two-dimensional filter, have been experimentally fabricated. By using 2-/spl mu/m/spl middot/CMOS technology and high-speed/high-precision circuits, an LSI clock rate of 14 MHz, signal swing of 2 V p-p with a single 5-V supply, random noise S/N of 60-70 dB p-p/r.m.s at LSI output, and power dissipation of less than 5 mW per amplifier have been achieved. Single-stage cascode amplifiers are extensively used to attain video band speed. Neutralization is introduced into fully differential filters to improve their frequency response.     

A synchronous switched capacitor filter [CMOS Si-gate implementation]

A new switched capacitor circuit is presented, realizing a moderate to high Q frequency emphasizing network. The original feature of this circuit is that its resonant frequency is equal to one half of the sampling frequency, and independent of the accuracy of the capacitor ratio or of any imperfection, both affecting only the Q factor. The gain is nearly proportional to the Q factor. An experimental circuit has been implemented in CMOS Si-gate technology with a programmable gain of 20 dB and 40 dB, corresponding to a Q factor of 8.6 and 79, respectively. Experimental results are in good agreement with the theory. Modifications of the basic circuit are proposed to cancel the effects of parasitic capacitances and to reduce the chip area.     

CMOS RF switched capacitor bandpass filter tuned by ring VCO

A new RF switched capacitor bandpass filter and its command circuit made up of a ring voltage controlled oscillator with ‘XOR’ gates are proposed. Implemented in a standard CMOS technology, this circuit is intended to be used in a subset of professional mobile phone applications [380–520 MHz]. Experiments carried out on a prototype show a tunable center frequency range of 260 MHz [240–500 MHz], with a quality factor that can be as high as 300.     

A 1.8-2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76-2.56 GHz CMOS voltage-controlled oscillator(VCO) with switched capacitor array and switched inductor array is presented.Fabricated in 0.18μm 1P6M CMOS technology,the VCO achieves a 37% frequency tuning range.The measured phase noise varies between -118.5 dBc/Hz and -122.8 dBc/Hz at 1 MHz offset across the tuning range.Power consumption is about 14.4 mW with a 1.8 V supply.Based on a reconfigurable LC tank with switched capacitor array and switched inductor array,the tuning range is a...     

A 1.8-2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76-2.56 GHz CMOS voltage-controlled oscillator(VCO)with switched capacitor array and switched inductor array is presented.Fabricated in 0.18μm 1P6M CMOS technology,the VCO achieves a 37% frequency tuning range.The measured phase noise varies between-118.5 dBc/Hz and-122.8 dBc/Hz at 1 MHz offset across the tuning range.Power consumption is about 14.4 mW with a 1.8 V supply.Based on a reconfigurable LC tank with switched capacitor array and switched inductor array,the mnmg range is analyzed and derived in terms of design parameters,yielding useful equations to guide the circuit design.     

Microelectronic switched capacitor filters

An explanation of what switched-capacitor (SC) filters are and how they work is given. Attention is focused on low-sensitivity SC filters, which can be developed from a general passive ladder where the branches are arbitrary impedances. The equations that describe the filter components are reviewed, and the characteristics of these low-sensitivity filters are outlined. Applications of the filters in telecommunications are discussed     

Integrated CMOS GSM baseband channel selecting filters realized using switched capacitor finite impulse response technique

A problem of the design and optimization of analog channel selecting filters, which are needed in wireless communication systems, is considered and evaluated in this paper on an example of the baseband GSM (global system for mobile telephony) channel filter. Two versions of this filter, both designed by the authors using switched-capacitor finite impulse response (SC FIR) technique, are presented and compared to each other as well as to other concurrent designs. In order to fully and plausibly compare the both filter versions (the newer and the elder one), the authors decided to design and fabricate both filters using the same technology, i.e., the technology of the elder filter version, which is the two metal, two poly CYE CMOS 0.8 μm process. The conclusions, which have been drawn, are, however, general and to a large extent technology independent.Although both presented filters are switched-capacitor (SC) finite impulse response (FIR) systems [Dąbrowski A, Cetnarowicz D, Długosz R, Pawłowski P. Design and optimisation of integrated CMOS FIR SC channel filter for a GSM Receiver, European Conference on Circuit Theory and Design, Helsinki, 28–31 August 2001. p I.265; Długosz R, Dąbrowski A, Pawłowski P. Design and measurement results of the GSM SC FIR channel filter realized in CMOS 0.8 μm technology. In: 9th international conference mixed design of integrated circuits and systems, 2002. p. 607–12] they essentially differ to each other as they are based on two quite different SC FIR delay line structures. In the first filter version Gillingham delay elements [Gillingham P. Stray-free switched-capacitor unit delay circuit. Electron lett 1984;20(7):308–10] are used, while in the second version even and odd delay elements [Dąbrowski A. Multirate and multiphase switched-capacitors circuits, London: Chapman & Hall; 1997; Dąbrowski A, Menzi U, Moschytz GS. Design of switched-capacitor FIR filters with application to a low-power MFSK receiver. IEE Proceedings-G 1992;139(4):450] are alternately connected to form the delay line. In this way an interesting comparison of these two SC delay line concepts has been possible.It should also be stressed that the frequency responses of both presented filters have been designed using the same technique, i.e., the Kaiser window of order N = 31. The upper frequency is in both cases equal to 500 kHz and the frequency of the controlling clock generator is equal to 1 MHz.The filter with Gillingham delay elements dissipates 30 mW with the 3 V supply voltage and occupies 2.2 mm². On the contrary, the even–odd SC FIR filter dissipates 18 mW only with the 3 V supply voltage and occupies 2.4 mm². Moreover, the newer filter version has the stopband attenuation greater by about 10 dB than the previous version.     

Micropower switched capacitor biquadratic cell

The implementation of the double correlated sampling noise reduction technique in conventional strays-insensitive switched capacitor biquad building blocks is described. The function is performed by an offset cancellation circuit which is incorporated into the structure without the use of any additional capacitor, only minor modifications in the switching topology, and one supplementary clock phase. Consequently, a significant reduction of the low-frequency (1/f) noise is made possible and the usual differential amplifiers may be replaced by simple inverting amplifiers operated in class AB, featuring high-speed, low-quiescent power dissipation and low noise. An experimental micropower SC biquadratic filter section designed for `leapfrog' or `follow-the-leader feedback' structures has been developed using high gain (>80 dB) CMOS push/pull inverting amplifiers together with a three-phase clocking sequence. The integrated circuit, implemented in a low-voltage Si-gate CMOS process, achieves excellent accuracy and less than 5 /spl mu/W power dissipation with a 32 kHz sampling rate and /spl plusmn/1.5 V supplies; dynamic range is 66 dB.     

Parasitic compensated switched capacitor circuits

A parasitic-insensitive switched capacitor circuit is presented which can functionally replace the `toggle-switched? capacitor. Its properties are established via an inverting integrator application. A related parasitic-insensitive realisation is also shown for a noninverting integrator, which can provide a 3/2 clock period transmission delay.     

GaAs switched capacitor DC-to-DC converter

A switched capacitor DC-to-DC negative converter fabricated in GaAs MESFET technology is introduced in this paper. The converter has an oscillator that runs at 250 kHz, and requires two external capacitors, 0.1 and 1 μF. The converter runs off a wide range of supply voltage, 2 to 10 V, and has a typical output impedance of 75 Ω. A typical open circuit voltage conversion efficiency of 99.6% is achieved. The circuit can be integrated with other GaAs circuits to provide an on-chip negative supply. Measured, simulated and analytical results are introduced in this paper     

An electrically-programmable switched capacitor filter

Techniques are presented for the design of a second-order switched capacitor filter which has its frequency response parameters programmed by the application of digital control signals. Two different types of weighted capacitor arrays are used to achieve programmability in the center frequency, peak gain, and selectivity. Experimental results are given for an integrated NMOS version with eight logarithmically-spaced center frequencies programmed by a 3 bit digital word, and 64 Q and gain values programmed by two 6 bit words. The filter is designed so that binary changes in the sampling frequency provide new sets of center frequencies which smoothly continue the logarithmic progression. Since the response depends on monolithic MOS capacitor ratios, the accuracy and reproducibility inherent in the switched capacitor approach are retained.     

MOS switched capacitor ladder filters

A new technique for designing precision, fully integrated, high-order filters using standard MOS technology is described. Switched capacitor integrators have been used to realize long time constants in small areas, and by interconnecting these integrators in a `leapfrog' configuration, monolithic high-order filters have been implemented with transfer functions that are very insensitive to component variations. Experimental results are presented for an NMOS fifth-order Chebyshev low-pass ladder filter with 0.1-dB passband ripple, a cutoff frequency of 3.4 kHz when clocked at 128 kHz, and a dynamic range of 83 dB. An efficient method for implementing transmission zeros is also presented, along with a complete design example, and additional experimental results for a third-order elliptic low-pass ladder filter which achieved 90-dB dynamic range, with a total power dissipation of 18 mW in a die area of 4400 mil/SUP 2/.     

MOS switched capacitor sample data filters

Thin paper presents a configuration for realizsing second-order switched capacitor filters. The basic building blocks ore switched capacitor integrator and first-order networks. The integrator and the first-order networks are free from parasitic capacitances. The design of filters is achieved by using bilinear Z-transform.     

A multiplexed switched capacitor filter bank

A technique is introduced which allows several integrator capacitors to be multiplexed onto a single operational amplifier. As a result, the op amp can be shared by several switched capacitor filter channels, drastically reducing the number of op amps required for filter banks. Twenty second-order filters have been implemented in a circuit using only two op amps and 2.5 mm/SUP 2/. The design of this system is presented and its performance is discussed. Some loss of signal energy is shown to occur during the multiplexing operations, which reduces filter Q. Causes of this charge loss are described, and its effects on performance are modeled. The design of the op amp used is presented, which incorporates a new system of input stage biasing and differential to single-ended conversion, as well as other features.     

A CMOS switched transconductor mixer

A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled outputs, which are alternatingly activated by the switches. For ideal switching, the operation is equivalent to a conventional active mixer. This paper analyzes the performance of the switched transconductor mixer, in comparison with the conventional mixer, demonstrating competitive performance at a lower supply voltage. Moreover, the new mixer has a fundamental noise benefit, as noise produced by the switch-transistors and LO-port is common mode noise, which is rejected at the differential output. An experimental prototype with 12-dB conversion gain was designed and realized in standard 0.18-/spl mu/m CMOS to operate at only a 1-V supply. Experimental results show satisfactory mixer performance up to 4 GHz and confirm the fundamental noise benefit.     

A switched capacitor circuit simulator: AWEswit

This paper describes the modeling and simulation of switched capacitor circuits in AWEswit. AWEswit is a mixed signal simulator for switched capacitor circuits. It allows for portions of the circuit to be modeled with digital blocks controlled by an event queue. The remainder of the circuit is modeled in the analog domain. The paper describes the circuit formulations employed by AWEswit, and how they are exploited in modeling the nonidealities associated with switched capacitor circuits. AWEswit employs asymptotic waveform evaluation (AWE) as its core simulation engine. It combines circuit formulations in the charge-voltage and current-voltage regimes. This flexibility in the circuit formulations means that if the circuit is modeled entirely with ideal switches (i.e. no resistors), then it is automatically solved in the charge-voltage regime (like SWITCAP2). However, if portions of the circuit need to be solved in the current-voltage regime, then AWEswit automatically partitions the circuit and solves the different partitions in whichever regime is appropriate, i.e., in the current-voltage regime (using AWE to evaluate circuit response) or in the charge-voltage regime. AWEswit naturally handles the bandwidth limitations associated with switched capacitor circuits. In addition, it models the clock feedthrough and signal-dependent charge dump that characterize MOSFET switches. The simulator is illustrated by example     

Simplified MOS switched capacitor ladder filter structures

A general technique for time-sharing amplifiers to reduce die area in switched capacitor ladder filters is described and illustrated with a fifth-order elliptic low-pass ladder filter requiring only three operational amplifiers. Techniques for synthesizing filters with maximum passband accuracy in the presence of parasitic capacitances are presented, and verified with two versions of the same fifth-order design integrated in a standard NMOS process. Passband accuracies of better than 0.1 dB have been achieved using only 0.3 pF unit-sized capacitors. The dynamic range is 75 dB.     

Switch-induced error voltage on a switched capacitor

A concise analytical expression for switch-induced error voltage on a switched capacitor is derived from the distributed MOSFET model. The result can be interpreted in terms of a simple lumped equivalent circuit. With this expression the dependence is investigated of the error voltage on process parameters and on switch turnoff rate, source resistance, and other circuit parameters. These results can be used to quickly predict the error voltage. The analytical expression is in close agreement with computer simulations and experiments.