GMRES方法在3-D寄生电容计算中的应用

随着VLSI向深亚微米发展、集成电路密度不断提高,互连延迟成了加快器件速度的一个限制因素,由于互连延迟是由金属连线间的电阻及电容所产生的,因此萃取寄生参数的工作更显重要.文章使用GMRES方法求解了3-D寄生电容分析的复系数线性方程组,并将其与SOR迭代法相比较.这种方法可以降低方程的迭代次数约20%,并明显减少了方程的求解时间.     

CMOS驱动电路中信号延迟的精确计算

本文提出了树形网络ＣＭＯＳ驱动电路中信号延迟相对精确的计算表达式，它考虑了不同延迟定义下ＣＭＯＳ驱动电路等老头儿 导通电阻及负功电容的影响，可用于ＶＬＳＩ互连延迟的计算及时间驱动布图系统信号延迟计算中。     

悬浮栅结构ISFET动态特性的HSPICE仿真

通过对ISFET敏感机理的理论分析,根据表面基模型,建立了悬浮栅结构ISFET器件的HSPICE动态行为模型,对ISFET器件的动态特性进行仿真得到时间响应曲线,并探讨了薄膜等效电阻、薄膜等效电容、互连线寄生电容和寄生电阻等因素与动态特性中延迟时间和迟滞等不理想因素的关系,为ISFET/REFET差分结构集成传感器芯片设计提供理论指导.     

互连线间容性串扰对延迟的影响

集成电路的性能越来越受到互连线间寄生效应的影响,特别是耦合电容的容性串扰,容性串扰引起互连线跳变模式相关的延迟。文中从E lm ore de lay定义的角度推导了互连线受同时跳变的阶跃信号激励时开关因子的大小,分析了互连线受非同时跳变的阶跃信号激励时耦合电容对互连线延迟的影响,给出了不同激励时的受害线延迟计算方法。分析表明,开关因子为0和2不能描述耦合电容对受害线延迟影响的下上限。H sp ice模拟结果证明了分析计算的准确性。     

VDSM集成电路互连特性及RC延迟研究

利用多层金属导体寄生电容模型,详细分析了不同的金属互连线参数对寄生电容的影响,并采用一个闭合公式对超深亚微米级集成电路中的RC互连延迟进行估计.结果表明,当金属导线的纵横比接近2时,线间耦合电容对互连总电容的影响将占主导地位.在超深亚微米工艺条件下,当金属线宽和间距比例W/P的最优质值为0.5～0.6时,计算的互连延迟为最小.此外,还给出了低介电常数材料对互连线电容和延迟的影响,为超深亚微米级的集成电路设计与实现提供有益的参考.     

悬浮栅结构ISFET动态特性的HSPICE仿真

通过对ISFET敏感机理的理论分析,根据表面基模型,建立了悬浮栅结构ISFET器件的HSPICE动态行为模型,对ISFET器件的动态特性进行仿真得到时间响应曲线,并探讨了薄膜等效电阻、薄膜等效电容、互连线寄生电容和寄生电阻等因素与动态特性中延迟时间和迟滞等不理想因素的关系,为ISFET/REFET差分结构集成传感器芯片设计提供理论指导。     

悬浮栅结构ISFET动态特性的HSPICE仿真

通过对ISFET敏感机理的理论分析，根据表面基模型，建立了悬浮栅结构ISFET器件的HSPICE动态行为模型，对ISFET器件的动态特性进行仿真得到时间响应曲线，并探讨了薄膜等效电阻、薄膜等效电容、互连线寄生电容和寄生电阻等因素与动态特性中延迟时间和迟滞等不理想因素的关系，为ISFET/REFET差分结构集成传感器芯片设计提供理论指导。     

基于各种快速Spice仿真器的Post-Layout寄生效应验证

现在的深亚微米工艺使用复杂的多层金属结构与先进电介质材料,随着工艺的进步,集成电路的器件尺寸越来越小,金属互连线做得越来越细,金属互连产生的寄生效应对电路性能的影响也越来越明显,各种各样的问题譬如由耦合电容产生了串扰噪声和延迟,IR drop引起的电压降,高电流密度引起的电迁移效应,以及混合信号设计中DC-path泄漏已经成为非常普遍的问题。对于整个芯片,在post-layout仿真时加上提取的寄生参数,有助于在设计中精确地分析每个寄生效应。快速Spice仿真器具有大的数据处理的容量和高的处理效率,因此这种仿真流程在设计中已经被广泛地应用。讨论如何在各种模式的仿真器(如UltraSim,NanoSim和HSIM)中选择合适的仿真器来进行post-layout仿真,以及不同的选择会有什么样不同的结果,另外还将对一些post-layout仿真结果进行分析。     

130nm PDSOI DTMOS体延迟研究

研究了基于IBM 8RF 130 nm工艺部分耗尽绝缘体上Si(PDSOI)动态阈值晶体管(DTMOS)体电阻、体电容以及体电阻和体电容乘积(体延迟)随Si膜厚度和器件宽度的变化.结果表明,Si膜厚度减小会导致体阻增大、体电容减小,但是体电阻和体电容的乘积却明显增大.Si膜厚度从200 nm减小到80nm,体延迟增加将近两个数量级.器件宽度增加使得体电阻和体电容都明显增大,DTMOS电路延迟也因此指数递增.推导出了PDSOI DTMOS的延迟模型,为SOI DTMOS器件设计提供了参考.     

铜互连CMP碟形缺陷及铜残留的研究

随着器件的特征尺寸越来越小,集成良越来越高,超大规模集成电路（ULSI）中设计的金属导线变细使得金属电阻增大,产生的热量增多,从而产生了严重的电迁移现象,同时由于线间电容和金属电阻增大引起的延迟（RC Delay）也不断恶化,这些都大大影响了器件的性能。传统的铝互连工艺因不能满足器件要求也逐渐被铜互连工艺取代。     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

多层空气隙Cu互连结构耦合电容的优化

随着超大规模集成电路特征尺寸不断缩小,多层cu互连之间的RC延迟成为一个越来越严重的问题.由于低介电常数(low-k)材料配合空气隙(air gap)结构可用于降低Cu互连导线间的耦合电容从而改善RC延迟特性,建立了单层和多层空气隙Cu互连结构的有限元分析模型,以研究空气隙结构尺寸与互连介质等效介电常数的关系.结果表明,在单层空气隙Cu互连结构中,通过增加互连导线间空气隙的结构尺寸可以减小Cu互连结构中的耦合电容,进而改善RC延迟特性;在多层空气隙Cu互连结构中,通过改变IMD和ILD中空气隙的尺寸结构可以得到RC延迟性能优化的多层空气隙Cu互连结构.     

Parasitic extraction: current state of the art and future trends

With the increase in circuit performance (higher speeds) and density (smaller feature size) in deep submicrometer (DSM) designs, interconnect parasitic effects are increasingly becoming more important. This paper first surveys the state of the art in parasitic extraction for resistance, capacitance, and inductance. The paper then covers other related issues such as interconnect modeling, model order reduction, delay calculation, and signal integrity issues such as crosstalk. Some future trends on parasitic extraction, model reduction and interconnect modeling are discussed and a fairly complete list of references is given     

An innovative interconnect structure with improved Elmore delay estimation model for deep submicron technology

With advancements in technology, size and speed have been the important facet in VLSI interconnects. The channel length of the device reduces to tens of nanometers, as the technology is transferring to the deep submicron level. This leads to the requirement of long interconnects in VLSI chips. Interconnects are known as the basic building block that can vary from size to size. They provide a connection between two or more blocks and have scaling problems that an IC designer faces while designing. As scaling increases, the impact of interconnect in the VLSI circuits became even more important. It controls all the important electrical characteristics on the chip. With scale-down technology, interconnects not only become closer with each other but their dimensions also change which can directly impact the circuit parameters. Certain RC models have already been defined to control these parameters but in this paper, authors have proposed a new improved Elmore delay estimation model (RC) to reduce delay and power consumption in interconnect circuits. An optimized Elmore delay calculation was performed for uniform and non-uniform wires to reduce the time constant of the interconnect circuits. Further, the proposed model is estimated and verified theoretically. A new improved RC model is compared to the designed π-model that shows remarkable results. We also observed the linear relationship of power consumption and delay for both the RC models and found that in π-model, upon decreasing the length of wire the power first increases then decreases but in the proposed model, the power first increases then remain constant and then further increases upon increasing the length of wire. Our proposed model shows the remarkable values as the average percentage improvement of power is 75.167% and delay as 74.714% is achieved using a uniform distribution.

     

Study of CMOS Process Variation by Multiplexing Analog Characteristics

Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic capacitance must be carefully modeled for accurate circuit performance. In this paper we address this need by contributing a test circuit methodology for the extraction of spatial, layout and size dependent variations at both device and interconnect levels. The test chip uses a scan chain approach combined with low-leakage and low-variation switches, and Kelvin sensing connections, providing access to detailed analog device characteristics in large arrays of test devices. Variation measurement using the designed test chip has proven successful for both device and interconnect test structures. The parameter extraction and variation analyses made possible by the variation test chip enable the identification of likely variation sources, quantification of circuit impact and sensitivity, and specification of layout practices for variation minimization.      

TFT AMLCD像素矩阵电路中栅延迟的模拟研究

建立了ａ－ＳｉＴＦＴＡＭＬＣＤ的等效电路模型,综合考虑栅信号线电阻、栅与源信号线的交叠电容以及ＴＦＴ导电沟道电容构成的ＲＣ（ＲｅｓｉｓｔｉｖｉｔｙＣａｐａｃｉｔａｎｃｅ）常数,模拟计算了栅信号延迟对液晶显示屏尺寸、显示分辨率及栅信号电极材料的依赖关系,为实现器件优化设计提供参考。     

车用仪表背光灯的LED线性恒流驱动电路设计

阐述了可用于车用仪表背光灯的高精度LED线性恒流驱动芯片设计,重点讨论在设计并联方式LED线性恒流驱动电路时如何消除连线分布电阻的影响,并推出一种新颖的可消除连线分布电阻影响的电路,最终通过电路模拟测试加以验证.研究结果表明,在设计高精度、高稳定性、大电流、并联方式LED线性恒流驱动电路时,消除连线分布电阻影响很有必要...     

Measurement and Analysis of Inductive Coupling Noise in 90 nm Global Interconnects

Inductive coupling is becoming a design concern for global interconnects in nanometer technologies. We present measurement results of the effect of inductive coupling on timing, and demonstrate that inductive coupling noise is a practical design issue in 90 nm technology. The measured delay change curve is consistent with circuit simulation results for an RLC interconnect model, and clearly different from those for a conventional RC model. The long-range coupling effect of inductive coupling, and noise reduction caused by ground insertion or decreased driver size were clearly observed on silicon. Examination of noise cancellation and superposition effects shown in measurement results confirm that the summation of delay variations due to each individual aggressor is a reasonable approximation of the total delay variation.     

High frequency characterization and modelling of the parasitic RC performance of two terminal ESD CMOS protection devices

This paper describes a simplified high frequency characterization approach to extract the parasitic RC figures of merit of two terminal CMOS electrostatic discharge (ESD) protection devices. Basic RC small signal equivalent models and corresponding parameter extraction procedures, applicable for the most typical structures––grounded gate NMOS, diodes and SCR’s are presented. The model application to study the impact of the ESD failures on the HF device and circuit characteristics is demonstrated.