低硬件成本的高性能Hash算法加速器VLSI设计

本文基于安全Hash算法(SHA-1),提出了一种结构优化的SHA-1硬件加速器.本设计通过改进数据通路,加快了运算单元的速度;同时,采用动态操作数生成的方法,节约了硬件资源.设计采用SMIC0.25μm CMOS工艺综合,其核心电路(core)等效门为16.8k;在86MHz的工作频率下,其数据吞吐率达1.07Gbps.分析结果显示,该硬件加速器具备低成本和高性能的特点,适用于PDA、智能手机等面积受限的移动设备,具有良好的应用前景.     

SHA-2算法在多核密码处理器上的实现研究

为了找出一种适合多核密码处理器的SHA-2算法高速实现方式,提高SHA-2算法在多核密码处理器上的执行速度。首先研究SHA-256、SHA-512算法在密码处理器上的实现方式,并研究多核密码处理器的结构特点与数据传输方式,分析SHA-2算法在多核上的高速实现原理。然后对SHA-2算法进行任务划分,提出SHA-2在多核密码处理器上的调度与映射算法并使用软件实现调度算法。在ASIC上的仿真验证结果表明,经优化后的SHA-2算法在多核上并行执行吞吐率有了较大提升,满足性能上的需求。     

基于LUT的高速低硬件开销SHA-3算法设计

通过对SHA-3算法和查找表(Look-Up-Table,LUT)方法的研究,提出一种高速低硬件开销SHA-3算法设计方案。首先,该方案利用状态机实现SHA-3算法核心置换函数的轮运算,并结合LUT方法处理每轮运算的数据交换和数据存储;然后,采用硬件模块并行处理和存储单元共用的方式,提高SHA-3算法的速度、降低硬件开销。最后,在SMIC 65nm CMOS工艺下设计SHA-3算法,DC综合后电路面积为65 833μm~2,在1.2V电压下最高工作频率可达到150MHz,功耗为2.5mW。     

基于SHA-3的密文数据检索技术

SHA-3算法的研究和应用已成为当前学术研究的热点。针对已有密文数据检索系统检索效率低的问题,在分析和研究已有密文数据检索技术的基础上,利用AES-128算法和SHA-3算法,设计和实现了基于SHA-3的密文数据检索系统。实验证明,该系统能够实现数据库加密、密文精确检索和密文模糊检索,提高密文检索效率,保证数据库安全。二次检索模型和SHA-3算法的使用,使此系统的检索准确性和检索效率达到无索引明文检索的70%。     

基于SHA-256的磁盘复制审计系统设计与实现

随着计算机和互联网络技术的迅速发展,电子数据鉴定的结论成为具有证据力的法定证据之一,文中介绍了电子取证中基于SHA-256算法的磁盘复制审计系统的设计与实现,在分析SHA-256算法的基础上,利用FPGA芯片实现了基于SHA-256算法的磁盘复制审计系统,提出了实现磁盘复制和生成SHA-256哈希值一种电路设计方案;利用SHA-256算法对DMA传输方式中的CRC校验码进行计算得到磁盘数据摘要,从而保证了采集数据的一致性,并且整个复制过程必须是可审计的;最后讨论了基于A1tera公司生产的StratixⅡ系列FPGA的实现结果。     

基于FPGA的SHA-256算法实现

本文分析了SHA-256算法的基本工作流程,对算法硬件实现的关键路径进行了优化设计,讨论了几个关键模块的设计方案。最后给出了基于Altera公司的CYCLONE系列FPGA的实现结果。     

Skein算法的流水线结构设计与实现

硬件实现的速度和性能是SHA-3算法甄选的重要指标。针对SHA-3末轮5个候选算法之一的Skein算法,结合其4轮迭代结构的关键路径较短而8轮迭代结构实现所用的选择器较少的优点,采用FPGA实现了一个两级流水线结构的Skein算法IP核。仿真验证结果表明,该算法在Xilinx Virtex-5上数据吞吐量达到6. 4Gbps,比之前的非流水线结构速度性能提高了82%以上,硬件资源利用率提高了2100,特别适用于Hash树计算。     

单向散列函数SHA-512的优化设计

在分析NIST的散列函数SHA-512基础上,对散列函数SHA-512中的关键运算部分进行了分解,通过采用中间变量进行预行计算,达到了SHA-512中迭代部分的并行计算处理,提高了运算速度。通过这种新的硬件结构,优化后的散列函数SHA-512在71.5MHz时钟频率下性能达到了1 652Mbit/s的数据吞吐量,比优化前性能提高了约2倍,最后还将实验结果与MD-5、SHA-1商用IP核性能进行了比较。     

SHA-1算法的HDL设计与仿真

随着宽带网络和数字视频的飞速发展,如何加强对数据内容的保护成为迫切需要解决的问题.HDCP是一种目前最有效的版权保护协议.它正是采用了SHA-1算法来验证信息传输的完整性.基于HDL语言的硬件设计方法,可以方便地设计硬件电路,建立SHA-1的算法模型,包括码流填充过程和压缩计算过程.用Veriiog HDL描述的电路,其综合结果可通过仿真验证.采用电路结构设计的SHA-1功能模块,简洁高效,可方便地在可编程逻辑器件中实现,并且已在多个嵌入式系统的设计中得到了应用和验证.     

安全散列算法SHA-1的研究

信息加密技术是当今保障网络安全的一种重要手段,加密算法已成为人们研究的一个热点。对SHA-1算法进行了深入研究,介绍了SHA-1算法的特性和应用,并对SHA-1算法原理及实现进行了分析。     

应用于后量子密码的高速高效SHA-3硬件单元设计

随着量子计算技术的高速发展,传统的公钥密码体制正在遭受破译的威胁,将现有加密技术过渡到具有量子安全的后量子密码方案上是现阶段密码学界的研究热点。在现有的后量子密码(Post-Quantum Cryptography,PQC)方案中,基于格问题的密码方案由于其安全性,易实施性和使用灵活的众多优点,成为了最具潜力的PQC方案。SHA-3作为格密码方案中用于生成伪随机序列以及对关键信息散列的核心算子之一,其实现性能对整体后量子密码方案性能具有重要影响。考虑到今后PQC在多种设备场景下部署的巨大需求,SHA-3的硬件实现面临着高性能与有限资源开销相互制约的瓶颈挑战。对此,本文提出了一种高效高速的SHA-3硬件结构,这种结构可以应用于所有的SHA-3家族函数中。首先,本设计将64 bit轮常数简化为7 bit,既减少了轮常数所需的存储空间,也降低了运算复杂度。其次,提出了一种新型的流水线结构,这种新型结构相比于通常的流水线结构对关键路径分割得更加均匀。最后,将新型流水线结构与展开的优化方法结合,使系统的吞吐量大幅提高。本设计基于XilinxVirtex-6现场可编程逻辑阵列(FPGA)完成了原型实现,结果显示,所设计的SHA-3硬件单元最高工作频率可达459 MHz,效率达到14.71 Mbps/Slice。相比于现有的相关设计,最大工作频率提高了10.9%,效率提升了28.2%。     

SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative

This paper proposes the architecture of the hash accelerator, developed in the framework of the European Processor Initiative. The proposed circuit supports all the SHA2 and SHA-3 operative modes and is to be one of the hardware cryptographic accelerators within the crypto-tile of the European Processor Initiative. The accelerator has been verified on a Stratix IV FPGA and then synthesised on the Artisan 7 nanometres TSMC silicon technology, obtaining throughputs higher than 50 Gbps for the SHA2 and 230 Gbps for the SHA-3, with complexity ranging from 15 to about 30 kGE and estimated power dissipation of about 13 (SHA2) to 26 (SHA-3) mW (supply voltage 0.75 V). The proposed design demonstrates absolute performances beyond the state-of-the-art and efficiency aligned with it. One of the main contributions is that this is the first SHA-2 SHA-3 accelerator synthesised on such advanced technology.     

Compact and unified hardware architecture for SHA-1 and SHA-256 of trusted mobile computing

This paper presents a compact and unified hardware architecture implementing SHA-1 and SHA-256 algorithms that is suitable for the mobile trusted module (MTM), which should satisfy small area and low-power condition. The built-in hardware hash engine in a MTM is one of the most important circuit blocks and dominates the performance of the whole platform because it is used as a key primitive to support most MTM commands concerning to the platform integrity and the command authentication. Unlike the general trusted platform module (TPM) for PCs, the MTM, that is to be employed in mobile devices, has very stringent limitations with respect to available power, circuit area, and so on. Therefore, MTM needs the spatially optimized architecture and design method for the construction of a compact SHA hardware. The proposed hardware for unified SHA-1 and SHA-256 component can compute a sequence of 512-bit data blocks and has been implemented into 12,400 gates of 0.25 μm CMOS process. Furthermore, in the processing speed and power consumption, it shows the better performance in comparison with commercial TPM chips and software-only implementation. The highest operation frequency and throughput of the proposed architecture are 137 MHz and 197.6 Mbps, respectively, which satisfy the processing requirement for the mobile application.     

Hardware implementation analysis of SHA-256 and SHA-512 algorithms on FPGAs

Hash functions are common and important cryptographic primitives, which are very critical for data integrity assurance and data origin authentication security services. Field programmable gate arrays (FPGAs) being reconfigurable, flexible and physically secure are a natural choice for implementation of hash functions in a broad range of applications with different area-performance requirements. In this paper, we explore alternative architectures for the implementation of hash algorithms of the secure hash standards SHA-256 and SHA-512 on FPGAs and study their area-performance trade-offs. As several 64-bit adders are needed in SHA-512 hash value computation, new architectures proposed in this paper implement modulo-64 addition as modulo-32, modulo-16 and modulo-8 additions with a view to reduce the chip area. Hash function SHA-512 is implemented in different FPGA families of ALTERA to compare their performance metrics such as area, memory, latency, clocking frequency and throughput to guide a designer to select the most suitable FPGA for an application. In addition, a common architecture is designed for implementing SHA-256 and SHA-512 algorithms.     

Implementation of the SHA-2 Hash Family Standard Using FPGAs

The continued growth of both wired and wireless communications has triggered the revolution for the generation of new cryptographic algorithms. SHA-2 hash family is a new standard in the widely used hash functions category. An architecture and the VLSI implementation of this standard are proposed in this work. The proposed architecture supports a multi-mode operation in the sense that it performs all the three hash functions (256, 384 and 512) of the SHA-2 standard. The proposed system is compared with the implementation of each hash function in a separate FPGA device. Comparing with previous designs, the introduced system can work in higher operation frequency and needs less silicon area resources. The achieved performance in the term of throughput of the proposed system/architecture is much higher (in a range from 277 to 417%) than the other hardware implementations. The introduced architecture also performs much better than the implementations of the existing standard SHA-1, and also offers a higher security level strength. The proposed system could be used for the implementation of integrity units, and in many other sensitive cryptographic applications, such as, digital signatures, message authentication codes and random number generators.     

Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions’ architectures

Many cryptographic primitives that are used in cryptographic schemes and security protocols such as SET, PKI, IPSec and VPN's utilize hash functions - a special family of cryptographic algorithms. Hardware implementations of cryptographic hash functions provide high performance and increased security. However, potential faults during their normal operation cause significant problems in the authentication procedure. Hence, the on-time detection of errors is of great importance, especially when they are used in security-critical applications, such as military or space. In this paper, two Totally Self-Checking (TSC) designs are introduced for the two most-widely used hash functions: SHA-1 and SHA-256. To the best of authors’ knowledge, there is no previously published work presenting TSC hashing cores. The achieved fault coverage is 100% in the case of odd erroneous bits. The same coverage is achieved for even erroneous bits, if they are appropriately spread. Additionally, experimental results in terms of frequency, area, throughput, and power consumption are provided. Compared to the corresponding Duplicated with Checking (DWC) architectures, the proposed TSC-based designs are more efficient in terms of area, throughput/area, and power consumption. Specifically, the introduced TSC SHA-1 and SHA-256 cores are more efficient by 16.1% and 20.8% in terms of area and by 17.7% and 23.3% in terms of throughput/area, respectively. Also, compared to the corresponding DWC architectures, the proposed TSC-based designs are on average almost 20% more efficient in terms of power consumption.     

SHA-1加密算法的硬件设计

该文介绍了一种在消息验证领域普遍使用的加密算法———SHA-1,阐述了硬件设计的思想和优化方法,以及用现场可编程逻辑阵列(FPGA)进行测试的结果。该设计在计算机安全领域有广泛的用途。     

SHA-2(512)热噪声随机数发生器

密码学的快速发展，使得安全协议和密码算法的强度越来越依赖于随机数质量。该文提出了一种新的安全随机数发生器结构，该结构是基于SHA-2(512)哈希函数，该函数的强度确保所生成随机数的不可预测性。给出了该函数的FPGA实现结构。考虑到性能、功耗、灵活性、费用和面积等要求，所提出的结构在许多应用中都是一种灵活解决方案。