Interoperability Verification in ISO 18000-7 Active RFID Systems: Experimental Setup and Results

Interoperability in an RFID system conforming to ISO 18000-7 standard is defined as the ability of any commercial interrogator to communicate with any commercial tag. A possibility that conformance verification in the physical communication layer between active tags and interrogators (readers) does not satisfy the interoperability property is established. Challenging the traditional or matrix test to verify interoperability, a novel methodology to verify interoperability for active RFID systems in particular and all communication systems following a command-reply protocol in general is introduced in a prior publication. In this article, the methodology is experimentally implemented using industry standard laboratory equipment and automation tools to develop a fully automated interoperability test suite. The automated test system design considerations, challenges and results are discussed in detail. For a particular equipment, the NI-5671 Radio Frequency Signal generator, the maximum number of samples that can be tested for different parameters of the physical communication layers are provided. The equipment limitations are discussed to provide the reader with guidelines to experiment with, and a reference to evaluate the resolution (one measure of the accuracy of the test) of different equipment. The different parameters considered in the test and their interactions in determining the interoperability property are recorded.     

基于ISO18000-6C标准的RFID认证协议

RFID技术应用越来越广,给人们带来便利的同时安全和隐私问题也相随而生,如何提高RFID系统的安全防范能力已成为该领域的重点研究方向。许多研究者提出了基于RFID空中接口通信的认证协议,但复杂的算法难以适用于符合ISO18000-6C标准的电子标签。论文根据ISO18000-6C标准提出了一种新的适合低成本标签的认证协议,为RFID安全提供了一套解决方案。     

一种基于ISO 18000-6B标准的RFID防碰撞算法

在射频识别（RFID）系统中,防碰撞算法用来确保读写器工作范围内的所有标签被正确识别。本文在树形搜索算法的基础上,提出了一种有效的防碰撞算法来提高RFID系统的性能。该算法性能的提升依赖于读写器查询方式的建立和碰撞位数据的映射。在算法的设计中考虑了平均请求周期、传输数据的长度和能量效率等指标。仿真结果表明,该算法在时间复杂度,通信开销和能量效率这三个性能指标上有显著的提升。     

面向ISO18000-6C协议的无源超高频射频识别标签芯片设计

本文提出了一种面向ISO18000-6C协议的无源超高频射频识别标签芯片设计。为了降低芯片的成本和功耗,本文设计了一种低功耗且不含电阻的稳压电路,一种低功耗且频率精度达到4%的时钟产生电路,以及一种新颖的具有大动态范围的ASK解调电路。本文还阐述了基于门控时钟技术的低功耗数字基带电路设计。该标签芯片的总功耗约为14微瓦,灵敏度达到-9.5dBm,读取距离可达5米。整个标签采用TSMC 0.18um CMOS工艺实现,芯片尺寸为880um880um。     

Design of a passive UHF RFID tag for the ISO18000-6C protocol

This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO18000-6C protocol.In order to reduce the die area,an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted.A low power clock generator is designed to guarantee the accuracy of the clock under±4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor,the total power consumption of the tag is about 14μW with a sensitivity of-9.5 dBm.The detection distance can reach about 5 m under 4 W effective isotropic radiated power.The whole tag is fabricated in TSMC 0.18μm CMOS technology and the chip size is 880×880μm~2.     

RFID MAC Performance Evaluation Based on ISO/IEC 18000-6 Type C

This paper evaluates a new RFID reservation MAC protocol that utilizes tree based collision avoidance. Performance evaluation is conducted for tag read latency and read efficiency as a function of link parameters defined in ISO/IEC 18000-6 Type C standard.     

符合ISO/IEC 18000-6C标准的UHF RFID读写器设计

在超高频段,ISO/IEC 18000-6标准中6B多用于交通领域,而6C主要用于物流、生产管理和供应链管理领域.分析了ISO/IEC 18000-6 C标准,基于此标准设计了一种超高频射频识别读写器.详细阐述了读写器的软硬件设计,其中硬件设计主要包括射频发送电路、射频接收电路和数字基带处理电路.读写器软件设计中叙述了整体设计结构、基于概率、槽计数器的防冲突算法、发送接收链路的数据编解码设计、16 bit CRC校验以及读写器对标签操作命令流程.     

RFID空中接口符合性测试与互操作性测试概述

详细介绍了RFID空中接口符合性测试和互操作性测试,同时定义了RFID测试的类别划分。描述了RFID空中接口符合性测试系统以及RFID互操作性测试的测试方法。     

自主知识产权RFID标准系列报道（三） 中兴长天2.45GHz协议与ISO/IEC 18000-4、-7协议比较研究

分别介绍了2.45 GHz乖口433 MHz频率下的ISO/IEC 18000-4和-7空中接口协议以及中兴长天2.45 GHz空中接口协议的主要内容、特点和应用场合,对比和分析这三种协议的防碰撞算法、通信过程、编码方式等,指出算法改进的方向.     

ISO/IEC18000-6B标签逻辑电路低面积设计

简要介绍了射频识别技术(RFID)协议ISO/IEC 18000-6B的通信,并基于该协议用VHDL语言设计了标签的逻辑部分电路.设计时运用命令分类、实时处理、资源共享等技术减少硬件资源,在SMIC 0.18μm工艺下综合为24 791μm2,并用Primepower测得功耗约10.6μW.设计采用Xilinx的FPGA开发平台进行了验证,逻辑分析仪结果表明设计满足要求.该电路应用于ISO/IEC18000-6B协议下RFID标签的数字部分.     

ISO/IEC 18000-6(CD)研究综述

介绍了射频识别技术(RFID)在UHF频段的ISO／IEC 18000-6(CD)的标准草案及其主要内容、特点和发展前景，对标准中两种类型的技术作了分析和对比，并结合未来的发展趋势指出了现有标准中有待改进的方面。     

ISO/IEC 18000-6C简析

介绍了RFID技术,以及ISO/IEC 18000-6系列等RFID技术UHF频段标准的发展、完善历程,重点分析了ISO/IEC 18000-6中A、B、C三种模式的优缺点,针对中国UHF频段的标准制定提出了技术和应用层面的建议.     

一种ISO18000-6B防碰撞算法重复搜索问题的解决方法

本文在研究了UHF频段RFID的ISO/IEC18000-6B空中接口标准的基础上,对ISO/IEC18000-6B防碰撞算法中出现的重复搜索问题,提出了一种易于实现的改进算法,并使用OPNET构建ISO/IEC18000-6B标准的仿真平台,由仿真平台的分析结果可知改进算法能够有效减少标签的识别时间,降低碰撞次数.     

IS018000—6中的FMO编码和PIE编码的编码技术

基带数据的编码是RFID系统中的关键技术。ISO18000-6作为超高频段RFID的最新国际标准,规定了阅读器和标签之间通信分别采用FMO编码和PIE编码,但标准中并未给出编码枝术的具体实现方法。本文提出的这两种编码的编码技术,方法简单、易于实现,在RFID的应用中能体现出很好的实用价值。     

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags in conformance with ISO/IEC 18000-3 protocol

A fully integrated analog front-end circuit for 13.56 MHz passive RFID tags is presented in this paper. The design of the RF analog front-end and digital control is based on ISO/IEC 18000-3 MODE 1 protocol. This paper mainly focuses on RF analog front-end circuits. In order to supply voltage for the whole tag chip, a high efficiency power management circuit with a rather wide input range is proposed by utilizing 15.5 V high voltage MOS transistors. Furthermore, a high sensitivity, low power consumption 10% ASK demodulator with a subthreshold-mode hysteresis comparator is introduced for reader-to-tag communication. The tag chip is fabricated in 0.18-μm 2-poly 5-metal mixed signal CMOS technology with EEPROM process. An on-chip 1 kb EEPROM is used to support tag identification, data writing and reading. The core size of the analog front-end is only 0.94×0.84 mm² with a power consumption of 0.42 mW. Measured results show that the power management circuit is able to maintain a proper working condition with an input antenna voltage range of 5.82–12.3 V; the maximum voltage conversion ratio of the rectifier reaches 65.92% when the tag antenna voltage is 9.42 V. Moreover, the power consumption of the 10% ASK demodulator is only 690.25 nW.     

超高频RFID无线接口标准ISO／IEC 18000-6C的研究

继ISO／IEC 18000-6A、B之后的ISO／IEC 18000-6C,它对前两种模式的协议特点进行了一系列有效的修正与扩充。其中物理层数据编码、调制方式、防碰撞算法等一些关键技术有了改进,使得ISO／IEC 18000-6C的性能比A、B有了很大的提高。本文介绍了ISO／IEC 18000-6C标准的协议特点及其与A、B之间的比较。     

现场总线的一致性测试和互操作性测试

参照ISO9646介绍了一致性测试的一些基本概念和过程，分析了它的一些缺陷和不足，对互扣作性测试的概念，分类，测试方法等各方面也进行了介绍和分析，并将互操作性测试和一致性测试进行了比较，从而能在理解一致性测试的基础更好地理解互操作性测试。     

Design and Performance Analysis of Emulator for Standard Conformance Test of Active RFID

An active radio frequency identification (RFID) system has the advantages of a long identification distance and a good identification rate, overcoming passive RFID drawbacks. Therefore, interest in the development of active RFID systems has been gradually increasing in areas of harbor logistics and national defense. However, some identification failures between active RFID systems developed under the same standards have been reported, presumably due to a lack of development of accurate evaluation methods and test equipment. We present a realization of the hardware and software of an emulator to evaluate the standard conformance of an active RFID system in a fully anechoic chamber. The performance levels of the designed emulator are analyzed using Matlab/Simulink simulations, and the applicability of the emulator is verified by evaluating the standard conformance of a real active RFID tag. Finally, we propose a new evaluation method by incorporating a self‐running test mode environment into the RFID tags to reduce testing time and increase testing accuracy. The application of the suggested method to actual tags improves measurement uncertainty by 0.56 dB over that obtained using existing methods.     

基于ISO／IECl8000-6标准的射频识别系统的FPGA设计及实现

介绍了ISO／IECl8000-6标准以及基于此标准的通信协议。提出了基于FPGA的900MHz射频识别（RFID）系统数字逻辑部分的实现方法，包括曼彻斯特码的编解码、信号的处理和发送以及反碰撞技术等。该方法具有处理速度快，电路形式简单，移植方便等优点，适合工程应用。