扩展到整数类型范围的模的模乘算法

针对模乘运算的模超过一半整数位会发生算术溢出,不使用高精度运算就无法处理的问题,提出一种利用同余关系缩小乘积的模乘算法。通过将整数分解成两位数,按照两位数乘法的原理,将高位部分乘积用同余关系缩小,避免了乘法运算过程的算术溢出。结果表明,该方法可以将64位整数为基础的模乘运算的模扩大到62位。     

一种有限域快速低功耗模乘电路设计与实现

有限域的运算是密码学的基础,而在有限域的运算中模乘运算是核心运算之一。为此,分析了模乘运算的原理及特点,使用Verilog HDL设计模乘电路,通过FPGA实现了基于有限域的模乘运算。电路应用双沿寄存器结构,并且规模小、速度快、功耗低能实现有限域通用模乘运算对加密算法的硬件实现具有实际价值。     

二进制域运算在DSP上的优化

主要研究二进制域运算在DSP上的实现。通过设置多个中间变量，实现了对数组的并行计算，将最佳正规基模乘算法提高到6级流水。重构almost inversion多项式基模逆算法结构，消除跳转语句，实现程序设计模块化。在TMS320C6204上执行113位和191位算法证实确实提高了模乘和模逆两种运算的速度。以循环移位取代乘法的模乘算法，限制了C6201的流水深度。     

一种通用GF(2m)模乘加速器的快速实现

在椭圆曲线密码体制(ECC)中,有限域GF(2m)上模乘运算是最基本的运算,加速模乘运算是提高ECC算法性能的关键。针对不同不可约多项式广泛应用的现状,提出了一种通用GF(2m)模乘加速器设计方案。该加速器通过指令调度的方式,能快捷地完成有限域上模乘运算。实现结果表明,该设计完全适用于智能卡等应用要求。     

Bipartite modular multiplication with twice the bit-length of multipliers

This paper presents a new technique to compute 2ℓ-bit bipartite multiplications with ℓ-bit bipartite multiplication units. Low-end devices such as smartcards are usually equipped with crypto-coprocessors for accelerating the heavy computation of modular multiplications; however, security standards such as NIST and EMV have declared extending the bit length of RSA cryptosystem to resist mathematical attacks, making the multiplier quickly outdated. Therefore, the double-size techniques have been studied this decade to extend the life expectancy of such multipliers. This paper proposes new double-size techniques based on the multipliers implementing either classical or Montgomery modular multiplications, or even both simultaneously (bipartite modular multiplication), in which case one can potentially compute modular multiplications twice faster. Furthermore, in order to get a more realistic estimation than the other works, this paper considers not only the cost of the multiplication, but also the cost of the other arithmetic instructions. In our estimation, the proposal provides comparable results for classical multiplier and Montgomery multiplier, and is the only available method for the bipartite multiplier. A preliminary version of this paper was presented at the 12th Australasian Conference on Information Security and Privacy, ACISP’07.     

GF（2m）域上快速模乘处理结构的研究与设计

加速GF(2m)上的模乘运算是提高GF(2^m)上ECC算法性能的关键。在分析EC上点乘操作的基础上，我们构造了模乘运算在线性Systolic上实现的局部并行处理递推形式，并设计了Systolic阵列的具体单元结构和连接，给出了性能分析和模拟结果。实验证明，局部并行阵列结构能适应多种EC上的模乘处理。     

GF(2~m)上椭圆曲线密码体制的硬件实现

特征为2的有限域GF(2m)较适合椭圆曲线密码算法的硬件实现。该文通过对GF(2m)上模运算的分析,将所有的模运算转化成模乘和模加,并对LSD乘法器的进行了改进,所设计的运算单元能进行GF(2m)上所有的模运算,利用该运算单元所实现的椭圆曲线密码算法具有面积小,速度快的优点,适合用于处理能力和存储空间受限的设备中。     

Recursion-free modular arithmetic in the lambda-calculus

We investigate encodings for modular arithmetic in the lambda-calculus. There are two approaches: adapting well-known numeral systems, and building a new one. This paper focuses on providing original techniques to encode modular arithmetic directly. We present a modular arithmetic numeral system complete with multiplication and an implementation of the Chinese remainder theorem, all without recursion i.e., without using fixed-point operators.     

有限域模乘专用指令设计

针对椭圆曲线密码算法中有限域模乘运算的需求,提出其专用模乘指令。利用指令域中的组参数实现算法多组模乘运算,通过对参数进行配置,使指令支持运算长度拓展,在模乘运算单元中实现Montgomery模乘算法,并设计素域和二进制域统一的硬件流水线,以及双域乘法器单元结构。实验结果表明,该有限域模乘指令和硬件运算单元具有较高的执行效率和较好的灵活性。     

一种高性能大数模运算单元及其应用

为了加速公钥密码系统的实现速度,设计支持大教模乘和模加减运算的模运算单元是关键.目前的方法多关注于这两种运算的分别实现,为了改善这种方式导致的硬件单元吞吐量低的问题,提出了一种流水线结构的高性能大数模运算单元.基于改进的Montgomery模乘算法,采用流水线技术,把模乘电路分成3个流水线阶段,并把模加减电路结合到第3阶段,得到一种能同时计算模乘和模加减的模运算单元.仿真结果显示,模运算单元以较少的资源占用率获得了较高的吞吐量,非常适合做高性能的公钥密码系统的基本硬件运算单元.     

GF(2m)上椭圆曲线密码协处理器的硬件实现

给出了一款GF(2m)上椭圆曲线密码协处理器的描述。对于椭圆曲线密码学中最关键的模乘运算采用蒙格玛利模乘算法，并且对这种算法进行改进，得到一种通用性较强的算法。对于硬件实现中遇到的判断寄存器是否为零，给出了一种快速方法。该协处理器共分为6部分，分别为：主控制单元，椭圆曲线点乘单元，椭圆曲线点加单元，椭圆曲线点倍单元，有限域加法单元，蒙格玛利模乘算法单元。     

一种新的大整数乘法算法

为解决超出计算机系统基本整数类型表达能力的整数(大整数)算术运算问题,以基础算法--大整数乘法为研究对象,根据大整数的表示形式与多项式表示形式上的相似性,结合大整数乘法进位与取模的特点,给出了一种关于大整数乘法的多项式算法.其方法与别的方法最大的不同是,虽然是求两个大整数乘法,但整个算法没有使用乘法,只是用加法运算而已...     

Montgomery exponent architecture based on programmable cellular automata

This study presents an efficient exponent architecture for public-key cryptosystems using Montgomery multiplication based on programmable cellular automata (PCA). Multiplication is the key operation in implementing circuits for cryptosystem, as the process of encrypting and decrypting a message requires modular exponentiation which can be decomposed into multiplications. Efficient multiplication algorithm and simple architecture are the key for implementing exponentiation. Thus we employ Montgomery multiplication algorithm and construct simple architecture based on irreducible all one polynomial (AOP) in GF(2^m). The proposed architecture has the advantage of high regularity and a reduced hardware complexity based on combining the characteristics of the irreducible AOP and PCA. The proposed architecture can be efficiently used for public-key cryptosystem.     

并行设计的高性能随机椭圆曲线加密协处理器

为加速椭圆曲线加密的运算,本文提出了一种新的并行设计的椭圆曲线加密处理器结构。该处理器采用的模运算单元的特点是含有两个模乘、一个模加和一个模平方模块。两个模乘可以并行运算,而且在模乘运算的同时可并行完成模加或模平方的运算。Xilinx公司的VirtexE XCV2600 FPGA硬件实现结果表明,完成有限域GF(2163)上任意椭圆曲线上的一次标量乘的全部运算只需3064个时钟,时间消耗为31.17μs,资源消耗为3994个寄存器和15527个查找表,适合高性能椭圆曲线加密应用的要求。     

GF(2m)域上快速模乘处理局部并行结构

在分析EC上点乘操作的基础上,构造了MSB方式下局部并行线性systolic结构的模乘递推形式,设计了具体的单元结构,给出了性能分析和模拟比较结果。实验证明MSB方式下局部并行、域多项式可变的阵列结构能适应多种EC上模乘,实现灵活、高速的模乘处理,而局部并行、固定域多项式结构能在较优的硬件代价下高效实现特定EC上模乘,有效提高GF(2m)上ECC算法的性能。     

Recursion based parallelization of exact dense linear algebra routines for Gaussian elimination

We present block algorithms and their implementation for the parallelization of sub-cubic Gaussian elimination on shared memory architectures. Contrarily to the classical cubic algorithms in parallel numerical linear algebra, we focus here on recursive algorithms and coarse grain parallelization. Indeed, sub-cubic matrix arithmetic can only be achieved through recursive algorithms making coarse grain block algorithms perform more efficiently than fine grain ones. This work is motivated by the design and implementation of dense linear algebra over a finite field, where fast matrix multiplication is used extensively and where costly modular reductions also advocate for coarse grain block decomposition. We incrementally build efficient kernels, for matrix multiplication first, then triangular system solving, on top of which a recursive PLUQ decomposition algorithm is built. We study the parallelization of these kernels using several algorithmic variants: either iterative or recursive and using different splitting strategies. Experiments show that recursive adaptive methods for matrix multiplication, hybrid recursive–iterative methods for triangular system solve and tile recursive versions of the PLUQ decomposition, together with various data mapping policies, provide the best performance on a 32 cores NUMA architecture. Overall, we show that the overhead of modular reductions is more than compensated by the fast linear algebra algorithms and that exact dense linear algebra matches the performance of full rank reference numerical software even in the presence of rank deficiencies.     

GF（3^m）椭圆曲线群快速算术运算研究

详细研究了GF(3m)上椭圆曲线基本算术运算,给出并证明GF(3m)上超奇异和非超奇异椭圆曲线仿射坐标系下点加、倍点、3倍点和3k倍点计算公式.提出高效3k倍点递归算法,在逆乘率较高时,其效率要优于逐次3倍点算法.在此基础上,提出一种新的变长滑动窗口wrNAF标量乘算法,其在保证较少点加法运算优点的同时可有效降低3倍点的计算量.     

Improving the computational efficiency of modular operations for embedded systems

Security protocols such as IPSec, SSL and VPNs used in many communication systems employ various cryptographic algorithms in order to protect the data from malicious attacks. Thanks to public-key cryptography, a public channel which is exposed to security risks can be used for secure communication in such protocols without needing to agree on a shared key at the beginning of the communication. Public-key cryptosystems such as RSA, Rabin and ElGamal cryptosystems are used for various security services such as key exchange and key distribution between communicating nodes and many authentication protocols. Such public-key cryptosystems usually depend on modular arithmetic operations including modular multiplication and exponentiation. These mathematical operations are computationally intensive and fundamental arithmetic operations which are intensively used in many fields including cryptography, number theory, finite field arithmetic, and so on. This paper is devoted to the analysis of modular arithmetic operations and the improvement of the computation of modular multiplication and exponentiation from hardware design perspective based on FPGA. Two of the well-known algorithms namely Montgomery modular multiplication and Karatsuba algorithms are exploited together within our high-speed pipelined hardware architecture. Our proposed design presents an efficient solution for a range of applications where area and performance are both important. The proposed coprocessor offers scalability which means that it supports different security levels with a cost of performance. We also build a system-on-chip design using Xilinx’s latest Zynq-7000 family extensible processing platform to show how our proposed design improve the processing time of modular arithmetic operations for embedded systems.     

对称密码中复合域乘法运算可重构设计研究

复合域乘法运算是对称密码算法中的基本运算和重要模块,因操作复杂且计算时间长,其实现性能在很大程度上制约着对称密码算法的运算速度。文章研究了对称密码算法中的复合域乘法运算特点及实现原理,设计了以GF（28）为基域,扩展到GF（（28 ）h（k=1,2,3,4）域上的复合域乘法可重构架构,通过配置能够灵活高效地实现GF（2 8）、GF（（2H）2）、GF（2 8）3、CF（（28）4）域上的有限域乘法操作。同时结合处理器的指令设计方法,设计了通用的复合域乘法操作及配置指令,能够极大的提高对称密码算法中复合域乘法运算的处理效率。最后文章对复合域乘法可重构架构进行了模拟与验证,在0．18μmCMOS工艺标准单元库下进行逻辑综合以及布局布线,并对综合结果进行了性能评估。结果表明,文章提出的复合域乘法可重构架构及相应的专用指令,在灵活性的前提下提供了较高的执行效率,具有较高的实用价值。     

正规基中模乘算法的FPGA实现方法研究

给出了GF(2m)上椭圆曲线密码系统中最佳正规基表示的模乘运算优化算法,提出了该算法的FPGA实现方案,并详细分析了实现该算法的有限状态机模型。结合Xilinx的FPGA器件,用VerilogHDL编写了实现该有限状态机的代码,在ISE和ModelSim开发工具中通过仿真、综合。试验表明,该文实现的模乘方案较其他实现方案具有较高的速度,并在EC-Elgamal密码体系中得到较好的应用。