Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

Compact Performance Models and Comparisons for Gigascale On-Chip Global Interconnect Technologies

The on-chip global interconnect with conventional Cu/low-k and delay-optimized repeater scheme faces great challenges in the nanometer regime owing to its severe performance degradation. This paper describes the analytical models and performance comparisons of novel interconnect technologies and circuit architectures to cope with the interconnect performance bottlenecks. Carbon nanotubes (CNTs) and optics-based interconnects exhibit promising physical properties for replacing the current Cu/low-k-based global interconnects. We quantify the performance of these novel interconnects and compare them with Cu/low-k wires for future high-performance integrated circuits. The foregoing trends are studied with technology node and bandwidth density in terms of latency and power dissipation. Optical wires have the lowest latency and power consumption, whereas a CNT bundle has a lower latency than Cu. The new circuit scheme, i.e., “capacitively driven low-swing interconnect (CDLSI),” has the potential to effect a significant energy saving and latency reduction. We present an accurate analytical optimization model for the CDLSI wire scheme. In addition, we quantify and compare the delay and energy expenditure for not only the different interconnect circuit schemes but also the various future technologies, such as Cu, CNT, and optics. We find that the CDLSI circuit scheme outperforms the conventional interconnects in latency and energy per bit for a lower bandwidth requirement, whereas these advantages degrade for higher bandwidth requirements. Finally, we explore the impact of the CNT bundle and the CDLSI on a via blockage factor. The CNT shows a significant reduction in via blockage, whereas the CDLSI does not help to alleviate it, although the CDLSI results in a reduced number of repeaters due to the differential signaling scheme.      

Ultra-low power FinFET-based domino circuits

Aggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode.     

Design and analysis of a low-swing driver scheme for long interconnects

Market forces are continually demanding devices with increased functionality/unit area; these demands have been satisfied through aggressive technology scaling which, unfortunately, has impacted adversely on the global interconnect delay subsequently reducing system performance. Line drivers have been used to mitigate the problems with delay; however, these have large power consumption. A solution to reducing the power dissipation of the drivers is to use lower supply voltages. However, by adopting a lower power supply voltage, the performance of the line drivers for global interconnects is impaired unless low-swing signalling techniques are implemented. The paper describes the design of a low-swing signalling scheme which consists of a low-swing driver, called the nLVSD driver which is an improved version of the MJ-driver [1] designed by Juan A. Montiel-Nelson and Jose C. Garcia. Subsequently, both low-swing driver schemes are analysed and compared focusing on their power consumption and performance characteristics, which are the main issues in present day IC design. A comparison between the two driver schemes showed that the nLVSD driver exhibited a 34% improvement regarding power consumption and a 28% improvement in delay when driving a 10 mm length of interconnect. A comparison between the two schemes was also undertaken in the presence of ±3σ Process and Voltage (PV) variations. The analysis indicated that the nLVSD driver scheme was more robust than the MJ-driver with a 33% and 44% improvement with respect to power consumption and delay variations. In order to further improve the robustness of the nLVSD scheme against process variation, the scheme was further analysed to identify which process variables had the most impact on circuit delay and power consumption. For completeness the effects of process variation on interconnect delay and power consumption was also undertaken.     

Shielding effect of on-chip interconnect inductance

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.     

基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

FinFET domino logic with independent gate keepers

Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% and the power consumption is reduced by up to 46% as compared to the standard domino logic circuits designed for similar noise margin in a 32 nm FinFET technology.     

互连线和CMOS模型对性能影响的分析

在集成电路中,全局互连线的设计是关键.分析了互连线RC和RLC模型的不同特性;针对互连线与CMOS器件级联的电路进行分析.分析了集成电路中互连线和CMOS的模型对性能的影响,并给出了基于HSPICE软件的仿真结果.仿真结果表明,不同互连线和CMOS模型对系统传输特性有一定影响.     

工艺变化下互连线分布参数随机建模与延迟分析

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,电路制造过程中的工艺变化已经成为影响集成电路互连线传输性能的重要因素.文中引入高斯白噪声建立了互连线分布参数的随机模型,并提出基于Elmore延迟度量的工艺变化下的互连延迟估计式;通过简化工艺变化量与互连线参数之间的关系式,对延迟一阶变化量与二阶变化量进行了分析,给出一般工艺变化下互连延迟的统计特性计算方法;另,针对线宽工艺变化推导出互连延迟均值与方差的计算公式.最后通过仿真实验对工艺变化下互连线延迟分析方法及其统计特性计算公式的有效性进行了验证.     

An innovative interconnect structure with improved Elmore delay estimation model for deep submicron technology

With advancements in technology, size and speed have been the important facet in VLSI interconnects. The channel length of the device reduces to tens of nanometers, as the technology is transferring to the deep submicron level. This leads to the requirement of long interconnects in VLSI chips. Interconnects are known as the basic building block that can vary from size to size. They provide a connection between two or more blocks and have scaling problems that an IC designer faces while designing. As scaling increases, the impact of interconnect in the VLSI circuits became even more important. It controls all the important electrical characteristics on the chip. With scale-down technology, interconnects not only become closer with each other but their dimensions also change which can directly impact the circuit parameters. Certain RC models have already been defined to control these parameters but in this paper, authors have proposed a new improved Elmore delay estimation model (RC) to reduce delay and power consumption in interconnect circuits. An optimized Elmore delay calculation was performed for uniform and non-uniform wires to reduce the time constant of the interconnect circuits. Further, the proposed model is estimated and verified theoretically. A new improved RC model is compared to the designed π-model that shows remarkable results. We also observed the linear relationship of power consumption and delay for both the RC models and found that in π-model, upon decreasing the length of wire the power first increases then decreases but in the proposed model, the power first increases then remain constant and then further increases upon increasing the length of wire. Our proposed model shows the remarkable values as the average percentage improvement of power is 75.167% and delay as 74.714% is achieved using a uniform distribution.

     

An Interconnect Scaling Scheme with Constant On-Chip Inductive Effects

This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS [1], interconnects become extremely resistive and, while inductance effects diminish with scaling but the performance, specifically, delay per unit length, degrades with scaling. The effect of the proposed global interconnect scaling scheme on optimized driver size, interconnect length, delay per unit length and total buffer area is quantified and compared with the unscaled and the ITRS cases. It is shown that the proposed scaling scheme improves the delay per unit length without degrading inductive effects or increasing buffer area with scaling.     

Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects

Metallic carbon nanotubes (CNTs) have received much attention for their unique characteristics as a possible alternative to Cu interconnects in future ICs. Until this date, while almost all fabrication efforts have been directed toward multiwalled CNT (MWCNT) interconnects, there is a lack of MWCNT modeling work. This paper presents, for the first time, a detailed investigation of MWCNT-based interconnect performance. A compact equivalent circuit model of MWCNTs is presented for the first time, and the performance of MWCNT interconnects is evaluated and compared against traditional Cu interconnects, as well as Single-Walled CNT (SWCNT)-based interconnects, at different interconnect levels (local, intermediate, and global) for future technology nodes. It is shown that at the intermediate and global levels, MWCNT interconnects can achieve smaller signal delay than that of Cu interconnects, and the improvements become more significant with technology scaling and increasing wire lengths. At 1000- global or 500- intermediate level interconnects, the delay of MWCNT interconnects can reach as low as 15% of Cu interconnect delay. It is also shown that in order for SWCNT bundles to outperform MWCNT interconnects, dense and high metallic-fraction SWCNT bundles are necessary. On the other hand, since MWCNTs are easier to fabricate with less concern about the chirality and density control, they can be attractive for immediate use as horizontal wires in VLSI, including local, intermediate, and global level interconnects.     

互连线间容性交叉耦合对时序分析的影响

集成电路的性能越来越受到互连线间寄生效应的影响,特别是引起互连线跳变模式相关延迟的容性交叉耦合已成为影响线路延迟的一个重要因素。为了提高分层的时序分析方法的准确性,文章引入了局部伪交叉耦合和全局伪交叉耦合的概念,提出了一种利用模块间功能关系识别由于模块间连接产生的全局伪交叉耦合的综合分析方法。实验数据证明了考虑全局伪交叉耦合在提高分层时序验证准确性上的价值。     

Predictions of CMOS compatible on-chip optical interconnect

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node.     

Negative capacitance independent multi-gate FinFETs and their optimisations

In order to reduce the operating voltage of FinFET and increase the flexibility of integrated circuit design, we have proposed a Negative Capacitance Independent Multi-Gate FinFET (NC-IMG-FinFET) with Ferroelectric-Metal-Insulator-Semiconductor-Insulator (FMISI) structure. Both the device and circuit analysis model of NC-IMG-FinFET are addressed, which are used to analyse the performance parameters of the device (the surface potential, internal gate voltage amplification, Sub-threshold Swing (SS), on-current and leakage) and the performance of a circuit (delay, power consumption, power delay product (PDP)). The simulation model of the NC-IMG-FinFET has been constructed by combining BSIM-IMG model with ferroelectric Landau-Khalatnikov model. The optimisations for ferroelectric film thickness of the NC-IMG-FinFETs are carried out in terms of device characteristics and circuit performances. The simulation results are consistent with the analysis results, indicating that the NC-IMG-FinFET has superior performance compared with the baseline device, in terms of smaller leakage, larger on/off current ratio and smaller SS (38.3 mV/dec at room temperature). Compared with the baseline IMG-FinFET circuits, there is large performance improvement for the NC-IMG-FinFET circuits, in terms of the power consumption and PDP.     

Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing

Every new VLSI technology generation has resulted in interconnects increasingly limiting the performance, area, and power dissipation of new processors. Subsequently, it is necessary to devise efficient interconnect design techniques to reduce the impact of VLSI interconnects on overall system design. New optimizations of a wave-pipelined multiplexed (WPM) interconnect routing circuit are described in this paper. These WPM circuits can be used with current interconnect repeater circuits to further reduce interconnect delay, interconnect area, transistor area, and/or power dissipation. For example, new area constrained WPM circuit optimizations illustrate that the interconnect circuit power can be reduced by 26% or the interconnect performance can be improved by 74%. Moreover, in both these cases, because a significant number of repeaters are eliminated, the transistor area can reduce by 41% or 29%, respectively. Finally, the tolerance of WPM circuits to crosstalk noise, power supply noise, clock skew, and manufacturing variations is also presented. This study of tolerance levels defines the conditions under which the WPM circuit will function correctly, and it is shown in this paper for the first time that WPM circuits are robust enough to operate with variability that can be encountered in deep submicrometer technologies.     

High-performance interconnects: an integration overview

The Information Revolution and enabling era of silicon ultralarge-scale integration (ULSI) have spawned an ever-increasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. The increasing influence of interconnect parasitics on crosstalk noise and R(L)C delay as well as electromigration and power dissipation concerns have stimulated the introduction of low-resistivity copper and low-permittivity (k) dielectrics to provide performance and reliability enhancement. Integration of these new materials into integrated circuit fabrication is a formidable task, requiring material, process, design, and packaging innovations. Additionally, entirely new technologies such as RF and optical interconnects may be required to address future global routing needs and sustain performance improvement     

Global (interconnect) warming

This article presents a comprehensive analysis of the thermal effects in advanced high-performance VLSI interconnect systems arising due to self-heating under various circuit conditions, including electrostatic discharge (ESD). Technology (Cu, low-k, etc.) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration (EM) reliability, have been analyzed simultaneously, which have important implications for providing robust and aggressive deep sub-micron (DSM) interconnect design guidelines. The analysis takes into account the effects of increasing interconnect (Cu) resistivity with decreasing line dimensions and the effect of a finite barrier metal thickness. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the global-tier signal lines are investigated. Finally, the reliability implications for minimum-sized vias in optimally buffered signal nets will also be quantified     

High speed interconnect through device optimization for subthreshold FPGA

Field programmable gate array (FPGA) consumes a significant amount of static and dynamic power due to the presence of additional logic for providing more flexibility as compared to application specific integrated circuits (ASICs). The fabrication cost of ASICs is rising exponentially in deep submicron and hence it is important to investigate different techniques for reducing FPGA power consumption so that they can also be employed in place of ASICs in portable energy constrained applications. It is also important to investigate the possibility of extending the use of FPGA even to subthreshold region for ultra low power (ULP) applications. Interconnect resources of an FPGA consumes most of the chip power, area and also determines the overall circuit delay. Subthreshold circuits show orders of magnitude power saving over superthreshold circuits. Improving the performance of subthreshold circuits is a main design challenge at the circuit and device levels to spread their application area. This paper proposes to improve the performance of subthreshold FPGA in terms of delay and switching energy by optimizing and operating interconnect drivers in the near threshold operating region. The possibility of inserting repeaters and the suitability of CNT as an interconnect in the subthreshold region are also explored. The simulation of FPGA interconnect resources using the proposed technique shows 67%, 73.33% and 61.8% increase in speed and 35.72%, 39% and 35.44% reduction in switching energy for Double, Hex and Long interconnect segments, respectively, over the conventional one.     

Interconnect design strategy: structures, repeaters and materialswith strategic system performance analysis (S2PAL) model

In this paper, we propose a novel methodology for scheming an interconnect strategy, such as what interconnect structure should be taken, how repeaters should be inserted, and when new metal or dielectric materials should be adopted. In the methodology, the strategic system performance analysis model is newly developed as a calculation model that predicts LSI operation frequency and chip size with electrical parameters of transistors and interconnects as well as circuit configuration. The analysis with the model indicates that interconnect delay overcomes circuit block cycle time at a specific length; D_c-cross. Here tentatively, interconnects shorter than D_c-cross are called local interconnects, and interconnects longer than that as global ones. The cross-sectional structures for local and global tiers are optimized separately. We also calculate global interconnect pitch and the chip size enlarged by the global interconnect pitch and the inserted repeaters, and then estimate the effectiveness of introducing new materials for interconnects and dielectrics