共查询到16条相似文献,搜索用时 78 毫秒
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基于TSMC 0.18 μm CMOS工艺,采用两级级联的折叠内插结构,设计了一种8位1 GS/s折叠内插A/D转换器。在预放大器阵列输出端引入失调平均网络,优化了预放大器阵列的输入对管尺寸,以补偿边界预放大器的增益衰减。在折叠电路中引入幅度补偿电路,以增加较小的电路功耗为代价改善了电路的带宽限制,提高了增益及输出线性范围。分析了内插平均电阻网路中的高倍内插误差,通过优化内插电阻值,实现了内插输出失调的减小,保证了系统良好的精度特性。仿真结果表明,在采样率为1 GS/s、输入正弦波频率为465.82 MHz的条件下,该8位折叠内插A/D转换器的有效位数能够达到7.31位,功耗为290 mW。 相似文献
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基于0.18 μm CMOS工艺设计并实现了一种8 bit 1.4 GS/s ADC.芯片采用多级级联折叠内插结构降低集成度,片内实现了电阻失调平均和数字辅助失调校准.测试结果表明,ADC在1.4GHz采样率下,有效位达6.4bit,功耗小于480 mW.文章所提的综合校准方法能够有效提高ADC的静态和动态性能,显示出... 相似文献
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A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier (SHA) is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers (opamps) are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW (including I/O drivers) when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads. 相似文献
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折叠插值结构是高速ADC设计中的常用结构。提出了一种新的在折叠插值结构ADC中只对THA进行时间交织的技术,可以在基本不增加芯片功耗和面积的情况下,使ADC的系统速度提高近1倍。位同步技术可以保证粗分和细分通路之间的同步,在位同步的基础上设计了新的编码方式。基于上述技术设计了8 bit 400 MS/s CMOS折叠插值结构ADC,核心电路电流为110mA,面积仅1mm×0.8mm,Nyquist采样频率下SNDR为47.2dB,SFDR为57.1dB。 相似文献
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A 1.4-V 8-bit 300-MS/s folding and interpolating analog-to-digital converter (ADC) is proposed. Fabricated in the 0.13-μm CMOS process and occupying only 0.6-mm2 active area, the ADC is especially suitable for embedded applications. The system is optimized for a low-power purpose. Pipelining sampling switches help to cut down the extra power needed for complete settling. An averaging resistor array is placed between two folding stages for power-saving considerations. The converter achieves 43.4-dB signal-to-noise and distortion ratio and 53.3-dB spurious-free dynamic range at 1-MHz input and 42.1-dB and 49.5-dB for Nyquist input. Measured results show a power dissipation of 34 mW and a figure of merit of 1.14 pJ/convstep at 250-MHz sampling rate at 1.4-V supply. 相似文献
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本文基于90nm CMOS工艺设计了一个单通道 2GSPS, 8-bit 折叠插值模数转换器。本设计采用折叠级联结构,通过在折叠电路间增加级间采样保持器的方法增加量化时间。电路中采用了数字前台辅助校正技术以提高信号的线性度。后仿结果表明,在奈奎斯特采样频率,该ADC的微分非线性DNL<±0.3LSB,积分非线性INL<±0.25LSB,有效位数达到7.338比特。包括焊盘在内的整体芯片面积为880×880 μm2。电路在1.2V 电源电压下功耗为210mW. 相似文献
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This article is presented to describe an area-efficient CMOS folding and interpolating analog-to-digital converter (ADC) for
embedded application, which is fully compatible with standard digital CMOS technology. A modified MOS-transistor-only folding
block contributes to a small chip area. At the input stage, offset averaging reduces the input capacitance and the distributed
track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio (SNDR). An INL/DNL of 0.77 LSB/0.6 LSB was measured. An SNDR figure of 43.7 dB is achieved at 4 MHz input frequencies when operated at full speed of 200 MHz. The chip is realized in a standard digital 0.18 μm CMOS technology and consumes a total power of 181 mW from 3.3 V power supply. The active area is 0.25 mm2. 相似文献
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Ming-Huang Liu Shen-Iuan Liu 《Solid-State Circuits, IEEE Journal of》2001,36(1):122-128
An 8-bit 10-MS/s folding and interpolating analog-to-digital converter (ADC) using the continuous-time auto-zero technique is presented. Compared with the conventional architecture, it can improve the nonlinear errors and enhance the signal-to-noise-and-distortion ratio (SNDR). Both architectures have been fabricated on the same die of a 0.35-μm DPDM CMOS process and measured under the same conditions with a 2.7-V supply voltage and 10-MHz sampling rate. The continuous-time auto-zero architecture shows an ENOB of 7.7 bits while the conventional one shows 5.8 bits 相似文献
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应用Matlab/Simulink工具对折叠内插模数转换器进行了建模,研究了具有8bit分辨率、200MHz采样频率的该模数转换器的芯片设计和实现.系统设计时采用Matlab/Simulink进行行为级建模并分别分析了预放大的增益、折叠电路的带宽以及比较器的失调对动态性能的影响.设计实现的模数转换器实测结果表明,积分非线性误差和微分非线性误差分别小于0.77和0.6LSB,在采样频率为200MHz及输入信号频率为4MHz时,信号与噪声及谐波失真比为43.7dB.电路采用标准0.18μm CMOS数字工艺实现,电源电压为3.3V,功耗181mW,芯核面积0.25mm2. 相似文献