Origin and Control of Material Defects in Silicon VLSI Technologies: An Overview

Very large-scale integrated circuits impose stringent demands on the quality of silicon wafers required for their fabrication. This paper is an overview of the interrelationships among silicon characteristics, processing, circuit performance, and crystal growth. The relationship between circuit performance and defects in the substrate is described, particularly the effects resulting form the transition from LSI to VLSI. The defect-generation process is then discussed in terms of as-grown silicon characteristics and crystal-growth conditions that control them. The interdependence of material parameters, internal gettering procedures used to reduce the effect of defects on device performance, and resistance to the warpage of silicon wafers is reviewed, with special emphasis on the current and future requirements of bipolar, MOS, and CCD processes.     

用于先进 CMOS电路的 150 mm硅外延片外延生长

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mmP/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mmP/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,     

P-Type Versus n-Type Silicon Wafers: Prospects for High-Efficiency Commercial Silicon Solar Cells

Chemical and crystallographic defects are a reality of solar-grade silicon wafers and industrial production processes. Long overlooked, phosphorus as a bulk dopant in silicon wafers is an excellent way to mitigate recombination associated with these defects. This paper details the connection between defect recombination and solar cell terminal characteristics for the specific case of unequal electron and hole lifetimes. It then looks at a detailed case study of the impact of diffusion-induced dislocations on the recombination statistics in n-type and p-type silicon wafers and the terminal characteristics of high-efficiency double-sided buried contact silicon solar cells made on both types of wafers. Several additional short case studies examine the recombination associated with other industrially relevant situations—process-induced dislocations, surface passivation, and unwanted contamination. For the defects studied here, n-type silicon wafers are more tolerant to chemical and crystallographic defects, and as such, they have exceptional potential as a wafer for high-efficiency commercial silicon solar cells.     

Performance limiting micropipe defects in silicon carbide wafers

Reports on the characteristics of a major defect in mass-produced silicon carbide wafers which severely limits the performance of silicon carbide power devices. Micropipe defects originating in 4H- and 6H-SiC substrates were found to cause pre-avalanche reverse-bias point failures in most epitaxially-grown pn junction devices of 1 mm² or larger in area. Until such defects are significantly reduced from their present density (on the order of 100's of micropipes/cm²), silicon carbide power device ratings will be restricted to around several amps or less     

用于先进CMOS电路的150mm硅外延片外延生长

随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mm P/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mm P/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,     

重掺〈100〉硅单晶抛光片条纹状起伏缺陷研究

重掺〈100〉硅单晶片抛光后经微分干涉显微镜观测。抛光片边缘区域存在条纹状起伏缺陷。通过分析条纹状起伏缺陷与重掺硅单品中杂质的分布状况和〈100〉品面本身腐蚀特性的关系，阐述了条纹状起伏缺陷形成的机理。通过工艺试验，对比了不同工艺条件下抛光片表面微观形貌状况，分析了抛光过程中各工艺条件对表面条纹起伏缺陷的影响，采用3步抛光工艺，得到了表面平整和一致性好的抛光片表面，抛光片边缘尤条纹起伏缺陷。     

125mm低阻硅抛光片清洗技术研究

在125 mm(5英寸)硅抛光片清洗过程中,发现硅片边缘容易出现"色斑"现象。对这一现象进行了分析,通过工艺试验,消除了这种现象。     

n‐Type multicrystalline silicon wafers prepared from plasma torch refined upgraded metallurgical feedstock

n‐Type silicon wafers present some definite advantages for the photovoltaic industry, mainly due to the low capture cross sections of minority carriers for most metallic impurities. This peculiarity is beneficial for multicrystalline silicon (mc‐Si) wafers in which the interaction between crystallographic defects and impurities is the main source of recombination centres. Most importantly, this peculiarity could be of a great interest when mc‐Si ingots are produced directly from upgraded and purified metallurgical silicon feedstock. It is of a paramount importance to verify if the advantages of conventional n‐type silicon also characterizes n‐type wafers provided by a direct metallurgical route. It is found, in raw wafers, that minority carrier diffusion lengths are three times higher in n‐type than in p‐type wafers, when the wafers are cut from the same ingot, where the bottom is p‐type and the top is n‐type, due to the difference in the segregation coefficients of doping elements (boron and phosphorus). After different processing steps and gettering treatments the minority carrier diffusion lengths are always neatly larger in n‐type than in p‐type wafers The results confirm the interest for n‐type silicon. Copyright © 2009 John Wiley & Sons, Ltd.     

背面刻蚀对单晶硅太阳电池性能影响的研究

为了减少太阳电池载流子的背面复合,采用离子束对沉积完SiNx减反射膜后的单面扩散和双面扩散的单晶硅片背面进行刻蚀,研究了刻蚀时间对太阳电池性能的影响.采用标准的太阳电池单片测试仪测试电池性能.发现背面经离子束刻蚀后,单面扩散和双面扩散电池片的并联电阻、开路电压、填充因子和转换效率都有所提高,而串联电阻和短路电流的变化则...     

热处理气氛对直拉硅单晶中体缺陷的影响

研究了五种不同的热处理气氛对直拉硅中氧沉淀及其诱生缺陷的影响.实验结果表明,经过低-高退火处理的硅片继续在五种不同的气氛中高温退火,氧沉淀会部分溶解,其溶解量与热处理气氛没有明显的关系,但不同气氛中处理的硅片中体缺陷(BMDs)的分布不同.并对此现象的机理进行了讨论,认为热处理气氛影响了硅片中点缺陷的分布从而影响到BMDs的分布.此研究对集成电路生产中内吸杂工艺的保护气氛的选择有指导意义.     

In-process voltage stressing to increase reliability of MOS integrated circuits

Time-dependent dielectric breakdown of gate oxides is one of the principal failure mechanisms of MOS integrated circuits. Voltage stressing of completed devices, which has been used to screen oxide defects and to thereby increase product reliability, is less effective with scaled high-density MOS integrated circuits because of limitations in the voltage which can be applied. Inprocess voltage stressing of silicon wafers, prior to completion of wafer processing, offers a feasible technique for achieving an effective voltage screen. Several possible techniques for inprocess voltage stressing are described, and the advantages and limitations of these are outlined. Data are presented showing typical fast-ramp dielectric breakdown distributions for MOS transistor arrays with an oxide thickness of 35 and 50 nm. Time-dependent dielectric breakdown distribution data on devices from the same wafers indicate that with all MOS transistors of an integrated circuit connected in parallel, as in one type of inprocess voltage stressing, defective oxide sites can be screened in periods of time ranging from a few seconds to hours. Inprocess voltage stressing, by decreasing susceptibility of completed devices to time-dependent dielectric breakdown, can substantially increase MOS integrated circuit reliability.     

Effect of interfacial and bulk organic contamination on the quality of thin silicon oxide

The effect of organic contamination of silicon (HF-last cleaned) and silicon dioxide (as-received) wafer surfaces on the quality of gate oxide was studied. Controlled contamination by model organics as well as cleanroom contamination conditions were investigated. Wafers were oxidized under oxidizing or inert ramp-up ambient to grow ultrathin thermal oxides (30 /spl Aring/). Surface and electrical characterization of the oxides was done by Auger sputter profiling, tunneling atomic force microscopy (TAFM) and gate oxide integrity (GOI) measurements. For oxides grown in an inert ambient during ramp-up, HF-last cleaned wafers had a large number of carbon-based defects as compared to as-received wafers. Oxygen in the ramp-up ambient oxidized and volatilized organics resulting in good quality thin gate oxides for HF-last cleaned wafers. However, for as-received wafers, the defect density was increased in an oxidizing ramp-up ambient. A probable mechanism for degradation of the gate oxide quality on HF-last wafers in an inert ramp-up ambient is investigated.     

注氢硅片中片状缺陷的结构特征及其深度分布的高分辨电镜研究

离子注入氢是改善硅材料性能,特别是实现硅片薄层剥离的重要途径。本文利用高分辨率电镜对注氢硅片的横截面样品进行了研究,观察了片状缺陷的结构特征,分析了片状缺陷尺寸和间距在纵深方向的变化。实验发现,沿着平行于正表面的(111)片状缺陷是注氢硅中的重要缺陷。片状缺陷的实质是四层晶面的应变,造成晶格膨胀约O．084nm。实验还发现片状缺陷的尺寸和间距随深度变化,在损伤带顶部和中间小,而在损伤带底部附近明显增大。     

Fabrication of thick silicon nitride blocks for integration of RF devices

A fabrication process for the creation of thick (tens of micrometres) silicon nitride blocks embedded in silicon wafers has been developed. This new technology allows the use of silicon nitride as dielectric material for radio frequency (RF) circuits on standard CMOS-grade silicon wafers. Measurement results show that a performance similar to that of dedicated glass substrates can be reached     

多晶硅太阳电池转换效率和晶体缺陷相关性

多晶硅太阳能电池组件以它显著的综合成本优势被广泛应用.铸锭多晶硅的晶体缺陷特征与其电池转换效率有着强烈的关联性.晶体的底部和顶部缺陷密度高,对应的电池转换效率低(14.5~15.5%);晶体中部因为较低的缺陷密度,对应着较高的电池转换效率(16.5~17.5%).不同种类的晶体缺陷对电池效率的影响又不尽相同,比如位错等顽固性缺陷会保留至终,而间隙态金属杂质等可去除的缺陷则会在电池制备过程中得以消除.     

CZ硅单晶中旋涡缺陷对低频大功率管制造的影响

CZ硅晶片中的旋涡缺陷在器件制造的热循环过程中 ,会转化成体内杆状层错 ,且易集结在发射结对应下方的基区和集电结附近 ,从而导致 EB结和 CB结的软击穿现象进行了研究 ,并采取了适当措施 ,以消除和控制旋涡缺陷的产生     

An etchant for delineation of flow pattern defects in heavily doped p-type silicon wafers

Secco etchant is conventionally used for delineation of flow pattern defects (FPDs) in lightly-doped Czochralski (Cz) silicon wafers. However, the FPDs in heavily doped p-type silicon wafers cannot be well delineated by Secco etchant. Herein, an etchant based on the CrO₃HFH₂O system, with an optimized volume ratio of V(CrO₃):V(HF)=2:3, where the concentration of CrO₃ is 0.25–0.35 M, has been developed for delineation of FPDs with well-defined morphologies for the heavily boron (B)-doped p-type silicon wafers.     

Wafer temperature measurement in a rapid thermal processor with modulated lamp power

Pyrometry methods utilizing modulated lamp power (“ripple”) were used to improve wafer temperature measurement and control in rapid thermal processing (RTP) for silicon integrated circuit production. Data from a manufacturing line where ripple pyrometers have been tested show significantly reduced wafer to wafer and lot to lot variations in final test electrical measurements and increased yields of good chips per wafer. The pyrometers, an outgrowth of Accufiber’s ripple technique, are used to compensate for ordinary production variations in the emissivities of the backsides of wafers, which face the pyrometers. Power to the heating lamps is modulated with oscillatory functions of time at either the power line frequency or under software control. Fluctuating and quasi-steady components in detected radiation are analyzed to suppress background reflections from the lamps and to correct for effective wafer emissivity. Sheet resistances of annealed wafers with high dose shallow As implants were used to infer temperature measurement capability over a range in backside emissivity. Emissivities are varied when depositing or growing one or more layers of silicon dioxide, silicon nitride, or polycrystalline silicon on the backsides of the wafers.     

面向对注氢硅片中微结构的影响

把不同面向的注氢硅片制成横截面样品,在高分辨率透射电子显微镜下进行观察,发现衬底面向对其中的微结构有明显的影响.首先表现为衬底中主要出现平行于正表面的氢致片状缺陷,即(10 0 )衬底中,主要出现平行于正表面的{ 10 0 }片状缺陷,而(111)衬底中出现的主要是平行于正表面的{ 111}片状缺陷.其原因是注入引起垂直正表面的张应变.另外,面向的影响还表现为,(10 0 )衬底中出现的{ 113}缺陷在(111)衬底中不出现.在(111)衬底中出现的晶格紊乱团和空洞在(10 0 )衬底中不出现.从而推测,{ 111}片状缺陷的形成不发射自间隙原子,而(10 0 )片状缺陷的形成将发射自