Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors

The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant.     

SOI反偏肖特基势垒动态阈值MOS特性

将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较.     

SOI反偏肖特基势垒动态阈值MOS特性

将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较.     

A dynamic threshold voltage MOSFET (DTMOS) for very low voltageoperation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V_dd. On the other hand, V_t is high at V_gs =0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V_dd=0.5 V     

High voltage applications and NBTI effects of DT-pMOSFETS with reverse Schottky substrate contacts

In this study, the characteristics of DT-pMOSFETs are discussed using the reverse Schottky substrate contacts. With this diode, the DTMOS can be operated at high voltage and temperature. In addition, it exhibited an improved driving current, DIBL, transconductance, and subthreshold slope. The driving current for DTMOS was 20% larger, and was 12 mV improved for DIBL under DTMOS operation. Furthermore, the NBTI effects of DTMOS were also reported for the first time. This is because DTMOS could operate just below 0.7 V of V_G due to the junction turn-on behavior. It is interesting to note that the shift of the ΔV_TH of pMOSFETs under NBTI measurement was significantly alleviated in the DT operating mode, about 30 mV improved after 10,000 s stressing, due to the alleviated electrical field across the gate oxide which was due to the substrate bias and the threshold voltage adjustment under DTMOS operation.     

工作在动态阈值MOS的特性研究

通过将衬底和栅极连接在一起实现了MOSFET的动态阈值,DTMOS与标准的MOSFET相比具有更高的迁移率,在栅极电压升高时DTMOS阈值电压会随之降低,从而获得了比标准的MOSFET大的电流驱动能力。DTMOS是实现低电压、低功耗的一种有效手段。     

High performance 0.1 μm dynamic threshold MOSFET using indiumchannel implantation

In this letter, we demonstrate a high-performance 0.1 μm dynamic threshold voltage MOSFET (DTMOS) for ultra-low-voltage (i.e., <0.7 V) operations. Devices are realized by using super-steep-retrograde indium-channel profile. The steep indium-implanted-channel DTMOS can achieve a large body-effect-factor and a low V_th simultaneously, which results in an excellent performance for the indium-implanted DTMOS     

high-performance and high-reliability 80-nm gate-length DTMOS with indium super steep retrograde channel

In this paper, we demonstrate for the first time a high-performance and high-reliability 80-nm gate-length dynamic threshold voltage MOSFET (DTMOS) using indium super steep retrograde channel implantation. Due to the steep indium super steep retrograde (In SSR) dopant profile in the channel depletion region, the novel In-SSR DTMOS features a low V/sub th/ in the off-state suitable for low-voltage operation and a large body effect to fully exploit the DTMOS advantage simultaneously, which is not possible with conventional DTMOS. As a result, excellent 80-nm gate length transistor characteristics with drive current as high as 348 /spl mu/A//spl mu/m (off-state current 40 nA//spl mu/m), a record-high Gm=1022 mS/mm, and a subthreshold slope of 74 mV/dec, are achieved at 0.7 V operation. Moreover, the reduced body effects that have seriously undermined conventional DTMOS operation in narrow-width devices are alleviated in the In-SSR DTMOS, due to reduced indium dopant segregation. Finally, it was found for the first time that hot-carrier reliability is also improved in DTMOS-mode operation, especially for In-SSR DTMOS.     

SOI 动态阈值MOS 研究进展

随着器件尺寸的不断缩小,传统MOS器件遇到工作电压和阈值电压难以等比例缩小的难题,以至于降低电路性能,而工作在低压低功耗领域的SOI DTMOS可以有效地解决这个问题。本文介绍了四种类型的SOI DTMOS器件．其中着重论述了栅体直接连接DTMOS、双栅DTMOS和栅体肖特基接触DTMOS的工作原理和性能．具体分析了优化器件性能的五种方案,探讨了SOI DTMOS存在的优势和不足。最后指出,具有出色性能的SOI DTMOS必将在未来的移动通讯和SOC等低压低功耗电路中占有一席之地。     

Dynamic threshold pass-transistor logic for improved delay at lowerpower supply voltages

We have investigated circuit options to surpass the 1 V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on- and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed     

A novel high performance SiGe channel heterostructure dynamicthreshold pMOSFET (HDTMOS)

In this letter, we propose a novel SiGe channel heterostructure dynamic threshold metal oxide semiconductor (DTMOS) and demonstrate its superiority over conventional Si-DTMOS. The introduction of a SiGe layer for the channel is very effective for reducing the threshold voltage in spite of keeping impurity doping level at the body region. Therefore, a low threshold voltage and a large body effect factor can be achieved simultaneously. The SiGe HDTMOS with highly doped body exhibits two times higher transconductance, 1.4 times higher saturation current, and better short channel immunity than that of the control Si-DTMOS with lightly doped body of which threshold voltage is nearly the same     

On the power dissipation in dynamic threshold silicon-on-insulatorCMOS inverter

A power dissipation model for SOI dynamic threshold voltage MOSFET (DTMOS) inverter is proposed for the first time. The model includes static, switching and short-circuit power dissipation. For the switching power dissipation, we have considered both the load capacitance and the device parasitic capacitances. Modeling of the short-circuit power dissipation is based on long-channel DC model for simplicity. The comparison of power dissipation and gate delay between conventional SOI CMOS and SOI DTMOS inverters concludes that DTMOS inverter is better in performance while consumes more power, and its advantage over floating-body SOI inverter diminishes as the power supply approaches 0.7 V     

Impacts of gate structure on dynamic threshold SOI nMOSFETs

The effects of different substrate-contact structures (T-gate and H-gate) dynamic threshold voltage silicon-on-insulator (SOI) nMOSFETs (DTMOS) have been investigated. It is found that H-gate structure devices have higher driving current than T-gate under DTMOS-mode operation. This is because H-gate SOI devices have larger body effect factor (/spl gamma/), inducing a lager reduction of threshold voltage. Besides, it is found that drain-induced-barrier-lowering (DIBL) is dramatically reduced for both T-gate and H-gate structure devices when devices are operated under DTMOS-mode.     

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V_t) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V_t is high at V_gs=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V_dd=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS)     

A monolithic based NIRS front-end wireless sensor

This paper concerns a novel analog front-end of a wireless brain oxymeter smart sensoring instrument based on near-infrared spectroreflectometry (NIRS). The NIRS sensor makes use of dynamic threshold transistors (DTMOS) for low voltage (1 V), low power and low noise enhancement. The design is composed of a transimpedance amplifier (TIA) and an operational transconductance amplifier (OTA). The OTA differential input pairs use DTMOS devices for input common mode range enhancement. The OTA was fabricated in a standard 0.18 μm CMOS process technology. Measurements under a 5 pF capacitive load for the OTA gave a DC open loop gain of 67 dB, unity frequency gain bandwidth of 400 kHz, input and output swings of 0.58 and 0.7 V, a power consumption of 18 μW, and an input referred noise of 134 nV/√Hz at 1 kHz without any extra noise reduction techniques. The achieved features of the proposed oxymeter front-end will allow ultra low-light level measurements, high resolution and good temperature stability.     

1-V DTMOS-Based Class-AB Operational Amplifier: Implementation and Experimental Results

In this paper, we describe a novel low-voltage class-AB operational amplifier (opamp) based on dynamic threshold voltage MOS transistors (DTMOS). A DTMOS transistor is a device whose gate is tied to its bulk. DTMOS transistor pseudo-pMOS differential input pairs are used for input common-mode range enhancement, followed by a single ended class-AB output. Two versions of the proposed opamp (opamp-A and opamp-B) were fabricated in a standard 0.18-mum CMOS process technology. Measurements under 5 pF and 10 kOmega load conditions gave, for opamp-A, a DC open-loop gain of 50.1 dB, and a unity gain bandwidth (GBW) of 26.2 MHz. A common-mode rejection ratio (CMRR) of 78 dB, and input and output swings of 0.7 V and 0.9 V, respectively, were achieved. Opamp-B has been optimized for biomedical applications, and is implemented to build the analog front-end part of a near-infrared spectroreflectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. A DC open-loop gain of 53 dB, a GBW of 1.3 MHz, and input and output swings of 0.6 V and 0.8 V, respectively, were measured. Opamp-A consumes 550 muW with an input referred noise of 160 nV/radicHz at 1 kHz. Opamp-B consumes only 40 muW and exhibits a lower input referred noise of 107 nV/radicHz at 1 kHz     

High drive-current electrically induced body dynamic threshold SOIMOSFET (EIB-DTMOS) with large body effect and low threshold voltage

A novel electrically induced body dynamic threshold metal oxide semiconductor (EIB-DTMOS) is proposed where the body is electrically induced by substrate bias and its high performance is demonstrated by experiments and simulations. EIB-DTMOS achieves a large body effect and a low V_th at the same time. The upper limit of the supply voltage of the EIB-DTMOS is higher than that of a conventional DTMOS, because the forward biased p-n junction leakage current of the EIB-DTMOS is lower. Among several DTMOSs, the accumulation mode EIB-DTMOS shows the highest drive-current at fixed off-current due to a large V_th Shift (or large back gate capacitance) and a suppressed short channel effect     

High-speed and energy-efficient subthreshold level converter for wider voltage conversion

Analog Integrated Circuits and Signal Processing - In this paper, a high speed and energy-efficient dynamic threshold MOSFET (DTMOS) based hybrid level converter (DTHLC) is proposed with wide...     

A novel dynamic threshold Voltage MOSFET (DTMOS) using heterostructure channel of Si/sub 1-y/C/sub y/ interlayer

We have demonstrated the fabrication of dynamic threshold voltage MOSFET (DTMOS) using the Si/sub 1-y/C/sub y/(y=0.005) incorporation interlayer channel. Compare to conventional Si-DTMOS, the introduction of the Si/sub 1-y/C/sub y/ interlayer for this device is realized by super-steep-retrograde (SSR) channel profiles due to the retardation of boron diffusion. A low surface channel impurity with heavily doped substrate can be achieved simultaneously. This novel Si/sub 1-y/C/sub y/ channel heterostructure MOSFET exhibits higher transconductance and turn on current.     

Ultra-Low voltage-power DTMOS based full-wave rectifier

In this paper, dynamic threshold MOS (DTMOS) transistor based full-wave rectifier with ultra-low power consumption is presented. The proposed circuit composed of only four NMOS and seven DTMOS transistors when many rectifier circuits consist of passive circuit components such as diodes, resistors and active circuit elements. The layout occupies an active area of 24.6 µm × 65.01 µm and post-layout simulation results performed using Cadence Environment with 0.18 µm TSMC CMOS technology parameters. The rectifier circuit with ±0.2 V DC supply voltages can be operated up to approximately 500 MHz and consumes only 2.83 nW thanks to the DTMOS transistors.