SΛMSUNG三星电子Mobile WiMAX的关键技术

1999年,IEEE成立了802.16工作组专门从事宽带无线接入标准的研究,到目前为止相继发布了IEEE 802.16、IEEE802.16a、IEEE 802.16d、IEEE 802.16e等一系列的技术标准.IEEE 802.16d对IEEE 802.16和IEEE 802.16a进行了整合和修订,是一项固定宽带无线接入技术的标准,主要用于固定、游牧等场景.而IEEE 802.16e是基于IEEE 802.16d标准的,能够后向兼容IEEE 802.16d的功能.该标准定义了可以同时支持固定和移动宽带无线接入的系统,工作在2～6 GHz适于移动性的频段,可支持车速移动(通常认为是120 km/h)的用户,同时固定无线接入用户能力并不因此受到影响.这种既能够提供高速数据业务又使用户具有移动性的技术被业界视为目前唯一能与3G竞争的下一代宽带无线技术.在物理层,802.16e可以支持2048点、1024点、512点的OFDMA,以适应不同的信道带宽.同时为了实现移动性,802.16e规定出了切换以及终端节电模式等技术.下文将对切换和终端节电模式这两种技术分别进行介绍.     

基于IEEE802.16e的头压缩的设计与实现

介绍了IEEE802.16e协议中MAC CS子层的头压缩机制,并结合MAC CS子层的特点,提出了一种IEEE 802.16e协议栈开发中MAC CS子层头压缩模块的实现方案.通过对已有头压缩算法的研究分析,并结合IEEE802.16e协议的特性提出了一种适合宽带无线通信系统的头压缩算法.     

基于IEEE802.16e的头压缩的设计与实现

介绍了IEEE802.16e协议中MACCS子层的头压缩机制,并结合MACCS子层的特点,提出了一种IEEE802.16e协议栈开发中MACCS子层头压缩模块的实现方案。通过对已有头压缩算法的研究分析,并结合IEEE802.16e协议的特性提出了一种适合宽带无线通信系统的头压缩算法。     

基于IEEE 802.16a的OFDM基带调制系统的FPGA设计

本文研究了基于IEEE802.16a的OFDM基带调制系统的实时实现,提出了一种切实可行的IEEE802.16a的OFDM调制方式的FPGA实现方法与结构,并介绍了IFFT运算、QPSK映射和插入循环前缀的具体电路。最后给出了硬件性能分析。     

基于IEEE802.16e移动宽带无线接入网的切换过程分析与实现

随着WiMAX组织的发展壮大加快了IEEE802.16标准的发展,移动WiMAX ——IEEE802.16e标准的提出更加引人注目.该标准对IEEE802.16标准进行了补充和拓展,定义了一个结合固定和移动宽带无线接入的系统,填补了高速无线局域网和高移动性蜂窝系统之间的空白.对IEEE802.16e标准中规定的移动宽带无线接入系统的切换过程进行了分析,并提出了该过程的软件实现方案.     

IEEE 802.16e小区搜索算法的VLSI实现

小区搜索是IEEE 802.16e系统的关键技术之一.由此提出了一种低复杂度的快速联合小区搜索和整数倍频偏估计算法的VLSI结构.该结构采用差分估计方法,有效地解决了频率选择性衰落信道对检测性能的影响.详细描述了该结构的各组成单元和设计方法,并在Altera公司的EP2S130器件上进行了仿真综合验证.验证结果表明,该模块最高工作频率为103.7MHz,能够正常应用于IEEE 802.16e接收机或其他类似通信系统.     

一种适用于OFDMA系统的时频结合Ranging检测算法

基于Ranging码的频域相关性,针对IEEE802.16e标准的OFDMA系统,提出了一种时频结合的初始Ranging检测算法,通过调整两门限的设置,在保证较高的检测性能基础上,可以有效地检测接收信号中有无Ranging请求、Ranging码编号、时偏等信息并且减少了Ranging检测的计算量。     

WiMAX系统中的CTC编译码算法实现

介绍了标准CTC编码器的结构和循环状态规则,分析了CTC译码器的结构和各种译码算法,并基于IEEE 802.16e OFDMA系统分别在加性高斯白噪声信道和多径衰落信道模型下,对不同信道模型进行了仿真验证。     

IEEE 802.16d/e宽带无线接入网络中的切换机制的研究

作为新一代的宽带无线接入技术IEEE 802.16d/e以自身固有的优势正越来越受到关注。相比于固定接入的WiMAX,移动版WiMAX,即IEEE 802.16e具有更好的市场前景,同时也面临更多的挑战。文章在分析和研究了IEEE 802.16e标准中定义的切换模式的基础上,总结了现有的IEEE 802.16e切换机制的研究现状,并建议为IEEE 802.16e的移动宽带接入网络提出一种具有QoS保证的支持无缝移动的移动性管理架构,从而实现了IEEE 802.16e的MS和网络中的通信对端之间实现具有端到端QoS保证的平滑服务。     

用可编程DSP实现IEEE 802.16 PHY信号处理

IEEE802.16标准的各个版本都规定了PHY(物理层)的多种选项,包括调制、信道编码和天线分集技术。物理信道带宽可以在1.25MHz～20MHz之间变化。上述所有选项都会影响基站的性能和信号处理复杂度。许多客户希望提供一种可以从802.16-2004升级到802.16e标准的方法。上述需求以及对支持互通性(成功部署新标准的关键)的需求,都要求基站的PHY采用可编程的信号处理器件。图1为802.16基站基带信号链路基本框图。因为802.16-2004和802.16e标准都是在OFDM基础上建立的,所以FFT和IFFT起了很大的作用。这两种变换都用于频域副载波(携带编码的数…     

Design of an FFT/IFFT Processor for MIMO OFDM Systems

In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to efficiently deal with multiple data sequences. The proposed processor not only supports the operation of FFT/IFFT in 128 points and 64 points but can also provide different throughput rates for 1-4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13-mum single-poly and eight-metal CMOS process. The core area is 660times2142 mum² , including an FFT/IFFT processor and a test module. At the operation clock rate of 40 MHz, our proposed processor can calculate 128-point FFT with four independent data sequences within 3.2 mus meeting IEEE 802.11n standard requirements     

基于802.11a的FFT/IFFT处理器设计

设计了一种应用于802.11a的64点FFT/IFFT处理器.采用单蝶形4路并行结构,提出了4路并行无冲突地址产生方法,有效地提高了吞吐率,完成64点FFT/IFFT运算只需63个时钟周期.提出的RAM双乒乓结构实现了对输入和输出均为连续数据流的缓存处理.不仅能实现64点FFT和IFFT,而且位宽可以根据系统任意配置.为了提高数据运算的精度,设计采用了块浮点算法,实现了精度与资源的折中.16位位宽时,在HJTC 0.18μmCMOS工艺下综合,内核面积为:0.626 7 mm2,芯片面积为:1.35 mm×1.27 mm,最高工作频率可达300 MHz,功耗为126.17 mW.     

A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM

In this paper, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in an OFDM-based IEEE 802.11a wireless LAN baseband processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25-/spl mu/m BiCMOS technology. The core area of this chip is 6.8 mm/sup 2/. The average dynamic power consumption is 41 mW at 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption.     

An Area Efficient FFT/IFFT Processor for MIMO-OFDM WLAN 802.11n

A pipelined Fast Fourier Transform and its inverse (FFT/IFFT) processor, which utilizes hardware resources efficiently, is proposed for MIMO-OFDM WLAN 802.11n. Compared with a conventional MIMO-OFDM implementation, (in which as many FFT/IFFT processors as the number of transmit/receive antennas is used), the proposed architecture (using hardware sharing among multiple data sequences) reduces hardware complexity without sacrificing system throughput. Further, the proposed architecture can support 1–4 input data sequences with sequence lengths of 64 or 128, as needed. The FFT/IFFT processor is synthesized using TSMC 0.18 um CMOS technology and saves 25% area compared to a conventional implementation approach using radix-2³ algorithm. The proposed FFT/IFFT processor can be configured to improve power efficiency according to the number of input data sequences and the sequence length. The processor consumes 38 mW at 75 MHz for one input sequence with 64-point length; it consumes 87 mW at 75 MHz for four input sequences with length 128-point and can be efficiently used for IEEE 802.11n WLAN standard.

基于DSP的正交频分复用的实现

在理论上推导了采用快速傅里叶逆变换/傅里叶变换(IFFT/FFT)实现正交频分复用(OFDM)调制解调的可行性,分析了采用IFFT/FFT实现OFDM调制解调比传统方法更具优势;然后在数字信号处理器(DSP)硬件平台上对采用IFFT/FFT实现OFDM调制解调进行了验证。实验结果表明:采用IFFT/FFT不仅能正确实现OFDM信号的调制解调,而且还大大简化了OFDM系统结构,降低了系统实现难度,节约了成本。     

A multi‐mode IFFT/FFT processor for IEEE 802.11ac: design and implementation

In this paper, we present 64/128/256/512‐point inverse fast Fourier transform (IFFT)/FFT processor for single‐user and multi‐user multiple‐input multiple‐output orthogonal frequency‐division multiplexing based IEEE 802.11ac wireless local area network transceiver. The multi‐mode processor is developed by an eight‐parallel mixed‐radix architecture to efficiently produce full reconfigurability for all multi‐user combinations. The proposed design not only supports the operation of IFFT/FFT for 1–8 different data streams operated by different users in case of downlink transmission, but also, it provides different throughput rates to meet IEEE 802.11ac requirements at the minimum possible clock frequency. Moreover, less power is needed in our design compared with traditional software approach. The design is carefully optimized to operate by the minimum wordlengths that fulfill the performance and complexity specifications. The processor is designed and implemented on Xilinx Vertix‐5 field programmable gate array technology. Although the maximum clock frequency is 377.84 MHz, the processor is clocked by the operating sampling rate to further reduce the power consumption. At the operation clock rate of 160 MHz, our proposed processor can calculate 512‐point FFT with up to eight independent data sequences within 3.2~μs meeting IEEE 802.11ac standard requirements. Copyright © 2015 John Wiley & Sons, Ltd.     

用于MB-OFDM UWB系统的FFT/IFFT处理器的设计与实现

设计了一种应用于超宽带(UWB)无线通信系统中的FFT/IFFT处理器。该处理器采用基24算法进行FFT运算,利用8路并入并出的流水线结构实现该算法,提高了处理器的数据吞吐率,降低了芯片功耗。提出了一种新颖的数据处理方式,在保证信噪比的情况下节约了逻辑资源。在乘法器的设计环节,针对UWB系统的具体特点,在结构上对乘法器进行了改进和优化,提高了乘法器的性能。最后,设计的FFT/IFFT处理器采用TSMC 0.18μm CMOS标准工艺库综合,芯片的内核面积为0.762mm2(不含测试电路)。在1.8V,25℃条件下,最大工作时钟317.199MHz,在UWB典型的工作频率下,内核功耗为33.5304mW。     

Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN

An optimal implementation of 128-Pt FFT/IFFT for low power IEEE 802.15.3a WPAN using pseudo-parallel datapath structure is presented, where the 128-Pt FFT is devolved into 8-Pt and 16-Pt FFTs and then once again by devolving the 16-Pt FFT into 4×4 and 2×8. We analyze 128-Pt FFT/IFFT architecture for various pseudo-parallel 8-Pt and 16-Pt FFTs and an optimum datapath architecture is explored. It is suggested that there exists an optimum degree of parallelism for the given algorithm. The analysis demonstrated that with a modest increase in area one can achieve significant reduction in power. The proposed architectures complete one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 128-point FFT computation in less than 312.5 ns and thereby meet the standard specification. The relative merits and demerits of these architectures have been analyzed from the algorithm as well as implementation point of view. Detailed power analysis of each of the architectures with a different number of data paths at block level is described. We found that from power perspective the architecture with eight datapaths is optimum. The core power consumption with optimum case is 60.6 MW which is only less than half of the latest reported 128-point FFT design in 0.18u technology. Furthermore, a Single Event Upset (SEU) tolerant scheme for registers is also explored. The SEU tolerant scheme will not affect the performance, however, there is an increase power consumption of about 42 percent. Apart from the low power consumption, the advantages of the proposed architectures include reduced hardware complexity, regular data flow and simple counter based control.     

数模同播音频广播系统中OFDM调制解调器的设计

设计了一种基于IFFT/FFT的高效OFDM调制解调器,实现数模同播音频广播系统中数字音频信号的OFDM调制解调,包括发射机中用于形成OFDM符号的时域与频域交织模块、OFDM调制模块和接收机中OFDM解调模块、时域与频域解交织模块。通过对IFFT/FFT算法的改进,该OFDM调制解调器中数据的输入顺序和输出顺序相同,不需要进行顺序输人逆序输出,并且可以把现有基2的幂次方的FFT变换扩展到任意点,实现适用于任意点的IFT/FFT,简化了IFFT/FFT模块本身和交织／解交织的资源消耗,巧妙地节省了系统所需的资源。