InSb(111)A面腐蚀坑成因分析

采用光学显微镜和光学轮廓仪分析了InSb晶片(111)A面经特定腐蚀剂腐蚀后出现的两种特征腐蚀坑,并通过多次腐蚀试验观察了这两种腐蚀坑形貌的演变。从理论上对腐蚀坑形貌的成因进行了分析,结果显示1类特征腐蚀坑的成因是由于晶片固有的位错缺陷,2类特征腐蚀坑可能是由于晶片表面存在一定深度的损伤层引起的。     

Effect of off-orientation of seed crystal on silicon carbide (SiC) single-crystal growth on the (11 $$\bar 2$$ 0) surface0) surface

The effect of off-orientation growth has been investigated in terms of stacking fault formation during physical vapor transport (PVT) growth of silicon carbide (SiC) single crystals on the (11 0) seed crystal surface. Occurrence of stacking fault formation is largely dependent on the direction of off-orientation, and basal plane stacking fault density is significantly reduced by growing the crystals on a (11 0) seed crystal off-oriented toward 〈0001〉. The density of the basal plane stacking faults rapidly decreases from 100–150 cm⁻¹ to ∼10 cm⁻¹ as the degree of off-orientation is increased from 0 to 10 deg. The results are interpreted in the framework of microscopic facet formation during PVT growth, and the introduction of off-orientation of seed crystal is assumed to prevent (01 0) and (10 0) microfacet formation on the (11 0) growing surface through modification of the surface growth kinetics and to suppress the stacking fault formation. An erratum to this article is available at .     

非、单晶硅太阳能电池组件比功率发电量对比研究

通过比较单晶硅与非晶硅比功率发电量,分析两者在太阳能发电功效上的具体差异.     

Crystallographic defects in thermally oxidized wafer bonded silicon on insulator (SOI) substrates

The crystalline quality of wafer bonded (WB) silicon on insulator (SOI) structures thermal treated in dry oxygen ambients has been investigated by means of transmission electron microscopy and defect etching. The main crystallographic defects present in the SOI layers are dislocations, amorphous precipitates, and oxidation induced stacking faults (OISF). The evolution of the OISFs with time and temperature has also been investigated. The main feature observed is that the OISF in WB SOI structures undergo a retrogrowth process at temperatures around T = 1195°C for times of t = 2h. This result is very similar to that recently reported for oxygen implanted SOI (SIMOX) but considerably different from that observed in bulk silicon. The experimental data fits nicely a model recently proposed for the retrogrowth of OISF in thin SOI layers. This model considers that the self-interstitial supersaturation is considerably reduced compared to bulk silicon due to the relative fast point defect recombination inside the top silicon layer.     

In situ nanoscale refinement by highly controllable etching of the(111) silicon crystal plane and its influence on the enhanced electrical property of a silicon nanowire

Nanoscale refinement on a(100) oriented silicon-on-insulator(SOI) wafer was introduced by using tetra-methyl-ammonium hydroxide(TMAH,25 wt%) anisotropic silicon etchant,with temperature kept at 50℃to achieve precise etching of the(111) crystal plane.Specifically for a silicon nanowire(SiNW) with oxide sidewall protection,the in situ TMAH process enabled effective size reduction in both lateral(2.3 nm/min) and vertical (1.7 nm/min) dimensions.A sub-50 nm SiNW with a length of microns with uniform triangular cross-section was achieved accordingly,yielding enhanced field effect transistor(FET) characteristics in comparison with its 100 nm-wide pre-refining counterpart,which demonstrated the feasibility of this highly controllable refinement process. Detailed examination revealed that the high surface quality ofthe(111) plane,as well as the bulk depletion property should be the causes of this electrical enhancement,which implies the great potential of the as-made cost-effective SiNW FET device in many fields.     

The influence of silicon heat treatments on the minority carrier generation and the dielectric breakdown in MOS structures

The minority carrier lifetime of Si and the dielectric breakdown of SiO₂ on Si has been investigated as a function of various high temperature treatments preceding the formation of the SiO₂ layer. Annealing wafers in H₂ or certain H₂ -containing ambients prior to oxidation lea to a dramatic decrease in the number of breakdown defects found in capacitors. The higher the temperature the more effective is the defect removal. Using this process the defect density could be reproducibly controlled at ≤10 defects/cm , and in some cases wafers with no defects were found. The defects appear to be related to some airborn contamination and can be increased by exposure to air and to certain aqueous cleaning steps. By “soaking≓ the Si wafers in an equilibrium gas mixture containing SiH₄ as well as HCl, it was possible to prevent etching of the Si but yet expose the wafer to approximately 4% HC1 for longer times and at higher temperatures, 12 75‡C, than is possible with the well known HCl-oxidation process. It was found that this treatment will remove Au, Fe, and Cu from intentionally contaminated wafers but at rates much slower than would be expected from bulk-diffusion, rate-limited transport. Soaking at 1275‡C led to minority carrier lifetimes comparable but not significantly better than for HCl-oxidized wafers.     

基于硅(111)晶面腐蚀的可控在线细化工艺及其对硅纳米线电学性能的改善

Nanoscale refinement on a (100) oriented silicon-on-insulator (SOI) wafer was introduced by using tetra-methyl-ammonium hydroxide (TMAH, 25 wt%) anisotropic silicon etchant, with temperature kept at 50 ℃ to achieve precise etching of the (111) crystal plane. Specifically for a silicon nanowire (SiNW) with oxide sidewall protection, the in situ TMAH process enabled effective size reduction in both lateral (2.3 nm/min) and vertical (1.7 nm/min) dimensions. A sub-50 nm SiNW with a length of microns with uniform triangular cross-section was achieved accordingly, yielding enhanced field effect transistor (FET) characteristics in comparison with its 100 nm-wide pre-refining counterpart, which demonstrated the feasibility of this highly controllable refinement process. Detailed examination revealed that the high surface quality of the (111) plane, as well as the bulk depletion property should be the causes of this electrical enhancement, which implies the great potential of the as-made cost-effective SiNW FET device in many fields.     

组合激光对单晶硅热作用的数值分析

为了提高激光加工中单晶硅材料对激光能量的耦合效率,采用一个短脉冲激光和一个长脉冲激光形成组合激光辐照单晶硅,使用COMSOL软件对该过程进行模拟,得到了组合激光长短脉冲间的延迟时间和长脉冲激光能量密度的变化对作用效果的影响,并与总能量相等的毫秒激光单独作用的效果进行比较;实验测量得到的不同能量密度的激光作用单晶硅后损伤形貌,与数值计算结果的趋势吻合。结果表明,组合激光能提高材料对激光的耦合效率;不同的延迟时间会影响组合激光的作用效果,最佳延迟时间为0.1ms;组合激光中毫秒激光能量密度占比较低时,作用效能较明显,随着毫秒激光能量密度占比的提高,对作用效果的提升相对变缓。该研究结果可以为组合激光的应用提供理论和实验依据。     

Role of interface chemistry and growing surface stoichiometry on the generation of stacking faults in ZnSe/GaAs

The existence of Zn-As and vacancy-contained Ga-Se interfacial layers are suggested by transmission electron microscopy of Zn-and Se-exposed (or - reacted) ZnSe/GaAs interfaces, respectively. A very low density of faulted defects in the range of ∼10⁴cm² was obtained in samples with Zn passivation on an Asstabilized GaAs-(2 × 4). However, the density of As precipitates increases as the surface coverage of c(4 × 4) reconstruction increased on the Zn-exposed Asstabilized GaAs-(2 × 4) surface and this is associated with an increase of the density of extrinsic-type stacking faults bound by partial edge dislocations with a core structure terminated on additional cations. On the other hand, densities of extrinsic Shockley-and intrinsic Frank-type stacking faults are of ∼5 × 10⁷/cm² in samples grown on Se-exposed Ga-rich GaAs-(4 × 6) surfaces. Annealing on this Se-exposed Ga-rich GaAs-(4 × 6) generated a high density of vacancy loops (1 × 10⁹/cm²) and an increase of the densities of both Shockley-and Frank-type stacking faults (>5 × 10⁸/cm²) after the growth of the films. Furthermore, we have studied the dependence of the generation and structure of Shockley-type stacking faults on the beam flux ratios in samples grown on Zn-exposed As-stabilized GaAs-(2 × 4) surfaces. Cation-and anion-terminated extrinsic-type partial edge dislocations were generated in samples grown under Zn-and Se-rich conditions, respectively. However, an asymmetric distribution on defect density under varied beam flux ratios (0.3 ≤ P_Se/P_Zn ≤ 10) is obtained.     

利用二次谐波产生研究Al2O3/Al(111)表面的动力学变化

主要介绍了当激光入射到单晶金属Al2O3／Al(111)表面时将发生二次谐波产生(SHG)现象的实验装置和实验方法,利用该装置可以研究SHG和从Al2O3／Al(111)表面反射的SHG在空间各向异性的变化情况,从而可以探测Al2O3／Al(111)表面结构对称性。实验中发现,当脉冲激光功率在2×106 W／cm2-9．6×106W／cm2范围内变化时,没有检测到SHG信号的各向异性变化;当使用P-极化泵浦激光时,发现Al2O3／Al(111)样品绕法线旋转360度时,P-极化的SHG信号在空间三个方向上呈现最大值相等;当使用脉冲强度为12×100 W／cm2的1064 nm P-极化泵浦激光时, Al2O3／Al(111)表面被损坏,损坏后的表面其SHG信号并不呈现对称的各向异性变化,当使用脉冲强度为11×106W／cm2的1064 nm P-极化泵浦激光时产生表面退火现象,从退火表面所产生的反射532 nm P-极化SHG信号中发现,SHG信号呈现衰减的各向异性成分。     

Au/Cd复合电极沉积方法对其与(111)面CdZnTe衬底接触性能的影响

CdZnTe晶片是HgCdTe外延薄膜的理想衬底。为了优化CdZnTe衬底的电学接触性能,作者基于真空蒸发法和磁控溅射法分别在p型导电性CdZnTe晶片(111)B (富碲面)制备Au/Cd复合电极。通过接触粘附试验,研究了复合电极的制备方法对电极与衬底之间的粘附性;利用卢瑟福背散射光谱法（RBS）比较了不同沉积方法下样品的元素深度分布;采用电流-电压(I-V)测试比较了两种制备工艺对Au/Cd复合电极与CdZnTe衬底欧姆接触特性的影响,从而确定了最佳复合电极的制备工艺。     

The influence of dose and protecting mask on electrically active defects induced by ion implantation in silicon

We present a study of electrically active defects induced by ion implantation, for two dopants: arsenic and phosphorous. Our analysis technique is Deep Level Transient Spectroscopy (D.L.T.S.). We have studied the generation of defects by direct implantation, and indirect implantation, that is through an SiO₂ layer. We follow the defect spectrum evolution for different doses (10⁸ to 10¹⁴ atoms/cm²) and for different annealing temperatures (from room temperature up to 800° C). The comparison of our results with other published ones allows us to improve the knowledge about the role of a protecting oxide layer, the influence of moderate thermal annealing, and the effect of oxygen on deep centers produced by ion bombardment.     

晶转埚转以及拉速对单晶硅生产过程的影响分析

单晶硅属于当前技术应用当中十分重要的一种半导体材料,其应用在电子信息技术领域以及太阳能技术领域当中的程度不断提升。当前单晶硅材料应用程度提升,也进一步增强了单晶硅在质量上的要求。换言之,单晶硅的杂质要求更高,加强杂质去除或者控制单晶硅当中的杂质氧含量就显得十分重要。本文侧重研究晶埚转以及拉速对单晶硅生产过程的影响分析。     

The influence of substrate temperature on the hydrogenated microcrystalline silicon growth through hollow cathode plasma

we exhibited the micro-hollow cathode (MHC) discharge to perform plasma enhanced chemical vapor deposition of hydrogenated microcrystalline silicon (μc-Si:H) in this paper. The role of substrate temperature on the μc-Si:H crystalline was focused. After testifying three substrates, glass, indium tin oxide (ITO) coating glass, and ITO coating polyimide (PI), we obtained over 80% crystalline volume fraction of μc-Si:H formed on the glass substrate. It was found that even the substrate temperature was as low as 120 °C the microcrystal Si can still be grown on ITO coating PI. We believe the high ionization rate in MHC due to hollow cathode effect promotes the microcrystal Si formation.     

（英）退火温度对电子束蒸发沉积硅薄膜结构和光学性能的影响

系统研究了退火温度对硅薄膜结构和光学性能的影响。通过电子束蒸发工艺制备硅薄膜,然后在氮气保护下对薄膜样品在200~500°C范围内进行退火处理。使用XRD、拉曼光谱、电子自旋共振和透射光谱测量等方法对薄膜样品进行了表征。结果显示,随着退火温度的升高,非晶硅薄膜结构有序度在短程和中程范围内得到改善,同时缺陷密度显著降低-。当样品在400°C退火后,消光系数k由6.14×10^-3下降到最小值1.02×10~3(1000 nm),这是由于此时硅薄膜缺陷密度也降到最低,约为沉积态薄膜的五分之一。试验结果表明,硅薄膜在适当的温度下退火可以有效地降低近红外区膜层的光学吸收,这对硅薄膜在光学薄膜器件研制中具有重要应用。     

THE GROWTH OF MONOCRYSTALLINE SILICON THIN FILM ON INSULATOR (SOI) BY SCANNING ELECTRON BEAM

An experiment for preparation of SOI films by using the scanning electron beam to modify the polycrystalline silicon on SiO2 is presented. This method takes on the epitaxial lateral growth of liquid phase with the crystallon to form monocrystalline silicon films. The effects of the beam power density, scanning velocity, temperature of the substrates and the construction of samples on the quality of the monocrystalline silicon films were discussed. A good experimental result has been obtained, the monocrystalline silicon zone is nearly 200×25μm2.     

氨化Si基Ga2O3/Co薄膜合成GaN纳米线及其表征

采用磁控溅射技术先在Si衬底上制备Ga2O3/Co薄膜,然后在950"C下流动的氨气中进行氨化反应制备GaN纳米棒.应用X射线衍射、扫描电镜、傅里叶红外吸收光谱、选区电子衍射和高分辨透射电子显微镜对样品进行表征.结果表明,采用此方法得到了六方纤锌矿结构的GaN单晶纳米棒.观察发现纳米棒表面光滑.并讨论了GaN纳米棒的生长机制.     

氨化Si基Ga2O3/Co薄膜合成GaN纳米线及其表征

采用磁控溅射技术先在Si衬底上制备Ga2O3/Co薄膜,然后在950"C下流动的氨气中进行氨化反应制备GaN纳米棒.应用X射线衍射、扫描电镜、傅里叶红外吸收光谱、选区电子衍射和高分辨透射电子显微镜对样品进行表征.结果表明,采用此方法得到了六方纤锌矿结构的GaN单晶纳米棒.观察发现纳米棒表面光滑.并讨论了GaN纳米棒的生长机制.     

A colloquium on the influence of versatile class of saturable nonlinear responses in the instability induced supercontinuum generation

We investigate the modulational instability induced supercontinuum generation (MI-SCG) under versatile saturable nonlinear (SNL) responses. We identify and discuss the salient features of saturable nonlinear responses of various functional forms such as exponential, conventional and coupled type on modulational instability (MI) and the subsequent supercontinuum (SC) process. Firstly, we analyze the impact of SNL on the MI spectrum and found both analytically and numerically that MI gain and bandwidth is maximum for exponential nonlinearity in comparison to other types of SNL’s. We also reported the unique behavior of the SNL system in the MI dynamics. Following the MI analysis, the proceeding section deals with the supercontinuum generation (SCG) process by virtue of MI. We examine exclusively the impact of each form of SNL on the SC spectrum and predicted numerically that exponential case attains the phase matching earlier and thus enable to achieve broad spectrum at a relatively shorter distance of propagation than the other cases of SNL’s. Thus a direct evidence of SCG from MI is emphasized and the impact of SNL in MI-SCG is highlighted. To analyze the quality of the output continuum spectrum, we performed the coherence analysis for MI-SCG in the presence of SNL.     

密闭式热场下<111>晶向Si单晶高晶转生长研究

在Kayex CG6000单晶炉上采用优化的350 mm密闭式热场,在23~25 r/min高晶转下用直拉法拉制出了Φ76.2~125 mm、n型高阻<111>晶向Si单晶,单晶的外形和径向电阻率均匀性良好。对<111>晶向Si单晶在高晶转下生长容易出现扭曲变形、棱面较宽现象的原因进行了分析。通过添加热屏,加强热场的保温和热屏的隔热作用,及缩小等径生长阶段熔Si液面与热屏间的距离,提高了晶体结晶前沿的温度梯度。从而避免了<111>晶向Si单晶的扭曲变形,减小了单晶棱面宽度,同时有利于消除晶体的漩涡缺陷。