Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability

Path delay fault model is the most suitable model for detectingdistributed manufacturing defects which can cause delayfaults. However, the number of paths in a modern design can beextremely large and the path delay testability of many practicaldesigns is very low. In this paper we show how to resynthesize acombinational circuit in order to reduce the total number of paths inthe circuit. Our results show that it is possible to obtain circuitswith a significant reduction in the number of paths while notincreasing area and/or delay of the longest sensitizable path in thecircuit.Research on path delay testing shows that in many circuits a largeportion of paths does not have a test that can guarantee detection ofa delay fault. The path delay testability of a circuit would increaseif the number of such paths is reduced. We show that addition of asmall number of test points into the circuit can help reducing thenumber of such paths in the given design.     

Delay Fault Coverage Enhancement Using Variable Observation Times

Detection of system timing failures has become a very importantproblem whenever high speed system operation is required. It has beendemonstrated that delay fault coverage loss could be significant if improperpropagation paths are used. This occurs when the delay test pair of a targetpropagation path cannot be effectively generated by an ATPG tool, or whenstuck-at test patterns are used as transition (or gate) delay test patterns.In this work, an efficient method is proposed to reduce the amount of faultcoverage loss by using variable observation times. The basic idea is tooffset the shorter propagation paths (really used) by tightening theobservation times. Given a probability distribution of defect sizes and aset of slack differences, this method is able to locate several observationtimes that result in small fault coverage loss.     

Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits

We present a technique to statistically estimate path-delay fault coverage for synchronous sequential circuits. We perform fault-free simulation using a multivalue algebra and accumulate signal transition statistics, from which we calculate controllabilities of all signals and sensitization probabilities for all gates and flip-flops. We use a rated clock testing model where all time frames operate at the rated clock. We obtain path observabilities either by enumerating paths in the all-paths method, or by a nonenumerative method considering only the longest paths. The path-delay fault detectability is the product of observabilities of signals on paths from primary inputs (PIs) or pseudo-primary inputs (PPIs) to primary outputs (POs) or pseudo-primary outputs (PPOs), and the controllability on the corresponding PI or PPI. We use the optimistic update rule of Bose et al. for updating latches during logic simulation. When compared with exact fault simulation, the average absolute deviation in our statistical fault coverage estimation technique is 1.23% and the very worst absolute deviation was 6.59%. On average, our method accelerates delay fault coverage computation four times over an exact path delay fault simulator.     

Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests

We classify all path-delay faults of a combinational circuit intothree categories: singly-testable (ST), multiply-testable (MT), and singly-testable dependent} (ST-dependent). The classification uses anyunaltered single stuck-at fault test generation tool. Only two runsof this tool on a model network derived from the original network areperformed. As a by-product of this process, we generate single andmultiple input change delay tests for all testable faults. With thesetests, we expect that most defective circuits are identified. All STfaults are guaranteed detection in the case of a single fault, andsome may be guaranteed detection through robust and validatablenon-robust tests even in the case of multiple faults. An ST-dependentfault can affect the circuit speed only if certain ST faults arepresent. Thus, if all ST faults are tested, the ST-dependent faultsneed not be tested. MT faults cannot be guaranteed detection, butaffect the speed only if delay faults simultaneously exist on a setof paths, none of which is ST. Examples and results on several ISCAS89 benchmarks are presented. The method of classification throughtest generation using a model network is complex and can be appliedto circuits of moderate size. For larger circuits, alternativemethods will have to be explored in the future.     

Design for Delay Testability in High-Speed Digital ICs

The cost-effective testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, costly testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a Design for Delay Testability (DfDT) technique such that high-speed ICs can be tested using inexpensive, low-speed test systems. Also extensions for possible full BIST of delay faults are addressed.     

On local transformations and path delay fault testability

Several synthesis for path delay fault (PDF) testability approaches are based on local transformations of digital circuits. Different methods were used to show that transformations preserve or improve PDF testability. In this paper we present a new unifying approach to show that local transformations preserve or improve PDF testability. This approach can be applied to every local transformation and in contrast to previously published methods only the subcircuits to be transformed have to be considered.Using our new approach we are able to show in a very convenient way that the transformations which are already used in synthesis tools preserve or improve PDF testability. We present further transformations which preserve or improve testability. We show that a transformation, claimed to preserve PDF testability, in fact, does not do so. Moreover, the testability improving factor which is a unit of measurement for the quality of testability improving transformations is introduced.Additionally, we present the capabilities of SALT (system forapplication oflocaltransformations), which is a general tool for application of a predefined set of local transformations. The implementation of SALT is described and it is shown how the isomorphism of a pattern to be searched and a matched subcircuit can be weakened to allow the application of local transformations more frequently.Finally, we confirm the theoretical part of this paper by experimental results obtained by application of the examined local transformations to several benchmark circuits. The effect of these transformations (and combinations of different types of transformations) on PDF testability, size and depth of the transformed circuits is examined and encouraging results are presented. For example, a reduction of up to 90% can be observed for the number of untestable paths.This work was supported in part by DFG grants Be 1176/4-1, Be 1176/4-2 and SFB 124 VLSI Design Methods and Parallelism.     

Efficient Path Selection for Delay Testing Based on Path Clustering

In this paper, we introduce a way of modeling the differences between the calculated delays and the real delays, and propose an efficient path selection method for path delay testing based on the model. Path selection is done by judging which of two paths has the larger real delay by taking into account the ambiguity of calculated delay, caused by imprecise delay modeling as well as process disturbances. In order to make precise judgment under this ambiguity, the delays of only the unshared segments of the two paths are evaluated. This is because the shared segments are presumed to have the same real delays on both paths.The experiments used the delays of gates and interconnects, which were calculated from the layout data of ISCAS85 benchmark circuits using a real cell library. Experimental results show the method selects only about one percent of the paths selected by the most popular method.     

Oscillation Ring Delay Test for High Performance Microprocessors

This paper proposes a new test scheme, oscillation ring test, and its associated test circuit organization for delay fault testing for high performance microprocessors. For this test scheme, the outputs of the circuit under test are connected to its inputs to form oscillation rings and test vectors which sensitize circuit paths are sought to make the rings oscillate. High speed transition counters or oscillation detectors can then be used to detect whether the circuit is working normally or not. The sensitizable paths of oscillation rings cover all circuit lines, detecting all gate delay faults, a large part of hazard free robust path delay faults and all the stuck-at faults. It has the advantage of testing the circuit at the working speed of the circuit. Also, with some modification, the scheme can also be used to measure the maximum speed of the circuit. The scheme needs minimal simple added hardware, thus ideal for testing, embedded circuits and microprocessors.     

Fault macromodeling and a testing strategy for opamps

In this paper, we propose a simple testing technique based on DC measurements for operational amplifiers. We first develop a comprehensive macromodel for the transistor-level opamp to alleviate the efforts of fault simulation. By incorporating appropriate I/O characteristics into the macromodel, the output deviation due to the modeling error can be significantly reduced. We use the transistor short/bridging faults to illustrate the efficiency of our proposed technique. Experimental results show that a high fault coverage can be achieved for the stand-alone opamp by measuring two DC parameters V _o-max ^* and V _o-min ^*. For the embedded opamps, many short/bridging faults cannot be detected by traditional functional testing. However, by using similar DC measurements along with a design for testability (DFT) scheme, we can improve the fault coverage dramatically.An earlier version of this work was reported in ICCAD-94.     

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

With increasing defect density and process variations in nanometer technologies, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. This paper presents a novel test technique based on supply gating, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overhead. Experimental results on a set of ISCAS89 benchmarks show an average reduction of 34% in area overhead with an average improvement of 65% in delay overhead and 90% in power overhead during normal mode of operation, compared to the enhanced scan implementation.

Fault Modeling and Fault Simulation in Mixed Micro-Fluidic Microelectronic Systems

Developments in electronic/fluidic microsystems are progressing rapidly. The ultimate goal is to deliver products in the 10,000 fluidic reaction-wells range. Exciting applications include massive parallel DNA analysis and automatic drug synthesis. Until now, only functional testing has been used to guarantee the quality of micro-fluidic systems after manufacturing.In this paper, defect-oriented test approaches developed in analogue fault modeling and simulation have been used to predict for the first time the faulty behavior of micro-electronic fluidic microsystems. The modeling is targeted for use in complex electronic/fluidic microsystems employing commercial microsystem CAD tools. It enables a measure for the quality of these systems based on the performed (functional) tests and can be a guide for future test-stimuli generation and yield prediction.     

基于故障仿真和粗糙集的复杂电路板测试性分析

针对关联模型在复杂电路板测试性分析中对不确定问题描述与分析的缺陷,提出了基于故障仿真和粗糙集的测试性分析方法.通过故障仿真生成条件属性集,利用粗糙集将其约简,最终形成分辨矩阵,从而评价电路的测试性水平.最后通过实例分析验证了方法的有效性.     

阵列乘法器通路时延故障的内建自测试

阵列乘法器因高度集成和高速运行,容易受到时延故障的困扰.该文对阵列乘法器的通路时延故障提出了一种用累加器实现的以单跳变序列作为测试序列的内建自测试方案.已有的理论和实践表明采用单跳变测试序列比多跳变序列具有更高的测试鲁棒性.同时,该文的测试方案在测试通路覆盖率和测试向量数之间做到了兼顾.仿真结果表明这种单跳变测试序列具有高测试通路覆盖率.此外,测试生成通过系统已有累加器的复用可节省硬件成本开销.     

Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits

A Body biasing technique has recently been proposed for microprocessors in sub-100 nm technology generations [11, 12]. It is shown that forward body bias (FBB) reduces the leakage power and suppresses the effect of process variation while reducing the complexity of dualV_th technology. In this paper, we study the effect of body bias on the delay fault testing of CMOS circuits. We analyze the impact of both fixed and adaptive body biasing techniques on test cost and the quality of test. Statistical analysis on several benchmark circuits shows that the adaptive body biasing design will have the most effective impact on delay fault by maintaining the test cost at its minimum under process variation while ensuring the test quality at its highest level. Bipul C. Paul received B.Tech. and M.Tech. degrees in radiophysics and electronics, from the University of Calcutta and the Ph.D. degree from Indian Institute of Science (IISc), Bangalore, India. After his graduation, he joined Alliance Semiconductor (India), where he worked on synchronous DRAM design. In 2000, he joined Purdue University, West Lafayette, USA, as a Post Doctoral Fellow, where he worked on low-power electronic design of nanoscale circuits (both bulk and SOI technologies), statistical design under process variation, VLSI testing, verification and noise analysis. He has also developed device and circuit optimization techniques for ultra-low power digital sub-threshold operation. Dr. Paul is presently with Toshiba Research, where he is working on post-silicon devices and technology and nano-architecture. He is also a Visiting Scientist at Stanford University, USA. Dr. Paul received National scholarship (India) in 1984, the senior research fellowship award from CSIR, India in 1995 and the Best Thesis of the Year award in 1999. He is a senior member of IEEE. Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor. His research interests include VLSI design/CAD with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. Dr. Roy has published more than 200 papers in refereed journals and conferences, holds 5 patents, and is a co-author of a book on Low Power CMOS VLSI Design (John Wiley). Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, best paper awards at 1997 International Test Conference and 2000 International Symposium on Quality of IC Design, and is currently a Purdue University faculty scholar professor. He is in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, and IEEE Transactions on VLSI Systems. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000). Dr. Roy is fellow of IEEE.     

Fault Modeling and Simulation Using VHDL-AMS

Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome.     

Fault simulation for general FCMOS ICs

This work presents a technique to correctly deal with non-stuck-at faults in FCMOS circuits making use of complex macrogates. This method can be applied to any gate-level fault simulator providing, for each line of the circuit, the observability status that is directly related to that of individual devices in the actual macrogate implementation. Conductance conflicts are correctly solved to detect bridgings and transistors stuck-on. Fault coverage results are presented and discussed for two typical FCMOS circuits. Results obtained on all ISCAS benchmarks show that the time required for the fault simulation of CMOS faults is comparable to that of stuck-ats.     

The Coupling Model for Function and Delay Faults

We propose a high-level fault model, the coupling fault (CF) model, that aims to cover both functional and timing faults in an integrated way. The basic properties of CFs and the corresponding tests are analyzed, focusing on their relationship with other fault models and their test requirements. A test generation program COTEGE for CFs is presented. Experiments with COTEGE are described which show that (reduced) coupling test sets can efficiently cover standard stuck-at-0/1 faults in a variety of different realizations. The corresponding coupling delay tests detect all robust path delay faults in any realization of a logic function. This research was sponsored in part by the U.S. National Science Foundation under Grants No. CCR-9872066 and CCR-0073406. Joonhwan Yi received the B.S degree in electronics engineering from Yonsei University, Seoul, Korea, in 1991, and the M.S. and Ph.D degrees in electrical engineering and computer science from the University of Michigan, Ann Arbor, in 1998 and 2002, respectively. From 1991 to 1995, he was with Samsung Electronics, Semiconductor Business, Korea, where he was involved in developing application specific integrated circuit cell libraries. In 2000, he was a summer intern with Cisco, Santa Clara, CA, where he worked for path delay fault testing. Since 2003, he has been with Samsung Electronics, Telecommunication Network, Suwon, Korea, where he is working on system-on-a-chip design. His current research interests include C-level system modeling for fast hardware and software co-simulation, system-level power analysis and optimization, behavioral synthesis, and high-level testing. John P. Hayes received the B.E. degree from the National University of Ireland, Dublin, and the M.S. and Ph.D. degrees from the University of Illinois, Urbana-Champaign, all in electrical engineering. While at the University of Illinois, he participated in the design of the ILLIAC III computer. In 1970 he joined the Operations Research Group at the Shell Benelux Computing Center in The Hague, where he worked on mathematical programming and software development. From 1972 to 1982 he was a faculty member of the Departments of Electrical Engineering– Systems and Computer Science of the University of Southern California, Los Angeles. Since 1982 he has been with the Electrical Engineering and Computer Science Department of the University of Michigan, Ann Arbor, where he holds the Claude E. Shannon Chair in Engineering Science. Professor Hayes was the Founding Director of the University of Michigan's Advanced Computer Architecture Laboratory (ACAL). He has authored over 225 technical papers, several patents, and five books, including Introduction to Digital Logic Design (Addison-Wesley, 1993), and Computer Architecture and Organization, (3rd edition, McGraw-Hill, 1998). He has served as editor of various technical journals, including the Communications of the ACM, the IEEE Transactions on Parallel and Distributed Systems and the Journal of Electronic Testing. Professor Hayes is a fellow of both IEEE and ACM, and a member of Sigma Xi. He received the University of Michigan's Distinguished Faculty Achievement Award in 1999 and the Humboldt Foundation's Research Award in 2004. His current teaching and research interests are in the areas of computer-aided design, verification, and testing; VLSI circuits; fault-tolerant embedded systems; ad-hoc computer networks; and quantum computing.     

Synthesis of Sequential Circuits by Redundancy Removal and Retiming

In this paper we propose a method for synthesizing sequentialcircuits to reduce the number of gates and flip-flops by removingboth combinationally and sequentially redundant faults. In order toremove sequentially redundant faults these faults are converted intocombinationally redundant faults by using retiming techniques and thecombinationally redundant faults can be removed by using a testpattern generation method for combinational circuits. To simplify agiven circuit retiming is utilized for two purposes in thismethod. One is to find sequentially redundant faults and another is toreduce the number of flip-flops and gates. Before and after eachretiming the combinationally redundant faults are removed.Experimental results for ISCAS 89 benchmark circuits show that thismethod can remove many of sequentially redundant faults and canreduce a large number of gates and flip-flops.     

Detection of Delay Faults in Memory Address Decoders

In this paper we present an efficient test concept for detection of delay faults in memory address decoders based on the march test tactic. The proposed Transition Sequence Generator (TSG) generates an optimal transition sequence for sensitization of the delay faults in address decoders by Hayes's transformation on a reflected Gray code. It can be used for parallel Built-In Self-Testing (BIST) of high-density RAMs. We also present an efficient Design For Test (DFT) approach for immediate detection of the effects of the delay faults in the address decoders which does not change memory access time. It requires extra logic to be attached to the outputs of the address decoders. This DFT approach can be used to increase memory testability for both on-line and off-line testing of single- and multi-port RAMs.