Inductance model and analysis methodology for high-speed on-chip interconnect

With operating frequencies entering the multi-gigahertz range, inductance has become an important consideration in the design and analysis of on-chip interconnects. In this paper, we present an accurate and efficient inductance modeling and analysis methodology for high-performance interconnect. We determine the critical elements for a PEEC based model by analyzing the current flow in the power grid and signal interconnect. The proposed model includes distributed interconnect resistance, inductance and capacitance, device decoupling capacitances, quiescent switching currents in the grid, pad connections, and pad/package inductance. We propose an efficient methodology for extracting these elements, using statistical models for on-chip decoupling capacitance and switching currents. Simulation results show the importance of various elements for accurate inductance analysis. We also demonstrate the accuracy of the proposed model compared to the traditional loop-based inductance approach. Since the proposed model can consist of hundreds of thousands of RLC elements, and a fully dense mutual inductance matrix, we propose a number of acceleration techniques that enable efficient analysis of large interconnect structures.     

异步时钟亚稳态仿真方法

当信号跨越时钟域的时候,会带来亚稳态问题,现在通用的做法是两级触发器同步来消除亚稳态。实际电路中在目的寄存器的时钟域获得该信号的时间可能不固定,通常相差一个时钟,提出了一种仿真方法,可以仿真实际电路中这种不确定现象。通过这种方法可以在仿真阶段检查跨时钟域信号设计是否合理。避免实际电路中的这种不稳定带来的功能失效。     

A multiconductor transmission line methodology for global on-chip interconnect modeling and analysis

This paper describes a methodology for global on-chip interconnect modeling and analysis using frequency-dependent multiconductor transmission lines. The methodology allows designers to contain the complexity of series impedance computation by transforming the generic inductance and resistance extraction problem into one of per-unit-length parameter extraction. This methodology has been embodied in a CAD tool that is now in production use by interconnect designers and complementary metal oxide semiconductor (CMOS) process technologists.     

A switch-level test generation system for synchronous and asynchronous circuits

A switch-level test generation system for synchronous and asynchronous circuits has been developed in which a new algorithm for fully automatic switch-level test generation and an existing fault simulator have been integrated. For test generation, a switch-level circuit is modeled as a logic network that correctly models the behavior of the switch-level including bidirectionality, dynamic charge storage, and ratioed logic. The algorithm is able to generate tests for combinational and sequential circuits. BothnMOS and CMOS circuits can be modeled. In addition to the classical line stuck-at faults, the algorithm is able to handle stuck-open and stuck-closed faults on the transistors of the circuit.In synchronous circuits, the time-frame based algorithm uses asynchronous processing within each clock phase to achieve stability in the circuit and synchronous processing between clock phases to model the passage of time. In asynchronous circuits, the algorithm uses asynchronous processing to reach stability within and between modules. Unlike earlier time-frame based test generators for general sequential circuits, the test generator presented uses the monotonicity of the logic network to speed up the search for a solution. Results on benchmark circuits show that the test generator outperforms an existing switch-level test generator both in time and space requirements. The algorithm is adaptable to mixed-level test generation.     

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving

High temperature has become a major problem for system-on-chip testing. In order to reduce the test application time while keeping the temperatures of the cores under test within safe ranges, a thermal-aware test scheduling technique is required. This paper presents an approach to minimize the test application time and, at the same time, prevent the temperatures of cores under test going beyond given limits. We employ test set partitioning to divide test sets into shorter test sequences, and add cooling periods between test sequences so that overheating can be avoided. Moreover, test sequences from different test sets are interleaved, such that the cooling periods and the bandwidth of the test bus can be utilized for test data transportation, and hence the test application time can be reduced. The test scheduling problem is formulated as a combinatorial optimization problem, and we use the constraint logic programming (CLP) to build the optimization model and find the optimal solution. As the optimization time of the CLP-based approach increases exponentially with the problem size, we also propose a heuristic which generates longer test schedules but requires substantially shorter optimization time. Experimental results have shown the efficiency of the proposed approach.     

SOC芯片的高速模拟IP测试方法学

很多SoC芯片里会使用SATA物理层,PCIE物理层以及DDR2/DDR3物理层等高速模拟IP。这些高速模拟IP需要被自动测试设备完整的测试。自动测试设备的高速测试选项就是用来测试高速IP,但随之而来的是测试成本的增加。智原科技利用内建自测试方法来取代费钱的自动测试设备的高速测试选项。内建自测试提供了最具成本效率的方法。高速模拟IP内建自测试的故障覆盖率很高,所以我们不再需要自动测试设备的高速测试选项及其所带来的高成本。     

On the generation of large passive macromodels for complex interconnect structures

This paper addresses some issues related to the passivity of interconnect macromodels computed from measured or simulated port responses. The generation of such macromodels is usually performed via suitable least squares fitting algorithms. When the number of ports and the dynamic order of the macromodel is large, the inclusion of passivity constraints in the fitting process is cumbersome and results in excessive computational and storage requirements. Therefore, we consider in this work a post-processing approach for passivity enforcement, aimed at the detection and compensation of passivity violations without compromising the model accuracy. Two complementary issues are addressed. First, we consider the enforcement of asymptotic passivity at high frequencies based on the perturbation of the direct coupling term in the transfer matrix. We show how potential problems may arise when off-band poles are present in the model. Second, the enforcement of uniform passivity throughout the entire frequency axis is performed via an iterative perturbation scheme on the purely imaginary eigenvalues of associated Hamiltonian matrices. A special formulation of this spectral perturbation using possibly large but sparse matrices allows the passivity compensation to be performed at a cost which scales only linearly with the order of the system. This formulation involves a restarted Arnoldi iteration combined with a complex frequency hopping algorithm for the selective computation of the imaginary eigenvalues to be perturbed. Some examples of interconnect models are used to illustrate the performance of the proposed techniques.     

Process-Variation and Temperature Aware SoC Test Scheduling Technique

High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoC). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these deviations will be suboptimal in terms of speed or thermal-safety. This paper presents an adaptive test scheduling method which acts in response to the temperature deviations in order to improve the test speed and thermal safety. The method consists of an offline phase and an online phase. In the offline phase a schedule tree is constructed and in the online phase the appropriate path in the schedule tree is traversed based on temperature sensor readings. The proposed technique is designed to keep the online phase very simple by shifting the complexity into the offline phase. In order to efficiently produce high-quality schedules, an optimization heuristic which utilizes a dedicated thermal simulation is developed. Experiments are performed on a number of SoCs including the ITC’02 benchmarks and the experimental results demonstrate that the proposed technique significantly improves the cost of the test in comparison with the best existing test scheduling method.     

A Novel Variable Shifting Code for Test Compression of SoC

The test vector compression is a key technique to reduce IC test time and cost since the explosion of the test data of system on chip （SoC） in recent years. To reduce the bandwidth requirement between the automatic test equipment （ATE） and the CUT （circuit under test） effectively, a novel VSPTIDR （variable shifting prefix-tail identifier reverse） code for test stimulus data compression is designed. The encoding scheme is defined and analyzed in detail, and the decoder is presented and discussed. While the probability of 0 bits in the test set is greater than 0.92, the compression ratio from VSPTIDR code is better than the frequency-directed run-length （FDR） code, which can be proved by theoretical analysis and experiments. And the on-chip area overhead of VSPTIDR decoder is about 15.75 % less than the FDR decoder.     

A scheduler synthesis methodology for joint SW/HW design exploration of SoC

The introduction of high-performance applications such as multimedia applications into SoCs led the manufacturers to provide embedded SoCs able to offer an important computing power which makes it possible to answer the increasing requirements of future evolutions of these applications. One of the adopted solutions is the use of multiprocessor SoCs. In this paper, we present a joint SW/HW design exploration methodology for multiprocessor SoCs. The system model relies on transaction-level component-based models for modeling parallel software and multiprocessor hardware. Our proposal comprises two original points. First, we propose a composable software-level scheduler constraints synthesis technique. Second, we present a combined software-level and exploratory hardware-level schedulers. The methodology has the advantage of combining real-time requirements of software with effective exploitation of multiprocessor hardware. We describe and apply the methodology to synthesize a scheduler of a slice-based MPEG-4 video encoder on the multiprocessor Cake SoCs.     

Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition

With increasing power density in modern integrated circuits, thermal issues are becoming a critical problem in System-on-a-Chip (SoC) testing. In this paper, we develop the thermal-aware test scheduling methods using Voltage/Frequency Scaling (VFS) and Test Partition (TP) to reduce the expensive Test Application Time (TAT). First, we develop a quick temperature estimation method in test scheduling to ensure the test temperature within the given range. Second, we propose a thermal-aware test scheduling method based on the mixed-integer linear programming model (MILP) (called STP-M) that applies VFS and TP to search the optimum scheduling and further reduce the TAT. Third, we develop a heuristic method based on Rectangular Strip Packing (called H-RSP) to quickly access the quasi-optimal scheduling. The experimental results on ITC’02 benchmarks showed that the STP-M obtains the most optimized result for every benchmark and saved 15.5% and 8.0% TAT on average compared with the existing works, while H-RSP takes less than 10 seconds to access the quasi-optimal scheduling that is close to that of STP-M.     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

A novel automatic test pattern generator for asynchronous sequential digital circuits

A novel automatic test pattern generator (ATPG) for stuck-at faults of asynchronous sequential digital circuits is presented. The developed ATPG does not require support by any design-for-testability method nor external software tool. The shortest test sequence generation is guaranteed by breadth-first search. The contribution is unique hazard identification before the test generation process, state justification on the gate level, sequential fault propagation based on breadth-first search and stepwise composition of state graphs for sequential test generation. A new six-valued logic together with a new algorithm was developed for hazardous transition identification. The internal combinational ATPG allows to generate test patterns one by one and only if it is required by sequential test generation. The developed and implemented ATPG was tested with speed-independent and quasi-delay-insensitive benchmark circuits.     

Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding

Growing test data volume and excessive test application time are two serious concerns in scan-based testing for SoCs. This paper presents an efficient test-independent compression technique based on block merging and eight coding (BM-8C) to reduce the test data volume and test application time. Test compression is achieved by encoding the merged blocks after merging consecutive compatible blocks with exact eight codewords. The proposed scheme compresses the pre-computed test data without requiring any structural information of the circuit under test. Therefore, it is applicable for IP cores in SoCs. Experimental results demonstrate that the BM-8C technique can achieve an average compression ratio up to 68.14 % with significant low test application time.     

Power control for an asynchronous multirate decorrelator

For code-division multiple-access (CDMA) wireless systems employing multiuser detection, the varied bit-error rate (BER) requirements of multimedia traffic dictate the use of transmitted power control. Using a decorrelator in an asynchronous multirate direct-sequence CDMA system, it may be necessary for different users to combat the noise enhancement and the propagation losses to varying degrees depending on individual requirements. In this context, we propose a power control algorithm for a multirate decorrelator that is suitable for a class of BER-based link quality objectives. If the uplink channel gain of the desired user is known, then it is straightforward for each user to choose the transmitted power needed to meet its target BER objective. In practice, however, the uplink channel gain is often difficult to measure. To avoid this measurement, we employ stochastic approximation methods to develop a simple iterative power control algorithm. In this algorithm, each mobile uses the output of its own decorrelator to update its transmitted power in order to achieve its BER objective. We show that when a user's bits have nonzero asymptotic efficiencies, the power control algorithm converges quickly in the mean square sense to the minimum power at which a user achieves its quality-of-service objective     

SoC的存储器Wrapper设计及故障测试

在系统芯片SoC测试中,存储器的可靠性测试是一项非常重要内容.IEEE Std 1500是专门针对嵌入式芯核测试所制定的国际标准,规范了IP核提供者和使用者之间的标准接口.基于此标准完成针对SoC存储器的Wrapper测试壳结构和控制器的设计.以32×8的SRAM为测试对象进行测试验证.结果表明,系统能够准确的诊断出存储器存在故障.     

龙芯税控SoC中Bootloader的设计与分析

本文介绍了龙芯税控SoC中Bootloader的设计过程,并详细分析了Bootloader中关于外部中断(IRQ)处理的详细过程.     

Laser scanning for semiconductor mask pattern generation

The use of laser scanning to generate semiconductor masks is reviewed. Following a brief historical introduction that describes early pattern generator implementations, current and future industry mask requirements are described with the consequences for pattern generator design: the need for small features, tight CD control, and high pixel delivery rates. The system architecture of a current deep UV scanning system is described in detail along with important print strategies, such as grayscale printing and multipass error averaging. Several subsystem technologies are then explored with emphasis on the application to short wavelengths and multiple beams. Today, frequency-doubled lasers generate the 257-nm radiation used by DUV pattern generators; tomorrow, sum frequency generation will be required to reach the wavelengths at or below 200 nm. Acousto-optic modulation (AOM) technology is shown to scale favorably with shorter wavelengths and to have the bandwidth capability for future system. Acousto-optic beam deflection, polygonal mirror beam deflection, and the reduction of scan bow error through the use of an f /spl middot/ sin(/spl theta/) lens are examined. A section on scan optics and image formation presents the differences between partially coherent imaging as used by a wafer stepper and the incoherent superposition of Gaussian beams as used by a laser scanner. Partially coherent imaging is shown to have a sharper image slope but worse feature size linearity. This section also discusses the effect of finite AOM turn-on time on the aerial image in the scan direction.