A precision reference voltage source

With increasing temperature the base-emitter voltage of a transistor with a constant current decreases, while the difference in base-emitter voltages of two identical (integrated) transistors having a constant current ratio increases. From the sum of the two voltages a nearly temperature- independent output voltage is obtained if this sum equals the gap voltage of silicon. A reference voltage source of 10 V based on the principle is described. The reference part of the circuit is an integrated circuit, and thin-film resistors with a small relative temperature coefficient are used. An operational amplifier and a few resistors and capacitors complete the circuit. The source has a parabolic temperature characteristic and the temperature peak can be controlled by resistor adjustment. A change of /spl plusmn/10 K in respect of the peak temperature causes an output voltage change of -250 /spl mu/V, while a change of /spl plusmn/30 K causes a change of -2.2 mV. A long-term stability of 10 ppm/month was measured. The circuit can compete with the best available Zener diode sources, and has the added advantage that practically no selection is necessary.     

Current-source a-Si:H thin-film transistor circuit for active-matrix organic light-emitting displays

In this letter, we describe a four thin-film-transistor (TFT) circuit based on hydrogenated amorphous silicon (a-Si:H) technology. This circuit can provide a constant output current level and can be automatically adjusted for TFT threshold voltage variations. The experimental results indicated that, for TFT threshold voltage shift as large as /spl sim/3 V, the output current variations can be less than 1 and 5% for high (/spl ges/0.5 /spl mu/A) and low (/spl les/0.1 /spl mu/A) current levels, respectively. This circuit can potentially be used for the active-matrix organic light-emitting displays (AM-OLEDs).     

A new NMOS temperature-stable voltage reference

An NMOS voltage reference has been developed that exhibits extremely low drift with temperature. The reference is based on the difference between the gate/source voltages of enhancement and depletion-mode NMOS transistors. The theoretical dependence of the reference voltage on both device and circuit parameters is analyzed and conditions for optimal performance are derived. The reference NMOS transistors are biased to the optimizing current levels by a unique feedback circuit. The measured output voltage drift in the integrated realization agrees well with theory and is less than 5 parts per million per degree Celsius over the temperature range -55/spl deg/ to +125/spl deg/C.     

A high current drive CMOS output stage with a tunable quiescent current limiting circuit

A CMOS output stage based on a complementary common source with an original quiescent current limiting circuit is presented. The quiescent current can be varied over a wide range by means of a control current with no need to modify the transistor aspect ratios. The output stage has been coupled to a conventional complementary input stage to form a rail-to-rail buffer. A prototype with the inclusion of auxiliary pins for biasing and current monitoring purposes has been designed using the 1-/spl mu/m double-polysilicon BCD3S process of STMicroelectronics. On a single 5-V power supply, the maximum output current is 20 mA. The amplifier, biased for a total power dissipation of 1 mW, exhibits a total harmonic distortion of -58 dB at 1 kHz with 4-V peak-to-peak on a 330-/spl Omega/ load. Correct operation of the quiescent current limiting circuit has been demonstrated for a minimum supply voltage of 2.2 V.     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.     

A bipolar monolithic multigigabit/s decision circuit

A monolithic multigigabit/s decision circuit using a 0.5-/spl mu/m bipolar process technology called advanced super self-aligned technology (SST-1A) has been developed. A special decision circuit including a novel current switch based on a nonthreshold logic circuit and a cutoff prevention principle was designed and fabricated. An output voltage swing of 1 V across a 50-/spl Omega/ load, a fast transition time of 90 ps (10-90%) and 3.6 Gbit/s operation have been achieved. Power dissipation per chip is about 600 mW. This IC is applicable to very-high-speed optical fiber transmission system repeaters.     

A realization of a below-1-V operational and 30-MS/s sample-and-hold IC with a 56-dB signal-to-noise ratio by applying the current-based circuit approach

This paper demonstrates the low-voltage and low-power operation of a MOS sample-and-hold circuit while preserving speed and accuracy, aiming at the realization of a pipelined low-voltage and low-power analog-to-digital converter on a system large-scale integrated circuit. It was fabricated by utilizing 0.35-/spl mu/m CMOS technology. The main feature of this circuit is that all the input, signals, and output are in the current form. The circuit consists of simple current mirrors. In order to eliminate the signal-dependent current transfer ratio error, voltages at the drain terminals of mirror transistors are fixed as constant. A source degeneration resistor, which is a transistor in the triode operational region, is connected to a mirror transistor in order to alleviate the influence of the threshold and transconductance parameter variations. Control signals are boosted in voltage and applied to the gate of switch NMOS transistors in the signal path in order to reduce the on-resistance of analog switches. A differential configuration is adopted throughout the entire circuit and effectively cancels switch feedthrough errors. As a result, a 30-MS/s operation with a signal-to-noise ratio (SNR) of 56 dB from a 1-V supply has been achieved, when the input current is /spl plusmn/200 /spl mu/A. The chip even operated down to 0.85 V with a 20-MHz clock. The SNR was measured as 50 dB with an input current of /spl plusmn/100 /spl mu/A.     

A low-voltage CMOS bandgap reference

The CMOS bandgap voltage reference described here uses the bipolar substrate-transistor and the bipolar-like source-to-drain transfer characteristics of MOS transistors in weak inversion to implement a voltage source that is proportional to absolute temperature (PTAT). A first version of PTAT source is derived from a circuit described previously. A second version is based on a novel cell that can be stacked to obtain the desired voltage. Both versions operate down to 1.3 V with a current drain below 1 /spl mu/A. A stability of 3 mV over 100/spl deg/C has been obtained with a few nonadjusted samples. Experimental results suggest some possible improvements to extend this stability to every circuit.     

CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration

A new CMOS voltage reference circuit consisting of two pairs of transistors is presented. One pair exhibits a threshold voltage difference with a negative temperature coefficient (-0.49 mV//spl deg/C), while the other exhibits a positive temperature coefficient (+0.17 mV//spl deg/C). The circuit was robust to process variations and exhibited excellent temperature independence and stable output voltage. Aside from conductivity type and impurity concentrations of gate electrodes, transistors in the pairs were identical, meaning that the system was robust with respect to process fluctuations. Measurements of the voltage reference circuit without trimming adjustments revealed that it had excellent output voltage reproducibility of within /spl plusmn/2%, low temperature coefficient of less than 80 ppm//spl deg/C, and low current consumption of 0.6 /spl mu/A.     

A two-terminal IC temperature transducer

A bipolar monolithic IC temperature transducer with an operating temperature range of -125/spl deg/C to +200/spl deg/C has been designed, fabricated, and tested. The two-terminal device, which is fabricated using laser trimmed thin-film-on-silicon technology, is a calibrated temperature dependent current source with an average output impedence of 10 M/spl Omega/ over the 3.5-V to 30-V range of input voltage. Overall absolute accuracies of /spl plusmn/0.5/spl deg/C from -75/spl deg/C to +150/spl deg/C have been achieved on a scale of 1 /spl mu/A/K under optimum operating conditions.     

Low-voltage high performance compact all cascode CMOS current mirror

A high performance and compact current mirror with extremely low input and high output resistances (R/sub in//spl sim/0.01/spl Omega/, R/sub out//spl sim/10 G/spl Omega/), high copying accuracy, very low input and output voltage requirements (V/sub in/, V/sub out//spl ges/V/sub DSsat/), high bandwidth (200 MHz using a 0.5 /spl mu/m CMOS technology) and low settling time (25 ns) is proposed. Simulations and experimental results are shown that validate the circuit.     

Low-voltage temperature sensor for micro-power harvesters in silicon-on-sapphire CMOS

A low-voltage temperature sensor designed for MEMS power harvesting systems is fabricated. The core of the sensor is a bandgap voltage reference circuit operating with a supply voltage in the range 1-1.5 V. The prototype was fabricated on a conventional 0.5 /spl mu/m silicon-on-sapphire (SOS) process. The sensor design consumes 15 /spl mu/A of current at 1 V. The internal reference voltage is 550 mV. The temperature sensor has a digital square wave output the frequency of which is proportional to temperature. A linear model of the dependency of output frequency with temperature has a conversion factor of 1.6 kHz//spl deg/C. The output is also independent of supply voltage in the range 1-1.5 V. Measured results and targeted applications for the proposed circuit are reported.     

Two-wire bridge-to-frequency converter

An integrated two-wire bridge-to-frequency converter is presented for use as a remote-signal conditioner for sensor bridges such as strain-gauge bridges of platinum-wire temperature-sensing bridges. The converter has a sensitivity on the order of 1 Hz per 1-/spl mu/V/V relative bridge output. A center frequency of 10 kHz allows the application of an untrimmed bridge with an imbalance up to /spl plusmn/10000 /spl mu/V/V. The instability is less than 10/SUP -4/ per Kelvin and per 1-V supply-voltage variation. The untrimmed transfer inaccuracy is lower than 1%. The linearity error is lower than 0.01%. Different bridge readout functions can be chosen by different circuit configurations. The converter can be connected to a single supply voltage. The frequency output is modulated on the supply current. The supply voltage is 12-24 V.     

A low-power microcontroller having a 0.5-/spl mu/A standby current on-chip regulator with dual-reference scheme

We present a microcontroller having a 0.5-/spl mu/A standby current on-chip regulator. To break through the area overhead problem which a conventional regulator scheme suffers from to achieve small standby current, we propose a dual-reference scheme in which one voltage reference circuit is provided for active mode and another voltage reference circuit is provided for standby mode. For the voltage reference circuit for standby mode, a resistor-free circuit was used to achieve small current consumption without occupying large area. The microcontroller was fabricated in a 0.18-/spl mu/m CMOS process. The implementation and measurement results show that the dual-reference scheme achieves 0.5-/spl mu/A current consumption of the regulator in standby mode with 50% smaller area than the conventional scheme. The measured standby current of the whole chip was 2.0 /spl mu/A.     

New 5.8-GHz circularly polarized retrodirective rectenna arrays for wireless power transmission

This paper proposes two new circularly polarized retrodirective rectenna arrays, including a 2 /spl times/ 2 array and a 4 /spl times/ 4 array. A proximity-coupled microstrip ring antenna is used as the retrodirective rectenna array element, which can automatically block harmonic signals up to the third order from reradiating by the rectifying circuit. These arrays are printed on a Rogers Duroid 5880 substrate of /spl epsiv//sub r/=2.2 with a two-layer structure, with a total thickness of 1.5748 mm (or 62 mil). The new retrodirective rectenna array can track the incoming power source signals automatically and is less sensitive to the power incident angle variations, i.e., main-beam alignment deviation. It can provide a nearly constant dc output voltage within /spl plusmn/10/spl deg/ and 90% dc output voltage within /spl plusmn/45/spl deg/. The conversion efficiencies of the two arrays are 73.3% and 55%, respectively, when the power density is 10 mW/cm/sup 2/. The retrodirective rectenna array can be used in the low-power density applications for microwave wireless power transmissions.     

Equivalent Circuit of the Bolometer Detector

A small-signal dynamic equivalent circuit is established for the output voltage of a dc-biased bolometer (barretter) detector. The circuit consists of a voltage generator /spl upsi//sub g/, whose output is an undistorted replica of the incident RF-power modulation envelope, followed by a series resistor R/sub 1/ of dynamic origin, a shunt capacitor C that represents heat storage in the bolometer wire, and a series resistor R/sub 0/ equal to the dc resistance, usually 200 ohms. The resistance R/sub 1/ is independent of signal level, and is typically about 220 ohms for an 8.75-mA bolometer and about 120 ohms for a 4.5-mA bolometer. At a modulation frequency f/sub m/ near 0 Hz, the equivalent audio source impedance of the bolometer is R/sub 1/ +R/sub 0/. The common belief that the source impedance is R/sub 0/ in the weak-signal case is, therefore, refuted. Formulas are derived giving v/sub g/ / /P/sub RF/ and R/sub 1/ as functions of basic, easily determined bolometer parameters. The time constant for open-circuit load is /spl tau//sub oc/= R/sub 1/C, where /spl tau//sub oc/ is determined best by measurement, since catalog values of /spl tau//sub oc/ often are seriously in error. The capacitance is C=/spl tau//sub oc/ / /R/sub 1/. With one type of bolometer /spl tau//sub oc/ measures about 110 /spl mu/s, while various catalogs state values of 250 to 350 /spl mu/s. The equivalent circuit is confirmed quantitatively by measurements of output voltage and source impedance versus modulation frequency.     

Low-voltage high-drive CMOS current feedback op-amp

A novel CMOS current feedback op-amp is presented. The solution works using a low supply voltage and provides a wide input/output swing as well as a high current driving capability. Experimental results from a prototype implemented in a 0.35-/spl mu/m technology and powered with 1.5 V are also given. The circuit exhibits a better than 500 kHz closed-loop bandwidth and a /spl plusmn/1 mA current drive capability.     

Low supply voltage high-performance CMOS current mirror with low input and output voltage requirements

This paper presents a scheme for the efficient implementation of a low supply voltage continuous-time high-performance CMOS current mirror with low input and output voltage requirements. This circuit combines a shunt input feedback and a regulated cascode output stage to achieve low input resistance and very high output resistance. It can be used as a high-precision current mirror in analog and mixed signal circuits with a power supply close to a transistor's threshold voltage. The proposed current mirror has been simulated and a bandwidth of 40 MHz has been obtained. An experimental chip prototype has been sent for fabrication and has been experimentally verified, obtaining 0.15-V input-output voltage requirements, 100-/spl Omega/ input resistance, and more than 200-M/spl Omega/ (G/spl Omega/ ideally) output resistance with a 1.2-V supply in a standard CMOS technology.     

A five-terminal plus or minus 15-V monolithic voltage regulator

A five-terminal /spl plusmn/15-V monolithic voltage regulator has been developed that incorporates internal frequency compensation and internally provides a /spl plusmn/1 percent output voltage tolerance. In addition, a thermally symmetric layout design of the chip has been used to eliminate the detrimental effects of thermal feedback on the die and ensure that the complementary tracking output voltages will be independent of the power dissipation in the series pass power transistors. Complete fault protection is accomplished by providing the power transistors with good dc safe operating area, internally limiting the short circuit output currents, and accurately limiting the junction temperature to within 10/spl deg/C of the specified maximum limit. Also, a new Zener diode geometry is employed that significantly reduces the noise associated with the reference voltage.     

A regulated charge pump with small ripple voltage and fast start-up

A regulated charge pump circuit is realized in a 3.3-V 0.13-/spl mu/m CMOS technology. The charge pump exploits an automatic pumping control scheme to provide small ripple output voltage and fast start-up by decoupling output ripple and start-up time. The automatic pumping control scheme is composed of two schemes, an automatic pumping current control scheme and an automatic pumping frequency control scheme. The former automatically adjusts the size of pumping driver to reduce ripple voltage according to output voltage. The latter changes the pumping period by controlling a voltage-controlled oscillator (VCO). The output frequency of the VCO varies from 400 kHz to 600 kHz by controlling the input bias voltage of the VCO. The prototype chip delivers regulated 4.5-V output voltage from a supply voltage of 3.3 V with a flying capacitor of 330 nF, while providing 30 mA of load current. The area is 0.25 mm/sup 2/ and the measured output ripple voltage is less than 33.8 mV with a 2-/spl mu/F load capacitor. The power efficiency is greater than 70% at the range of load current from 1 to 30 mA. An analytical model for ripple voltage and recovery time is proposed demonstrating a reasonable agreement with SPICE simulation results.