A fast pump-down VBB generator for sub-1.5-V DRAMs

Based on the study about the previously developed V_BB generators, a fast pump-down and high-efficiency V_BB generator with a cross-coupled hybrid pumping circuit 2 (CHPC2) is presented in this paper. CHPC2 takes only the advantages from the previous generators, eliminating the disadvantages. CHPC2 shows a |V_BB|/V_CC as large as 98% even at low V_CC =0.9 V, strongly ensuring that it is suitable at sub-1.5-V DRAM applications. Moreover, CHPC2 exhibits a better pumping efficiency and a larger pumping current over the previous ones with a wide range of the load resistance at V_CC=1.2 V     

High-speed sensing scheme for CMOS DRAMs

A significant improvement in sensing speed over the half-V_DD bit-line precharge sensing scheme is obtained by precharging the bit line to approximately 2/3 V_DD. The 2/3-V_DD sensing scheme also results in higher-bit-line capacitance, asymmetrical bit-line swing, and higher power consumption. However, the speed advantage of 2/3-V_DD sensing may outweigh the disadvantages and can significantly improve DRAM performance. For the unboosted word-line case, symmetrical bit-line swing can be retained by limiting the bit-line downward voltage swing through a clamping circuit added to the sense amplifier, resulting in almost no loss of stored charge in a cell. The authors show that the 2/3-V_DD sensing with a limited bit-line swing has several distinct advantages over the half-V_DD sensing scheme and is particularly suitable for high-performance high density CMOS DRAMs     

Efficient back-bias generator with cross-coupled hybrid pumpingcircuit for sub-1.5 V DRAMs

A very efficient back-bias generator with cross-coupled hybrid pumping circuit (CHPC) is presented. Though the CHPC is based on the previously suggested hybrid pumping circuit (HPC). Its cross-coupled nature which can totally eliminate the sacrificial voltage loss in storing the supply voltage (V_CC) at the capacitor shows a much better pumping efficiency and increased pumping current over the HPC for V_CC ranging from 3.3 to 0.9 V     

Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMs

A sensing scheme in which the bit line is precharged to half V/SUB DD/ is introduced for CMOS DRAMs. The proposed circuitry uses a PMOS memory array and incorporates the following features: (1) a complementary sense amplifier consisting of NMOS and PMOS cross-coupled pairs; (2) clocked pulldown of the latching node; (3) complementary clocking of the PMOS pullup; (4) full-sized dummy cell generation of reference potential for sensing; (5) shorting transistor to equalize precharge potential of bit lines; and (6) depletion NMOS decoupling transistors for multiplexing bit lines. The study shows that the half-V/SUB DD/ bit-line sensing scheme has several unique advantages, especially for high-performance high-density CMOS DRAMs, which compared to the full-V/SUB DD/ bit-line sensing scheme used for NMOS memory arrays or the grounded bit-line sensing scheme for PMOS arrays in CMOS DRAMs.     

A precharged-capacitor-assisted sensing (PCAS) scheme with novellevel controllers for low-power DRAMs

A precharged capacitor-assisted sensing (PCAS) scheme suitable for low-power DRAM using boosted-sense ground (BSG) is proposed. In this scheme, the data on bitlines are sensed with the assistance of precharged capacitors. Precise data level generation is achieved with sense speed 4.2 ns faster than the conventional scheme in the case that bitline swing is 1.4 V. Necessary decoupling capacitors can be efficiently implemented in memory arrays by using junction capacitors between well and substrate so that the area penalty of decoupling capacitors can be minimized. To keep sensed data stable, two types of level controllers are introduced. A voltage downconverter (VDC) with a current mirror discharger (CMD) compensates for the change of both data levels during write/read operations. A level controller with charge transfer amplifier (CTA) prevents the BSG level from falling during the row active period. The two level controllers greatly improve data-retention characteristics     

Cell-plate-line/bit-line complementary sensing (CBCS) architecturefor ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced     

Hot-carrier reliability in double-implanted lightly doped drain devices for advanced DRAMs

Hot-electron degradation in short-channel (0.50 mu m and 0.83 mu m) double-implanted lightly doped drain (DI-LDD) devices was characterised using DC stress tests. Compared to lightly doped drain (LDD) devices of the same effective channel length L/sub eff/, the measurements indicate that channel hot-electron injection is more prevalent in devices with the p/sup +/-pocket implant due to a higher peak channel electric field. Degradation is more severe in both the drain current and transconductance. However, an improvement in short-channel effects was seen in DI-LDD devices over LDD devices. For the same L/sub eff/, the punch-through voltage was higher and the subthreshold swing lower for the DI-LDD devices.<>     

Embedded trench DRAMs for sub-0.10-μm generation by usinghemispherical-grain technique and LOCOS collar process

For the future system on chip era, the embedded DRAM is one of the most important devices. Since the kinds of device increase and each device must be produced from only 10000 wafers, it is difficult to withdraw the investment cost to fabricate each device. To suppress the investment cost, the devices must be shrunk by changing the integration and the materials as little as possible. In this paper, we propose the trench capacitor scaling strategy. We show that the strategy achieves 30 fF/cell for the 0.08 μm trench and reduces the cost of ownership (COO) and raw process time (RPT) of the 0.08 μm trench to 80% of 0.18-μm trench, with an investment of only $1.6 M. It is achieved by the LOCOS collar process and HSG technique     

A flexible redundancy technique for high-density DRAMs

The limitations of conventional redundancy techniques are pointed out and a novel redundancy technique is proposed for high-density DRAMs using multidivided data-line structures. The proposed technique features a flexible relationship between spare lines and spare decoders, as well as lower probability of unsuccessful repair. With this technique the yield improvement factor of 64-Mb DRAMs and beyond is estimated to be more than twice that with the conventional technique in the early stages of production     

A built-in Hamming code ECC circuit for DRAMs

An error checking and correcting (ECC) technique that checks multiple cell data simultaneously and allows fast column access is described. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty, and can be applied to a 16-Mbit DRAM with 20% chip area increase and less access-time penalty. The soft error rate has been estimated to be about 100 times smaller than that of the basic horizontal-vertical parity-code ECC technique     

A new on-chip converter for submicrometer high-density DRAMs

The converter described is a feedback-type voltage regulator which supplies a reduced voltage to an entire RAM circuit. A novel timing activation method was introduced to save power. The converter has been implemented on an experimental 4-Mb dynamic RAM. It was found that an even faster access time and higher reliability compared to a conventional design could be achieved by using an on-chip voltage converter and shorter channel transistors. This voltage converter is suitable for high-density, high-speed, and high-reliability DRAMs with submicrometer transistors.     

A study of pipeline architectures for high-speed synchronous DRAMs

The performances of SDRAMs with different pipeline architectures are examined analytically on the basis of the time required to refill the on-chip cache of a Pentium CPU. The analysis shows that the cycle time of the conventional pipeline structures cannot be reduced because of its difficulty in distributing the access time evenly to each pipeline stage of the column address access path. On the contrary, the wave pipeline architecture can make the access path evenly divided and can increase the number of pipeline stages to achieve the shortest cache refill time. But the wave congestion at the output terminal of the wave pipeline path caused by access time fluctuation narrows the valid time window. The parallel registered wave pipeline architecture can remove the effect of access time fluctuation so that the cycle time is defined only by the data pulse width. If the data pulse width t_w<2 ns, even 500-MHz clock frequency can be obtained     

A dual-phase-controlled dynamic latched amplifier for high-speedand low-power DRAMs

A dual-phase-controlled dynamic latched (DDL) amplifier for a differential data transfer scheme designed to achieve both high speed and low power in DRAMs is described. This circuit reduces the excessive operating margin caused by device fluctuations by using a pair of dynamic latched amplifiers, controlled by a dual-phase clock, to automatically correct the output data. Two circuit technologies are used in the DDL amplifier to achieve 200-MHz operation in a 1-Gb SDRAM using 0.13-μm technology: a cycle-time-progressive control circuit that increases the operating frequency and a shared DDL amplifier technique that reduces the area penalty of the DDL amplifier. These techniques and circuits reduce the access time to 10 ns, which is 1.2 ns less than that of the conventional dynamic amplifier, while also reducing the operating current to less than 10% that of the static amplifier     

Low voltage circuit design techniques for battery-operated and/orgiga-scale DRAMs

This paper describes a charge-transferred well (CTW) sensing method for high-speed array circuit operation and a level-controllable local power line (LCL) structure for high-speed/low-power operation of peripheral logic circuits, aimed at low voltage operating and/or giga-scale DRAMs. The CTW method achieves 19% faster sensing and the LCL structure realizes 42% faster peripheral logic operation than the conventional scheme, at 1.2 V in 15 Mb-level devices. The LCL structure realizes a subthreshold leakage current reduction of three or four orders of magnitude in sleep mode, compared with a conventional hierarchical power line structure. A negative-voltage word line technique that overcomes the refresh degradation resulting from reduced storage charge (Q_s) at low voltage operation for improved reliability is also discussed. An experimental 1.2 V 16 Mb DRAM with a RAS access time of 49 ns has been successfully developed using these technologies and a 0.4-μm CMOS process. The chip size is 7.9×16.7 mm² and cell size is 1.35×2.8 μm²     

Highly manufacturable advanced gate-stack technology for sub-45-nm self-aligned gate-first CMOSFETs

Issues surrounding the integration of Hf-based high-/spl kappa/ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-/spl kappa/ CMOSFETs with wide process latitude. HfO/sub 2/ of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A high-temperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-/spl kappa/ stack, integrating two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n- and pMOS and gate-stack dry etch. We demonstrate that a dual metal gate CMOSFET yields high-performance devices even with a conventional gate-first approach if an appropriate metal separation between band-edge metal for nMOS and pMOS is incorporated. Optimization of dry-etch process enables gentle and complete removal of two different metal gate stacks on ultrathin high-/spl kappa/ layer.     

一种空中联合作战频谱感知方法

现代联合作战中,有效的频谱感知可以提高电磁态势感知能力,避免自扰互扰问题的出现。通过将传统集中式频谱感知架构中的非指挥节点拆分为次级节点和三级节点,以能量感知为基本方法并对感知信息进行二次融合,形成了分布式频谱感知模型。仿真结果表明,分布式频谱感知模型不但在感知性能上较传统感知模型提高5%左右,而且在感知性能相同的条件下,指挥节点的带宽拥堵率仅为传统模型的10%~20%,达到了提高频谱利用率的目的。     

Accurate RF extraction method for resistances and inductances of sub-0.1 /spl mu/m CMOS transistors

An accurate RF method using a linear regression of high-frequency Z-parameter equations at zero gate voltage is developed to extract resistances and inductances of sub-0.1 /spl mu/m MOSFETs. Good agreement between the measured and modelled S-parameters is observed up to 30 GHz, verifying the accuracy of the RF method.     

A new active position sensing method for ropeless elevator

Traditional cable driven elevators perform poorly in high-rise buildings because the weight of the cable limits the payload, and its elasticity degrades control performance. Further, it is not mechanically possible to include several elevator cars in the same hoistway because of the cable. However such multi-car elevator systems are desirable since they reduce passenger waiting time and reduce the space requirements of the elevator system. A promising solution is to use long armature linear motors spanning the hoistway to directly drive elevator cages. In such applications, the mover position sensing method must be explicitly addressed since most active position sensing methods require traveling cables, which are also an obstacle for multi-car elevator systems.In this paper, the linear-motor active position sensing method is formally introduced and the principle of operation, design and real-time operation methods are presented. The proposed method is used to measure the position of the mover of a long armature permanent magnet linear synchronous motor requiring no active components on the mover, thus traveling cables are eliminated. The principle of operation is inspired by linear variable differential transformer: A magnetic shunt positioned at a fixed distance ahead of the mover deforms the magnetic field created by one of the armature coils. The deformation can be determined by measuring the induced voltages on the neighboring coils, and the position of the shunt, and thus the mover, can be calculated.A design method for the optimal dimensions of the shunt for a given armature to provide long measurement range and small maximum position error is presented, accompanied by a real-time measurement algorithm that will enable the motor to be driven using the method. Finally the method is verified by simulations and experimental results conducted on a full scale linear-motor elevator prototype that was constructed in the laboratory.     

A new method for the channel-length extraction in MOSFETs with sub-2-nm gate oxide

A simple method to extract the effective channel length in deep-submicrometer devices with sub-2-nm gate oxide thickness is presented. The method uses the measured gate current from accumulation to strong inversion. It is easy to implement, fast, and accurate.     

A high-density dual-port memory cell operation and arrayarchitecture for ULSI DRAMs

A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis of the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to the complete pipelining operation of a DRAM array and a refresh-free DRAM core are also discussed