A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cellefficiency and noise immunity

A 2.5-V 288-Mb packet-based DRAM with 32 banks and 18-DQ organization architecture achieving a peak bandwidth of 2.0-GB/s at V _DD=2.25 V and T=100°C has been developed using (1) an area- and performance-efficient chip architecture with a mixture of high-speed interface circuits with DRAM peripheral circuits to increase cell efficiency; (2) a multilevel controlled bitline equalizing scheme and a distributed sense amplifier driving scheme to enhance DRAM core timing margin while increasing the number of cells per wordline for cell efficiency over the previous subwordline driving scheme; (3) a flexible column redundancy scheme with multiple fuse boxes instead of excessive spare memory cell arrays for 143 internal I/O architecture; and (4) optimized I/O circuits and pin parasitic design including pad and package to maximize the operating frequency     

An automatic temperature compensation of internal sense ground forsubquarter micron DRAM's

This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage levels maintain a small subthreshold leakage current for a memory cell transistor (MC-Tr), and a distributed BSG (DBSG) scheme and a column decoded sensing (CDS) scheme achieve the effective scaling. These schemes can set the DRAM array free from the leakage current problem and the influence of temperature variations. Therefore, parameters for the MC-Tr, threshold voltage (V _th), and the boosted voltage for the gate bias can be scaled down, and it is possible to determine the V_th of the MC-Tr simply (0.45 V at K=0.4) for the satisfaction of the small leakage current, for high speed and stable operation, and for high reliability (V_PP is below 2 V_CC). They are applicable to subquarter micron DRAM's of 256 Mb and more     

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM

Circuit techniques for battery-operated DRAMs which cover supply voltages from 1.5 to 3.6 V (universal V_cc), as well as their applications to an experimental 64-Mb DRAM, are presented. The universal-V_cc DRAM concept features a low-voltage (1.5 V) DRAM core and an on-chip power supply unit optimized for the operation of the DRAM. A circuit technique for oxide-stress relaxation is proposed to improve high-voltage sustaining characteristics while only scaled MOSFETs are used in the entire chip. This technique increases sustaining voltage by about 1.5 V compared with conventional circuits and allows scaled MOSFETs to be used for the circuits, which can be operated from an external V_cc of up to 4 V. A two-way power supply scheme is proposed to suppress the internal voltage fluctuation within 10% when the DRAM is operated from external power supply voltages ranging from 1.5 to 3.6 V. An experimental 1.5-3.6-V 64-Mb DRAM is designed based on these techniques and fabricated by using 0.3-μm electron-beam lithography. An almost constant access time of 70 ns is obtained. This indicates that battery operation is a promising target for future DRAMs     

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-μm CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71×1.20 μm ², and the chip size is 15.91×9.06 mm². A typical access time under 3.3 V power supply voltage is 29 ns     

Low voltage circuit design techniques for battery-operated and/orgiga-scale DRAMs

This paper describes a charge-transferred well (CTW) sensing method for high-speed array circuit operation and a level-controllable local power line (LCL) structure for high-speed/low-power operation of peripheral logic circuits, aimed at low voltage operating and/or giga-scale DRAMs. The CTW method achieves 19% faster sensing and the LCL structure realizes 42% faster peripheral logic operation than the conventional scheme, at 1.2 V in 15 Mb-level devices. The LCL structure realizes a subthreshold leakage current reduction of three or four orders of magnitude in sleep mode, compared with a conventional hierarchical power line structure. A negative-voltage word line technique that overcomes the refresh degradation resulting from reduced storage charge (Q_s) at low voltage operation for improved reliability is also discussed. An experimental 1.2 V 16 Mb DRAM with a RAS access time of 49 ns has been successfully developed using these technologies and a 0.4-μm CMOS process. The chip size is 7.9×16.7 mm² and cell size is 1.35×2.8 μm²     

An experimental 1.5-V 64-Mb DRAM

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V_CC voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 μm² crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 μm electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs     

Variable VCC design techniques forbattery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V_CC level; (2) compensation of DC generators, V_BB and V_PP, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V_CC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M×8) by simulation     

A high-speed, small-area, threshold-voltage-mismatch compensationsense amplifier for gigabit-scale DRAM arrays

A high-speed small-area DRAM sense amplifier with a threshold-voltage (V_T) mismatch compensation function is proposed. This sense amplifier features a novel hierarchical data-line architecture with a direct sensing scheme that uses only NMOS transistors in the array, and simple V_T mismatch compensation circuitry using a pair of NMOS switching transistors. The layout area of the sense amplifier is reduced to 70% of that of a conventional CMOS common I/O sense amplifier due to the removal of PMOS transistors from the array. The readout time is improved to 35% of that of a conventional CMOS sense amplifier because of direct sensing and a 1/10 reduction in V_T mismatch. This sense amplifier eliminates the sensitivity degradation and the area overhead increase that are expected in gigabit-scale DRAM arrays     

Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier

A novel bitline sensing scheme is proposed for low-voltage DRAM to achieve low power dissipation and compatibility with low-voltage CMOS. One of the major obstacles in low-voltage DRAM is the degradation of data-retention time due to low signal level at the memory cell, which requires power-consuming refresh operations more frequently. This paper proposes an offset-cancellation sense-amplifier scheme (OCSA) that improves data-retention time significantly even at low supply voltage. It also improves die efficiency, because the proposed scheme reduces the number of sense amplifiers by supporting more cells in each sense amplifier. Measurements show that the data-retention time of the proposed scheme at 1.5-V supply voltage is 2.4 times of the conventional scheme at 2.0 V.     

Limitations and challenges of multigigabit DRAM chip design

This paper describes the limitations and challenges involved in designing gigabit DRAM chips in terms of high-density devices, high-performance circuits, and low-power/low-voltage circuits. The key results obtained are as follows. 1) For formation of a MOSFET shallow junction, which suppresses threshold voltage (V_T) variation and offset voltage of sense amplifiers, reduction in ion-implantation energy and process temperature is essential. Also, the keys in terms of area, speed, stable cell operation, and ease of fabrication are use of low-resistivity multilevel metal wiring and high permittivity materials and three-dimensional memory cells to reduce a difference in height between the memory cell array and the surrounding peripheral circuits. 2) For creation of a high speed, the keys are memory-subsystem technology such as pipeline operation, wide-bit I/O, low-voltage interfaces, and high-density packaging. Embedded DRAM further enhances the speed and throughput by using massively parallel processing of signals on a large number of data-lines and reducing internal bus capacitances. 3) For power reduction, the key continues to be reduction of the data-line dissipating charge through both partial activation of multidivided data-lines and lowering of the data-line voltage. Ultralow-voltage operation, essential to drastic power reduction, can be achieved by subthreshold-current reduction circuits such as source-gate backbiasing, multi-V_T, dynamic V_T, and node-boosting schemes     

A 64-Mb DRAM with meshed power line

A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t_RAS=50 ns (typical) at V_cc=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V_SS shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4-μm CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM     

Approaches to extra low voltage DRAM operation by SOI-DRAM

The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFETs with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFETs to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-μm 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V     

A high-density dual-port memory cell operation and arrayarchitecture for ULSI DRAMs

A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis of the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to the complete pipelining operation of a DRAM array and a refresh-free DRAM core are also discussed     

A divided/shared bit-line sensing scheme for ULSI DRAM cores

A new dynamic RAM (DRAM) signal sensing principle, a divided/shared bit-line (DSB) sensing scheme, is proposed. This sensing scheme provides folded bit-line sensing operation in a crosspoint-type memory cell array. The DSB scheme offers a high-density DRAM memory core with the common-mode array noise eliminated. A bit-line architecture based on this new sensing principle and its operation are demonstrated. A divided/pausing bit-line sensing (DIPS) scheme, which is an application of this DSB principle to the conventional folded bit-line type of memory cell arrangement, is also proposed. The DIPS architecture achieves complete pausing states for alternate bit lines throughout the active period. These alternate pausing bit lines shield the inter-bit-line coupling noise between active bit lines. Here the inter-bit-line coupling noise is eliminated by a slight architectural change to the conventional folded bit-line memory cell array. These new memory core design alternatives provide high-density DRAM memory cores suitable for the 64-Mb level and beyond. with the memory array noise reduced significantly     

A circuit technology for high-speed battery-operated 16-Mb CMOSDRAM's

A battery-operated 16-Mb CMOS DRAM with address multiplexing has been developed by using an existing 0.5-μm CMOS technology. It can access data in 36 ns when powered from a 1.8-V battery-source, and 20 ns at 3.3 V. However, this device requires a mere 57 mA of operating current for an 80-ns cycle time and only 5 μA of standby current at 3.3 V. To achieve both high-speed and low-power operation, the following four circuit techniques have been developed: 1) a parallel column access redundancy (PCAR) scheme coupled with a current sensing address comparator (CSAC), 2) an N&PMOS cross-coupled read-bus-amplifier (NPCA), 3) a gate isolated sense amplifier (GISA) with low V_T, and 4) a layout that minimizes the length of the signal path by employing the lead on chip (LOC) assembly technique     

Cell-plate-line/bit-line complementary sensing (CBCS) architecturefor ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced     

A 1-Gb DRAM for file applications

A time-shared offset-canceling sensing scheme, a defective word-line Hi-Z standby scheme, and a flexible multimacro architecture have been developed for 1-Gb DRAM. These circuit technologies have been applied to a 1-Gb DRAM for file applications employing 0.25 μm CMOS process technology, a diagonal bit-line cell, and a two-stage pipeline circuit technique. In this DRAM, a 30% chip size reduction and a 400-MB/s data transfer rate have been achieved. A 100% improvement in yield has been estimated by Monte-Carlo simulation. The 1-Gb DRAM die size is 936 mm². The cell size is 0.54 μm². The operating current is 58 mA at 2 V and 100 MHz     

Low-voltage, high-speed circuit designs for gigabit DRAMs

This paper describes several new circuit design techniques for low V_CC regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (ΔV_BL ) as well as the V_GS margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-μm twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t_RAC) of 28 ns at V_cc=1.5 V and T=25°C has been obtained     

High-performance embedded SOI DRAM architecture for the low-powersupply

This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM. The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the low voltage range. In our proposed stressless SOI DRAM array, the applied electric field to the gate oxide of the memory-cell transistor can he relaxed. The crucial problem that the gate oxide of the embedded-DRAM process must be thicker than that of the logic process can be solved. As a result, the performance degradation of the logic transistor can be avoided without forming the gate oxides of the memory-cell array and the logic circuits individually. In addition, the data retention characteristics can be improved. Secondly, we propose the body-bias-controlled SOI-circuit architecture which enhances the performance of the logic circuit at sub-1.2-V power supply voltage, Experimental results verify that the proposed circuit architecture has the potential to reduce the gate-delay time up to 30% compared to the conventional one. This proposed architecture could provide high performance in the low-voltage embedded SOI DRAM     

A low-noise folded bit-line sensing architecture for multigigabitDRAM with ultrahigh-density 6F2 cell [CMOS design]

The 6F² cell is widely known for its small area, but its sensing is unstable due to the large array noise. A new low-noise sensing scheme for a 6F² DRAM cell is proposed, employing two noise reduction methods: the divided sense and combined restore scheme and the bit-line noise absorbing scheme. They can reduce word-line to bit-line as well as bit-line to bit-line coupling noises. The bit-line noise is reduced to 85% of that of a conventional scheme with only 0.05% area overhead, which is negligible compared to the area saving by using a 6F² cell. The total chip area and the sensing time can he reduced to 85 and 87%, respectively, compared to conventional DRAM. A 2 kbit DRAM test chip with a 6F² cell Is fabricated using 256 M DRAM technology, and its stable operations are confirmed