A monolithic, standard CMOS, fully differential optical receiver with an integrated MSM photodetector

This paper presents a realization of a silicon-based standard CMOS, fully differential optoelectronic inte grated receiver based on a metal-semiconductor-metal light detector (MSM photodetector). In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photo generated currents. The optoelectronic integrated receiver was designed and implemented in a chartered 0.35 μm, 3.3 V standard CMOS process. For 850 nm wavelength, it achieves a 1 GHz 3 dB bandwidth due to the MSM pho todetector's low capacitance and high intrinsic bandwidth. In addition, it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to -3 dB frequency.     

Asynchronous 250-Mb/s optical receivers with integrated detector instandard CMOS technology for optocoupler applications

A high-speed ten-channel optical receiver, integrated in a standard 0.6-μm CMOS technology, is presented. Each data channel consists of a spatially modulated light detector (SML-detector) and a low-offset receiver. The SML detector has a much higher intrinsic bandwidth than a conventional photodiode junction implemented in standard CMOS. One channel of the ten is sacrificed and used as a reference to define the threshold level for the other channels. The optical receiver can handle up to 250 Mb/s of noncoded data (including dc) per channel at 20 μW average light input power (λ=860 nm). Power dissipation per channel is only 4 mW. When combined with appropriate light emitters, a compact and low-cost optocoupler can be obtained with improved speed performance compared to existing optocouplers     

Experimental characterization of integrated optical wireless components

Line of sight optical links can provide extremely high bandwidth communications between terminals, but in order to maintain alignment between transmitter and receiver, tracking is required. In this letter, we report results from a "solid-state" tracking transmitter and receiver. The transmitter consists of a custom complementary metal-oxide-semiconductor (CMOS) integrated circuit that is flip-chip bonded to a seven-element resonant cavity light-emitting diode. The receiver uses a custom seven-element InGaAs detector array that is flip-chip bonded to a CMOS integrated circuit. Results from an initial link demonstration show overall system operation at 100 Mb/s/channel, for Manchester coded data.     

An instantaneous response CMOS optical receiver IC with widedynamic range and extremely high sensitivity using feed-forwardauto-bias adjustment

An instantaneous response CMOS optical-receiver IC is described with wide input dynamic range and high sensitivity. In a TCM (time compression multiplexing)-TDMA (time division multiple access) fiber-optic subscriber system, a receiver should be able to handle burst-data packets with different amplitude. This requires quick response and a wide dynamic range. Instantaneous response is achieved with a new feed-forward auto-bias adjustment technique. In addition, multistaged offset compensation provides a wide dynamic range without any external elements and adjustments. Using these design techniques, an optical receiver IC was fabricated in a standard 0.8-μm CMOS technology. The receiver has a wide dynamic range of more than 25 dB for burst-mode optical input at 29 Mb/s. It has high transimpedance gain of 150 dBΩ and high sensitivity of -42 dBm with stable operation for FET threshold voltage and power supply voltage fluctuation     

基于CMOS传感器的光ID信息服务系统模型

CMOS图像传感器具有功耗低、尺寸小,以及价格便宜等优点,目前已被广泛应用于智能手机中.采用CMOS图像传感器作为可见光通信的接收装置,有利于技术的推广和实用化.文章首先介绍了采用CMOS传感器作为可见光通信接收机的原理,接着针对当前国内外研究中存在的问题提出了信号增强算法,最后验证了算法的可行性和适用性,并由此提出了一套光ID信息服务系统模型.     

CMOS RF receiver system design: a systematic approach

A unified system-level design methodology for highly integrated CMOS radio frequency receiver design is introduced. This complete system-level design methodology is targeted to minimize the total power consumption of the receiver. System-level design techniques which can be used to derive the overall receiver radio specifications and study noise and linearity performance of receivers are presented. Then, a few circuit examples of building blocks in receiver signal chain are analyzed to show a linear relationship between power and dynamic range of the blocks. The result is then used to derive the optimal system specification distribution among receiver signal chain building blocks yielding the minimum total receiver power consumption for a given system performance. The theory and an actual CMOS Bluetooth receiver design are compared showing very good agreement.     

A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination

In this work, a novel circuit topology for a Low-Voltage Differential Signaling (LVDS) output driver with reduced power consumption is proposed. Also, a low-signal current version of the LVDS driver working with lower supply voltage is proposed along with a compatible differential current-mode receiver. Both the drivers and the receiver feature active-terminated ports that eliminate the need for a dedicated passive terminator for matching. An asymmetric impedance network on the output side of the driver selectively eliminates any reflections coming from the channel while providing a high output impedance to the outgoing signal. For a target signal swing at the receiver input, the proposed termination scheme helps to reduce the driver signal current to up to a third of the current required by a conventional LVDS driver using a passive termination at the output. The asymmetric impedance network consists of a scaled-down replica driver that drives a common drain stage acting as the load for the main driver. The proposed driver topology meeting all LVDS specifications has been implemented in 3.3-V thick-gate CMOS technology. Simulation results show an achievable data rate of 5 Gb/s while transmitting over a 7.5-in FR4 PCB backplane trace for a target BER of 10⁻¹⁵, with power consumption equal to 17.8 mW, which is 25% less than a conventional LVDS driver with passive source end termination producing the same voltage swing at the receiver input. The low-current version of the driver has been implemented in 0.18-μm 1.8-V digital CMOS technology and shows similar performance over the same channel with a power consumption of 4.5 mW.     

高灵敏度CMOS光电集成接收机设计

设计了一个由调节型级联跨阻抗放大器(TIA)和双光电二极管(DPD)构成的CMOS光电集成(OEIC)接收机.具体分析了这个光电集成接收机的噪声和灵敏度及其相互关系.接收机中的噪声主要是电路中电阻的热噪声和MOS器件的闪烁噪声.提出了优化接收机灵敏度的方法.通过低成本的CSMC 0.6μm CMOS工艺流片并对芯片进行了测试.从测试眼图可知,该CMOS光电集成接收机可工作在1.25GB/s的传输速率下,灵敏度为-12dBm.     

An integrated 0.35 μm CMOS optical receiver with clock and data recovery circuit

This paper presents an integrated optical receiver that operates at 1 Gb/s in a standard 0.35 μm digital CMOS technology. The receiver consists of an integrated CMOS photodetector, a transimpedance amplifier (TIA) followed by a post-amplification stage and a dual-loop clock and data recovery (CDR) circuit. At a wavelength of 860 nm, the circuit requires an average light input power of −19.7 dBm to obtain a bit-error rate (BER) of 10⁻¹². The complete receiver consumes a total power of approximately 155 mW from a 3.3-V supply. The core circuit area is 0.85×1.32 mm².     

Integrated optical receiver with beam localisation

The performance of optical receivers is degraded by misalignment and defocusing of the incident light beam on a detector. The presented integrated optical receiver solves the alignment and defocusing problem using optoelectronic light beam localisation. A demonstrator is realised in a standard CMOS technology     

High-speed, burst-mode, packet-capable optical receiver andinstantaneous clock recovery for optical bus operation

This paper describes an enhanced performance version of a high-speed burst-mode compatible optical receiver and its application to 622-Mb/s optical bus operation in conjunction with an instantaneous clock recovery scheme. The receiver is fabricated in a 12 GHz f_t silicon bipolar technology and consists of a differential transimpedance amplifier with an auto-threshold level controller and a high-speed quantizer. Using an InGaAs avalanche photodiode, the typical burst mode sensitivity is around -34 dBm (10^-9 BER) at bit rates up to 1.5 Gb/s with a dynamic range of 26 db for both pseudorandom and burst signals. The results using a laser beam modulated by a high-speed external modulator indicate that the receiver can be operated at bit rates higher than 2 Gb/s. With a worst-case self-resetting time <50 ns for the threshold control circuit, the receiver is usable for optical packet communication where data signals with varying optical power are employed. This receiver was demonstrated in a 622-Mb/s optical bus application where the clock signal was recovered from the packet data signal using a novel high-speed CMOS instantaneous clock recovery IC     

A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator

A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 /spl mu/m CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply.     

Optical broadcast and clock distribution for multi-chip-modules

In this letter, we report a new architecture for clock and broadcast distribution using optical interconnect components, such as vertical cavity surface emitting lasers (VCSEL) and pin photodiodes with benefits of diffractive optical elements (DOE) fan-out. A two-bit-large bus for broadcast or clock distribution demonstration is presented using collective wiring technologies and MCM hybridization process in a standard BGA package. Diffractive optical elements allow one to four distribution scene through an optical plate. Specific laser drivers for VCSELs and photodiode receiver are realized in complete CMOS 0.6 μm transmitter and receiver chips.     

A SONET STS-3c user network interface integrated circuit

Two different design implementation techniques were used to produce a functionally complex high performance synchronous optical network (SONET) synchronous transmission signal (STS)-3c (155.52 Mb/s) user network interface (UNI) chip in cost-effective 1 μm CMOS technology. The CMOS chip functions as an STS-3c transmitter and receiver and can interface to the STS-3c line in either bit-serial or byte-parallel data format. The transmitter creates a SONET STS-3c frame structure including the necessary framing and control bytes. The receiver performs frame detection, several performance monitoring functions, and payload processor interpretation. In addition to SONET overheads, both the transmitter and receiver provide payload asynchronous transfer mode (ATM) mapping signals to the user. The user can choose between serial operation at 155.52 Mb/s or parallel operation at 19.44 Mbyte/s. Test results show that the experimental integrated circuit performs successfully at serial data rates of up to 300 Mb/s     

A 4.5-mW 900-MHz CMOS receiver for wireless paging

An ultralow-power 900-MHz receiver implemented on a single CMOS chip is intended for use in FLEX wireless paging. The receiver uses an indirect conversion to zero intermediate frequency (IF) to suppress the flicker noise corner in the second mixer to less than 1 kHz. Various techniques for low-power design, most of them unique to CMOS, are presented, with theoretical support and experimental verifications. The receiver, fabricated in a 0.25-μm standard CMOS process, achieves 7.4-dS noise figure at 1.6 kHz with -25-dBm IIP3 on a 1.5 V supply. The voltage-controlled oscillator (VCO) has a phase noise of -98 dBc/Hz at 25 kHz offset. The nominal receiver bias current of 3 mA is higher than the expected 2 mA because of unanticipated losses in coupling capacitors     

A single-chip 900 MHz CMOS receiver front-end with a highperformance low-IF topology

An analog receiver front end chip realized in a 0.7 μm CMOS technology is presented. It uses a new, high performance, downconverter topology, called double quadrature downconverter, that achieves a phase accuracy of less than 0.3° in a large passband around 900 MHz, without requiring any external component or any tuning or trimming. A high performance low-IF receiver topology is developed with this double quadrature downconverter. The proposed low-IF receiver combines the advantages of both the classical IF receiver and the zero IF receiver: an excellent performance and a very high degree of integration. In this way, it becomes possible to realize a true fully integrated receiver front-end that does not require a single external component and which is, different from the zero-IF receiver, nonetheless totally insensitive to parasitic baseband signals and self-mixing products     

A direct-to-digital frequency translating sigma-delta based receiver

In this brief, a new form of direct conversion sigma-delta modulator-based receiver is presented. Distortion reduction is obtained as a result of including the down conversion mixers into the sigma-delta loop. The use of an equivalent low-pass model simplifies the analysis and design. The proposed architecture is very attractive for integration into any suitable CMOS technology. Simulation of a discrete equivalent model shows agreement with predicted performance.     

Moving average filter for spur reduction in subsampling fractional PLLs

A mono-bit digital receiver circuit for instantaneous frequency measurement is presented. The circuit is co-designed with Indium Phosphide Double Heterojunction Bipolar Transistor and complementary metal oxide semiconductor (CMOS) devices. The chip is fabricated by InP/CMOS three-dimensional (3D) heterogeneous integration using the wafer-level bonding technique. The measurable signal frequency within?+?15 to???25 dBm power is up to 7.5 GHz with a 14-GHz clock. Compared to an integrated circuit (IC) with a traditional InP or CMOS technologies, the proposed chip could benefit from both InP and CMOS technology. In the heterogeneous integration, InP devices provide high operating frequency, broad signal bandwidth, and large input signal dynamic range, while CMOS devices achieve complex function with low power consumption. In this way, the system FoM is improved for a mono-bit digital receiver while the system power consumption is kept the same. This work also shows the great potential of the 3D heterogeneous integration for the high-performance mixed-signal and multifunction radio-frequency ICs.

     

A Fully Integrated 60GHz Four Channel CMOS Receiver with 7GHz Ultra-Wide Bandwidth for IEEE 802.11ad Standard

In this paper, a fully integrated CMOS receiver frontend for high-speed short range wireless applications centering at 60GHz millimeter wave （mmW） band is designed and implemented in 90nm CMOS technology. The 60GHz receiver is designed based on the super-heterodyne architecture consisting of a low noise amplifier （LNA） with inter-stage peaking technique, a single- balanced RF mixer, an IF amplifier, and a double-balanced I/Q down-conversion IF mixer. The proposed 60GHz receiver frontend derives from the sliding-IF structure and is designed with 7GHz ultra-wide bandwidth around 60GHz, supporting four 2.16GHz receiving channels from IEEE 802.1lad standard for next generation high speed Wi- Fi applications. Measured results show that the entire receiver achieves a peak gain of 12dB and an input 1-dB compression point of -14.SdBm, with a noise figure of lower than 7dB, while consumes a total DC current of only 60mA from a 1.2V voltage supply.     

Fully differential optoelectronic integrated receiver imple-mented by 0.35 μm standard CMOS process

A high-bandwidth, high-sensitivity fully differential optoelectronic integrated receiver is implemented in a chartered 3.3 Vstandard 0.35 um analog CMOS process. To convert the incident light into a pair of fully differential photo-currents, anovel fully differential photodetector is proposed, which is composed of two completely identical photodiodes. The mea-surement results show that the receiver achieves a 1.11 GHz 3 dB bandwidth and a -13 dBm sensitivity for a 10-12 bit error at1.5 Gb/s data rate under illumination by 850 nm incident lights.